We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about Moore's Law and the impact of it on the industry today.

The assertion that Moore made in April 1965 Electronics paper was:"Thus there is a minimum cost at any given time in the evolution of the technology. At present, it is reached when 50 components are used per circuit. But the minimum is rising rapidly while the entire cost curve is falling (see graph below)." 

"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years."

Clearly Moore's law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays - transistors) to achieve minimum cost will double every year.
The reduction of cost per component for many years was directly related to the reduction in feature size - dimensional scaling. But many other technology improvements made important contributions as well, such as increasing the wafer size from 2" all the way to 12".
But many observers these days suggest that 28nm will be the optimal feature size with respect to cost for many years to come. Below are some charts suggesting so:

And more analytical work by IBS’ Dr. Handel Jones

Graphically presented in the following chart

Or as nicely drawn by Globalfoundries

Recently EE Times reported that EUV Still Promising on IMEC's Road Map. IMEC provided a road map to transistor scaling all the way to 5nm, as illustrated in the following chart:

Yes, we probably can keep on scaling but, clearly, at escalating complexity and with completely new materials below 7nm. As dimensional scaling requires more advanced lithography it is clear that costs will keep moving up, and the additional complexity of transistor structures and all other complexities associated with these extreme efforts will most likely drive the costs even higher.
Looking at the other roadmap chart provided by IMEC and focusing on the SRAM bit cell in the first row, the situation seems far worse:

Since at 28 nm SRAM bit cell is already 0.081μm2, this chart indicates that future transistor scaling is barely applicable to the SRAM bit cell, which effectively is not scaling any more.
Unfortunately, most SoC die area is already dominated by SRAM and predicted to be so even more in the future, as illustrated by the following chart:

Source:. Y. Zorian, Embedded memory test and repair: infrastructure IP for SOC yield, in Proceedings the International Test Conference (ITC), 2002, pp. 340–349
Dimensional scaling was not an integral part of Moore's assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore. The following chart captures Samsung’s view of the future of dimensional scaling for NV memory, and it seems relevant to the future of logic scaling just as well.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi underlines the milestone for monolithic 3D in the semiconductor road map 2019.

In the recent CEA Leti day, that took place as part of Semicon West 2013, Laurent Malier, Leti CEO presented his "A look at the coming Decade".
Slide 15 of the presentation provides Leti vision for CMOS roadmaps as presented here:

Monolithic 3D is presented on the road-map as the technology to follow 7nm process node.

Early this year we blogged - IEDM 2012: The pivotal point for monolithic 3D ICs, it is quite reassuring to see monolithic 3D now as part of the industry road-map. As we discussed than the memory vendors are already gearing up for volume production of the 3D NAND as reported recently Toshiba to Build Fab for 3D NAND Flash, leveraging monolithic 3D cost reduction advantage. It only makes senses for the CMOS market to follow. Doubters would ask why the industry would introduce new dimension to a road map that has been extremely successful for over 40 years. And the answer is very simple - because it is successful any more. We are all aware that the escalating costs of lithography had diminished transistors cost reduction as illustrated in the following ASML chart

But even if we ignore these issues we should remember that "Atoms don't scale" (as was phrased by Bernie Meyerson of IBM), and we are quickly approaching these limit as is presented by the following Intel chart:

And accordingly Mike Mayberry, director of its component research at Intel, said at the very recent IMEC Technology Forum "...has looked down the highway of conventional silicon development and reckons things become foggy beyond about the 7-nm node".
In fact Mike in his March 2013 presentation titled "Pushing Past the frontiers of Technology" clearly also present the monolithic 3D on his road map as the following slides illustrates

As was very well stated by Mark Bohr - Senior Fellow of Technology and Manufacturing Group and a Director of Process Architecture and Integration of Intel:

We have a guest contribution today from Ze'ev Wurman, the Chief Software Architect of MonolithIC 3D Inc. In this blog-post, Ze'ev discusses some industry implications of recent events relating to science education. Ze'ev has participated in developing California’s education standards and assessments in mathematics since the mid-1990s. Between 2007 and 2009, he served as a senior policy adviser at the U.S. Department of Education. Throughout their development Wurman analyzed the Common Core mathematics standards drafts for the Pioneer Institute. In the summer of 2010 he served on the California Academic Content Standards Commission that reviewed the adoption of Common Core for California. Wurman earned his BSEE and MSEE degrees from the Technion in Israel, and he is a recipient of the Eliyahu Golomb Israel Security Award.