It is commonly believed that the fundamental limit to MOSFET feature-size scaling is direct source-drain tunneling. We may hit this limitation around the 5nm node. Is that the end of the road for CMOS Scaling?
We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel was at Applied Materials for almost two decades, and served as Chief Technology Officer and Chief Marketing Officer for many groups there.
Shekhar Borkar, a Fellow at Intel, and Andrew Chien, the VP of Intel Research, wrote a provocative and much-circulated article titled "The Future of Microprocessors" a few months back. Let's discuss this article today...
We have a guest contribution today from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. In this post, Zvi shares his perspective on where the industry is going.
Do semiconductor startups still make sense? A panel of high-profile Silicon Valley Venture Capitalists, Investment Bankers and Executives debated this issue last Thursday...
We have a guest contribution today from Ze'ev Wurman, MonolithIC 3D Inc.'s Chief Software Architect. Ze'ev discusses yield issues with 3D stacked chips.
Device Variability and Scaling
We have a guest contribution today from Paul Lim, MonolithIC 3D Inc.'s Principal Device Engineer. In this post, Paul discusses device variability and how it changes with scaling.
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