Others work relevant to monolithic 3D IC
- 3D stacking offers an extension for Moore's Law, E&T Magazine by Chris Edwards, February 16th, 2015.
- Leti Devices Workshop, Leti San Francisco, December 14th, 2014.
- True 3-D Chip Harness Nanotubes, EE Times Article by R. Colin Johnson, December 19th, 2014.
- Novel Low Temperature 3D Wafer Stacking Technology for High Density Device Integration, by Dr. Ionut Radu, Soitec, Bucharest 2013.
- Going Up! Monolithic 3D As An Alternative to CMOS Scaling, by Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti), April 9th, 2014.
- Rise of the Monolithic 3D Chip, IEEE Spectrum, February 24th, 2014.
- CMOS technologies: Our most power efficient solution today and our vision toward 10nm node and beyond, Leti Devices Workshop, December 8, 2013
- High-Density Integration of Functional Modules Using Monolithic 3D-IC Technology, Dept. of Electrical and Computer Engineering, Georgia Tech, Atlanta GA, USA and Qualcomm Research, San Diego, CA, USA
- Low Power Design, Past and Future (monolithic 3D), By Bob Brodersen (UCB), Anantha Chandrakasan (MIT) and Dejan Markovic (UCLA).
- Cramming more components onto integrated circuits, By Gordon E. Moore.
- Monolithic 3D chip fabricated without TSVs, Solid State Technology blog post.
- New 3D Approaches: Enabling Technologies for Nanoelectronic Devices, Soitec at CEA-LETI 15thAnnual Review
- 3D-IC Integration (CMP 3D IC presentation)
- Helping Flash Memory Grow Up: Etch Technology For The Terabit Era (The Applied Materials Blog)
- CMP 3D-IC Integration (Cirsuit's Multi Projects Webpage) .
- Monolithic 3D-ICs with single grain Si thin film transistors (Solid State Electronics An International Journal)
- Cost Efficient Wafer-Level Stacking Technologies (Chip Scale Review - Digital Edition - January - February 2013, pg. 26-30)
- Building block for wafer-level 3D Integration (Solid State Technology Magazine)
- Michio Kaku: Tweaking Moore’s Law (Video)
Papers and Presentations
- "Monolithic 3D Advantage", Free E-book, November 2014.
- Precision Bonders - A Game Changer for Monolithic 3D, IEEE S3S 2014, October 2014.
- Monolithic 3D Integrated Circuits, NCCAVS Joint User Group Meeting, June 12, 2014
- A disruptor to the semiconductor industry The Monolithic 3D IC, ITHERM 2014, May 2014.
- Monolithic 3D Integrated Circuits - Zvi Or-Bach Technion Lecture, Israel, March 2014 (video lecture).
- "Der Ausweg aus dem Skalierungs-Dilemma?", Electronic Information, Germany, January 2014.
- "THE MONOLITHIC 3D-IC", Slide Presentation at the 2013 S3S Conference, October 2013.
- "Practical Process Flows for Monolithic 3D", 3D Plenary Talk held at the 2013 S3S Conference, October 2013.
- "The Monolithic 3D Advantage", Tutorial presented at the 2013 IEEE 3DIC Conference, October 2013.
- "Thermal Considerations for Monolithic Integration of Three-Dimensional Integrated Circuits", Poster presented at the 2013 S3S Conference, October 2013.
- "Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC", Paper presented at the 2013 IEEE 3DIC Conference, October 2013.
- "MonolithIC 3D™ - the Future of Semiconductor Scaling", Presentation at Semicon West 2013 - SIF, July 2013.
- "Monolithic 3D Memory - NAND Flash, DRAM and R-RAM", Free E-book, March 2013.
- "Monolithic 3D - In General", Free E-book, March 2013.
- "Monolithic 3D Advantage", Free E-book, February 2013
- "The Monolithic 3D Advantage", Paper, January 2013
- "Cooling Three-Dimensional Integrated Circuits using Power Delivery Networks", Paper at the IEDM Conference, Dec 2012 (paper) (slides).
- "Monolithic 3D Integrated Circuits", Guest Lecture at Technion City, January 1st, 2013
- "The First Step to Take When You Consider Taking Your Scientific Breakthrough to Startup", Guest Lecture at Technion City, January 1st, 2013
- MonolithIC 3D-ICs RCAT, HKMG , RCJLT and 3D Embedded eDRAM Approach, MonolithIC 3D Inc., Free E-book, December 2012
- "The Short, Medium and Long-Term Path to the 3D Ecosystem", Panel Discussion at EDPS, April 5th, 2012
- "Monolithic 3D-ICs with Single Crystal Silicon Layers", Invited paper at the IEEE 3DIC conference, 2012 (paper) (slides)
- "Fine-Grained 3D Integration", Invited talk at the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society, January 11, 2012
- "Monolithic 3D - The effective alternative to Dimensional Scaling", Invited lecture at the Technion - Israel Institute of Technology, November 21, 2011
- "3D: Where are we today; Where are we going; and How will you get there with us?", Invited talk at the 9th International System-on-Chip (SoC) Conference, Exhibit & Workshops in Southern California, November 2-3, 2011
- "Monolithic 3D-ICs: The Effective Alternative to Dimensional Scaling", Invited keynote speech at the Intl. Electronics Forum in Seville, October 7, 2011
- "Resistive RAM: Technology and Market Applications", Invited Talk at the University of California, Berkeley, September 2011
- "Monolithic 3D Integrated Circuits", Invited Talk at Intel Research (Photonics Technology Lab), July 2011
- "Monolithic 3D Integrated Circuits", Invited Talk at the CMOS Emerging Technologies Workshop, June 2011
- "Monolithic 3D DRAM Technology", Invited Talk at the American Vacuum Society Workshop on 3D Packaging, June 2011
- "The Monolithic 3D-IC", Invited Talk at the 3D Workshop at the Intl. Conference on Technology & Instrumentation in Particle Physics, June 2011
- "Monolithic 3D FPGAs", Invited Talk at the Intl. Memory Workshop, May 2011
- "Monolithic 3D Integrated Circuits", Invited Talk at the Technical University of Munich, May 2011
- "Monolithic 3D Integrated Circuits", appears in Issue #37 of Future-Fab International, April 2011
- "Monolithic 3D Technology: Nu3D-IC, A Semiconductor Industry Game Changer", Invited Presentation at the 3D-ASIP Conference, Dec 2010.
- "Resistive RAM: Technology and Market Applications", Invited Presentation at the IEEE-SCV Electron Devices Society, Nov 2010.
- "3D-FPGA: The Path to ASIC-like Density, Power and Performance", Invited Presentation at the Applied Materials 3D Interconnect Symposium, Jan 2010.
Patents
Only issued patents are listed below. We have 50+ patents pending at the US Patent Office.
- US Patent 8,956,959 Method of manufacturing a semiconductor device with two monocrystalline layers, Issued February 17th, 2015.
- US Patent 8,921,970 Semiconductor device and structure, Issued December 30th, 2014.
- US Patent 8,912,052 Semiconductor device and structure, Issued December 16th, 2014.
- US Patent 8,907,442 System comprising a semiconductor device and structure, Issued December 9th, 2014
- US Patent 8,901,613 Semiconductor device and structure for heat removal, Issued December 2nd, 2014.
- US Patent 8,902,663 Method of maintaining a memory state, Issued December 2nd, 2014.
- US Patent 8,846,463 Method to construct a 3D semiconductor device, Issued September 30th, 2014.
- US Patent 8,836,073 Semiconductor device and structure, Issued September 16th, 2014.
- US Patent 8,823,122 Semiconductor and optoelectronic devices, September 2nd, 2014.
- US Patent 8,803,206 3D semiconductor device and structure, August 12th, 2014.
- US Patent 8,754,533 Monolithic three-dimensional semiconductor device and structure, June 17th, 2014.
- US Patent 8,753,913 Method for fabricating novel semiconductor and optoelectronic devices, June 17th, 2014.
- US Patent 8,742,476 Semiconductor device and structure, June 3rd, 2014.
- US Patent 8,709,880 Method for fabrication of a semiconductor device and structure, April 29th, 2014.
- US Patent 8,703,597 Method for fabrication of a semiconductor device and structure, April 22nd, 2014.
- US Patent 8,686,428 Semiconductor device and structure, April 1st, 2014.
- US Patent 8,687,399 Semiconductor device and structure, April 1st, 2014.
- US Patent 8,674,470 Semiconductor device and structure, March 18th, 2014.
- US Patent 8,669,778 Method for design and manufacturing of a 3D semiconductor device, March 11th, 2014.
- US Patent 8,664,042 Method for fabrication of configurable systems, March 4th, 2014.
- US Patent 8,642,416 Method of forming three dimensional integrated circuit devices using layer transfer technique, February 4, 2014.
- US Patent 8,581,349 3D memory semiconductor device and structure, November 12th, 2013.
- US Patent 8,574,929 Method to form a 3D semiconductor device and structure, November 5, 2013.
- US Patent 8,557,632 Method for fabrication of a semiconductor device and structure, October 15th, 2013.
- US Patent 8,541,819 Semiconductor device and structure, Issued September 24th, 2013
- US Patent 8,536,023 Method of manufacturing a semiconductor device and structure, Issued September 17, 2013
- US Patent 8,492,886 3D integrated circuit with logic, Issued July 23rd, 2013.
- US Patent 8,476,145 Method of fabricating a semiconductor device and structure, Issued July 2, 2013
- US Patent 8,461,035 Method for fabrication of a semiconductor device and structure, Issued June 11, 2013
- US Patent 8,450,804 Semiconductor device and structure for heat removal, Issued May 28th, 2013
- US Patent 8,440,542 Semiconductor device and structure, Issued May 14th, 2013
- US Patent 8,427,200 3D semiconductor device, Issued April 23rd, 2013
- US Patent 8,405,420 System comprising a semiconductor device and structure, Issued March 26, 2013
- US Patent 8,395,191 Semiconductor device and structure, Issued March 12, 2013
- US Patent 8,384,426 Semiconductor device and structure, Issued February 26, 2013
- US Patent 8,379,458 Semiconductor device and structure , Issued February 19, 2013
- US Patent 8,378,715 Method to construct systems, Issued February 19, 2013
- US Patent 8,378,494 Method for fabrication of a semiconductor device and structure, Issued February 19, 2013
- US Patent 8,373,439 3D semiconductor device, Issued February 12, 2013
- US Patent 8,373,230 Method for fabrication of a semiconductor device and structure, Issued February 12, 2013
- US Patent 8,362,482 Semiconductor Device and structure, Issued January 29, 2013
- US Patent 8,362,800 3D semiconductor device including field repairable logics, Issued January 29, 2013
- US Patent 8,298,875 Method for fabrication of a semiconductor device and structure, Issued October 30, 2012
- US Patent 8,294,159 Method for fabrication of a semiconductor device and structure, Issued October 23, 2012
- US Patent 8,283,215 Semiconductor and optoelectronic devices, Issued October 9, 2012
- US Patent 8,273,610 Method of constructing a semiconductor device and structure, Issued September 25, 2012
- US Patent 8,258,810 3D semiconductor device, Issued September 4, 2012
- US Patent 8,237,228 System comprising a semiconductor device and structure, Issued August 7, 2012
- US Patent 8,203,148 Semiconductor device and structure, Issued June 19, 2012
- US Patent 8,163,581 Semiconductor and optoelectronic devices, Issued April 24, 2012
- US Patent 8,153,499 Method for fabrication of a semiconductor device and structure, Issued April 10, 2012
- US Patent 8,148,728 Method for fabrication of a semiconductor device and structure, Issued April 3, 2012
- US Patent 8,115,511 Method for fabrication of a semiconductor device and structure, Issued February 14, 2012
- US Patent 8,114,757 Semiconductor device and structure, Issued February 14, 2012
- US Patent 8,058,137 Method for fabrication of a semiconductor device and structure, Issued November 15, 2011
- US Patent 8,026,521 Semiconductor device and structure, Issued September 27, 2011
- US Patent 7,986,042 Method for fabrication of a semiconductor device and structure, Issued July 26, 2011
- US Patent 7,960,242 Method for fabrication of a semiconductor device and structure, Issued June 14, 2011
- US Patent 7,964,916 Method for fabrication of a semiconductor device and structure, Issued June 21, 2011
