We were invited to join a panel session titled: "Monolithic 3D: Will it Happen and if so..." at IEEE 3D-Test Workshop Oct. 9th, 2015. So we are happy to see monolithic 3D on the title, but then the title also suggests that the industry is wondering is it real or is it a pipe dream. The doubts are in opposition to companies such as Qualcomm who strongly advocate it, and the support CAE which Leti, in collaboration with ST Micron and IBM,are presenting monolithic 3D as the "low-cost scaling" for 2018. See chart below from July 2015 Leti Day.

The doubts might relate to the technology challenge illustrated by the following slide:

The upcoming IEEE S3S Conference 2015 in Sonoma, CA, on October 5th thru 8th provides comprehensive coverage of R&D activities in the monolithic 3D space. It starts with short courses on Monday. On Tuesday there will be a planery talk - "Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration" by Prof. Tsu-Jae King Liu, followed by "3D-Invited Monolithic 3D Alternative Technologies" session with representatives of Qualcomm, CEA Leti, Taiwan National Nano Device Laboratories, Stanford University and UCLA presenting and updating on the state of monolithic 3D technologies currently being developed arround the world as being illustrated in the following slide:  

Then on Wednesday we would have an additional session of “Invited Talks on M3DI” followed by a “Selected Papers on M3DI” session.
In short the most comprehensive technical event on the emerging monolithic 3D technologies. 
Yet – the question “Monolithic 3D: Will it Happen…” is still being asked.
The concerns are that the leading edge vendors are too busy these days still with dimensional scaling and if anything else could be done it seems that FD-SOI would be it; while trailing edge fabs, are in most cases, avoiding any major transistor process development. The recent failure of Suvolta could be an indication of this reality.  
Here comes Game-Changing 2.0. A major technology innovation to be unveiled on Wednesday by MonolithIC 3D in a paper titled: “Modified ELTRAN® - A Game Changer for Monolithic 3D”. This paper will present a novel use of the ELTRAN® process developed by Canon Inc. about 20 years ago primarily for SOI applications. Using ELTRAN (Epi. Layer Transfer) techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change the current frontline fab process. This flow is further simplified and could be integrated with the game changing monolithic 3D flow introduced last year which leverages the emerging precision bonders, such as EVG’s Gemini® XT FB. This flow provides a natural path for product innovation and an unparalleled competitive edge. In addition, this game-changer breakthrough offers a very cost competitive flow.  The following chart illustrates the original use of ELTRAN process for the fabrication of SOI wafers: 

In the “Invited Talks on M3DI” we will have an opportunity to learn from the inventor of the ELTRAN process Dr. Takao Yonehara, currently with Applied Materials, in his talk “Epitaxial Layer Transfer Technology and Application”. Prior to Applied Materials Dr. Yonehara worked with Solexel, a Silicon Valley start up, to deploy the ELTRAN process for low cost solar cell fabrication. This talk would be followed by Prof. Joachin Burghartz of Institute for Microelectronics Stuttgart, talk on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” where they use a variation of the flow in small scale production.
The semiconductor industry are bifurcating these days into one a segment that follows aggressive scaling for few super-value applications supported by very few vendors, while the bulk of the industry is enhancing old fabs while targeting the main stream applications and the emerging IoT opportunities. Further enhancing these older fabs with monolithic 3D would be a most effective return on investment. As indicate by the CEA slide above – “low cost scaling” and by a paper to be presented by Global Foundries showing monolithic 3D provides Power-Performance-Area (PPA) equivalent to dimension scaling at fraction of the cost. The Game-Changing 2.0, mean that without need for major process R&D efforts or new equipment the path for 3D scaling is now open with enormous advantages for IoT. And accordingly my answer to the above question is encompassed in the title of the invited talk prior to the panel “Monolithic 3D is Already Here – the 3D NAND – and Now it would be Easy to Adapt it for Logic”
In addition the other division – SOI and SubVt provide good complementing technology updates for the power performance objectives that are so important for these emerging markets. So do come to the S3S and enjoy unique key technologies update with the great wine and country pleasures of Sonoma Valley.

The forthcoming IEEE S3S Conference 2015 ,Sonoma, CA, on October 5th thru 8th, will focus on key technologies for the IoT era. It is now accepted that the needs for the emerging IoT market are different from those which drive the high volume PC and Smart-Phone market. The following Gartner slide illustrates this industry bifurcation where traditional mass products follow the – ever more expensive – scaling curve, while IoT devices, with their focus on cost, power, flexibility and accessibility, will seek place near its minimum.

The current high volume is focus on handful of foundries and SoC vendors driving a handful of designs at extremely high development cost each, processed at the most advanced nodes, with minimal processing options. In contrast, the emerging IoT market is looking for older nodes with lower development costs, broad range of process options, with many more players both at the foundry side and the design side.

For the IoT market the key enabling technologies are extreme low power, as enabled by SOI and sub-threshold design, integrating with multiple sensor technologies and communication technologies that ca be enabled by 3D integrations. All of these combined in forming the IEEE S3S unified conference.

This year conference includes many exciting papers and invited talks. It starts with three plenary talks: 

• Gary Patton – CTO of Global Foundries: New Game Changing Product Applications Enabled by SOI
  
• Geoffrey Yeap – VP at Qualcomm.: The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology
  
• Tsu-Jae King Liu – Chair of EE Division, Berkeley University: Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration
  

The following forecast from BI Intelligence suggest that the semiconductor technologies that are in good fit for the future market of IoT should be prime interest for the semiconductors professionals

Quoting Jim Walker, Research VP at Gartner presented on the “Foundry vs. SATS: The Battle for 3D Wafer Level Supremacy”. He argued 3D ICs are the key enabler of performance and small form factor of products required for IoT.


Hence the coming IEEE S3S conference provides important opportunity to catch up and learn about these technologies.

Let me share with you some nuggets from the monolithic 3D integration part of the conference:

Prof. Joachin Burghartz of the Institute for Microelectronics Stuttgart will deliver an invited talk on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” that will present a process technology to fabricate flexible devices 6-20 micron thin. This process flow is currently in manufacturing in their Stuttgart fab, as described below;

Another interesting discussion will be presented by NASA scientist Dr. Jin-Woo Han who will describe “Vacuum as New Element of Transistor”. These transistors are made of “nothing” and could be constructed within the metal stack, forming monolithic 3D integration with silicon-based fabric underneath.

In his invited talk titled “Emerging 3DVLSI: Opportunities and Challenges” Dr. Yang Du will share with us Qualcomm views on monolithic 3D IC which they term 3DVLSI and could be illustrated by the following figure which seems very fitting for IoT applications 

Globalfoundries will present joint work with Georgia Tec. titled “ Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs”. This work again shows that monolithic 3D can provide a compelling alternative to dimension scaling as illustrated by the following chart.

We will present “Modified ELTRAN® - A Game Changer for Monolithic 3D” that shows a practical flow for exiting fab to process monolithic 3D devices using their exiting transistor process and equipment. This flow leverages the work done by Canon about 20 years back called ELTRAN, for Epitaxial Layer Transfer. The following slide illustrates the original ELTRAN flow.

By deploying the elements of this proven process, a multilayer device could be built first by processing a multilayer transistors fabric at the front end of line, and then process the metal stacks from both top and bottom sides.

The conference includes many more interesting invited talks and papers covering the full spectrum of IoT enabling technologies. In addition, the conference offers short course on SOI application and monolithic 3D integration, and a fundamental class on low voltage logic.

New technologies are an important part of the future of semiconductor industry, and a conference like the S3S would be a golden opportunity to step away for a moment from the silicon valley, and learn about non-silicon and silicon options that promise to shape the future. 

The forthcoming IEEE S3S Conference 2015 ,Sonoma, CA, on October 5th thru 8th, will focus on key technologies for the IoT era. It is now accepted that the needs for the emerging IoT market are different from those which drive the high volume PC and Smart-Phone market. The following CEA Leti slide illustrates this industry bifurcation where traditional mass products follow the – ever more expensive – scaling curve, while IoT devices, with their focus on cost, power, flexibility and accessibility, will seek place near its minimum.

The current high volume is focus on handful of foundries and SoC vendors driving a handful of designs at extremely high development cost each, processed at the most advanced nodes, with minimal processing options. In contrast, the emerging IoT market is looking for older nodes with lower development costs, broad range of process options, with many more players both at the foundry side and the design side.

For the IoT market the key enabling technologies are extreme low power, as enabled by SOI and sub-threshold design, integrating with multiple sensor technologies and communication technologies that ca be enabled by 3D integrations. All of these combined in forming the IEEE S3S unified conference.

This year conference includes many exciting papers and invited talks. It starts with three plenary talks:

• Gary Patton – CTO of Global Foundries: New Game Changing Product Applications Enabled by SOI
  
• Geoffrey Yeap – VP at Qualcomm.: The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology
  
• Tsu-Jae King Liu – Chair of EE Division, Berkeley University: Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration
  

Prof. Tsu-Jae King will present in her talk an extremely low power nano-mechanical switch that could be fabricated within the metal stack. The slide below describes some of its characteristics.

Prof. Joachin Burghartz of the Institute for Microelectronics Stuttgart will deliver an invited talk  on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” that will present a process technology to fabricate flexible devices 6-20 micron thin. This process flow is currently in manufacturing in their Stuttgart fab, as described below;

Another interesting discussion will be presented by NASA scientist Dr. Jin-Woo Han who will describe “Vacuum as New Element of Transistor” As shown below

These transistors are made of “nothing” and could be constructed within the metal stack, forming monolithic 3D integration with silicon-based fabric underneath.

The conference includes many more interesting invited talks and papers covering the full spectrum of IoT enabling technologies. In addition, the conference offers short course on SOI application and monolithic 3D integration, and a fundamental class on low voltage logic.

Among the papers we will present “Modified ELTRAN® - A Game Changer for Monolithic 3D” that shows a practical flow for exiting fab to process monolithic 3D devices using their exiting transistor process and equipment. This flow leverages the work done by Canon about 20 years back called ELTRAN, for Epitaxial Layer Transfer. By deploying the elements of this proven process, a multilayer device could be built first by processing a multilayer transistors fabric at the front end of line, and then process the metal stacks from both top and bottom sides. The following slide illustrates the resulting monolithic 3D structure.

New technologies are an important part of the future of semiconductor industry, and a conference like the S3S would be a golden opportunity to step away for a moment from the silicon valley, and learn about non-silicon and silicon options that promise to shape the future.