We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi adds information to his previous blog post: Dimension Scaling and the SRAM Bit-Cell.

Embedded SRAM will scale from 0.09µm² at 22-20nm node to 0.06µm² at 11-10nm node. In other words only 30% reduction instead of the 4x reduction expected of historical dimension scaling, to roughly 0.02µm²!!!

In our previous blog (attached below) that followed ISSCC 2013 we saw some early indication of this slowdown.  Yet we were still surprised to realize how bad it really is. This might explain why after resisting IBM and other pushes for embedded DRAM, Intel announced few month ago that its Haswell processor will incorporate embedded DRAM after all.

Another point from this ASML slide is the adaption of monolithic 3D by the NAND Flash vendors. We believe this is a start of a trend, and that logic vendors has now one more reason to follow it.

The IEEE International Solid-State Circuit Conference Feb 17-21, 2013 just ended in San Francisco last week, and the issue of dimensional scaling as it relates to EUV and future per transistor device cost was an important topic in the plenary session. One important, and perhaps overlooked, aspect of the industry’s scaling issue relates to the future of the SRAM bit-cell within this framework of dimensional scaling. We would like to shine some light on this impending issue.

As widely reported in the industry and articulated by ASML’s Executive VP & CTO Martin van den Brink at ISSCC 2013, there is substantial evidence that without EUV the cost of logic transistors is most likely going up with scaling. One slide he used to illustrate this is below:

The above slide arrived after Martin had presented another non-encouraging slide, showing the same view from three companies: a Broadcom chart of increasing cost per gate correlated with dimensional scaling, together with the now famous Nvidia chart of no more crossover of transistor cost below 28nm, and third a GlobalFoundries chart showing some limited value for EUV.

We may attribute Martin statements to ASML interest in promoting EUV, but since ASML has already received significant EUV participation from INTEL, Samsung and TSMC, it might indicate further bumps are on the road to bringing EUV to market. We don't know if EUV will ever become real, but we do know very well that it is been delayed, and delayed again, and delayed again. It was made public recently that EUV has probably already missed the 10nm process node -“10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries.
An even more interesting slide was presented by van den Brink:

This chart brings up an important aspect of dimensional scaling that has not been discussed much before - the scaling of the SRAM bit-cell.  According to this chart, the SRAM bit-cell size might not be reduced from the 20nm to 10 nm node, and might even get larger at 7nm as it may need more than 8 transistors. (Sound familiar? Fabs are doing the same with BEOL metallization scaling…little or none)

Modern logic devices demand a significant amount of embedded SRAM. In fact, more than 50% of the typical logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010) 

The dominant embedded SRAM bit-cell architecture has been the 6 transistor cell (6T). And for many years this very cell has been hand-crafted using special design rules independently developed by foundries for every new technology node. It makes sense: the SRAM cell is a unique structure that does not obey normal logic design rules as it drives output against output anytime a write cycle is being performed. In many cases it is the SRAM cell that is the most sensitive portion of the logic device to process parameter variations and this sensitivity greatly impacts end device yield.

It well known that scaling the SRAM bit-cell has become harder and harder. Some vendors have already moved away from the 6T bit-cell in preference to the 8T (eight transistors) bit-cell.  ISSCC 2013 had a significant number of papers that were presented using 8T SRAM.  The few papers who kept the 6T SRAM embedded in their logic devices were forced to add read/write support circuits and additional overhead to enable the 6T bit-cell to function reliably.

Since SRAM bit scaling is now not able to keep up with logic scaling, the overall end device cost scaling could be even more disappointing than the transistor or gate cost illustrations above. 

Of course, well aware of this trend, IBM has been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that in their 32nm product line the use of the embedded DRAM has given IBM the equivalent of a process node scaling benefit. Yet, as of now, most other vendors have not adopted eDRAM due to the process complexity and cost it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimensional scaling as the DRAM capacitor will be very hard to scale, the extra power for supporting DRAM will not be available and the cost of advance process development to add in extra complexity will be too high.

Accordingly we can learn from the recent ISSCC that dimensional scaling is facing the cost challenges we were aware of before in addition to new challenges that we might not have been aware of: the cost and the active/passive power handicaps due to the incompatibility of the 6T SRAM  bit-cell with scaling.

As we have suggested before, now that monolithic 3D is practical, we could advance and maintain Moore's Law by augmenting dimensional scaling with 3D IC scaling. We could enjoy depreciated equipment charges for more years and much lower R&D engineering outlays that would bring down production and development costs, and also enjoy improvements to power and performance.

Another exciting option is to replace the 6T SRAM bit-cell with the 1T bi-stable floating body memory cell invented by Zeno Semiconductor.  The Zeno bit-cell provides two stable states, analogous to an SRAM while only consuming ~20% area of a traditional 6T SRAM and requires considerably less power.  The area and power savings over a traditional 6T SRAM improve further with scaling.  Most excitingly the Zeno bit-cell is compatible with existing logic processes.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses EE Time's article about: "Moore's Law seen hitting big bump at 14 nm".

The EE Times article covering Imec's Luc van den Hove keynote talk at IEDM 2012 reports: "Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase - and still carry a hefty cost premium - due to the lack of next-generation lithography". Van den Hove provided the following slide photo as an illustration:

Yet, in an article about Intel's 22nm IEDM presentation, EE Times is quoting Mark Bohr of Intel: "Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel "is nowhere near that," he said. "Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm," Bohr said.


So who is right between those two giants?

Could it be that both of them are?

In a recent blog titled "Is the Cost Reduction Associated with Scaling Over?" we presented charts clearly supporting Luc van den Hove, IMEC's CEO, position. The following slide from an IBM presentation includes an NVidia chart (which we also discussed in another blog, Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies? ).

Accordingly, it would seem that TSMC wafer costs are in line with Luc and so is the case with IBM.

GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium yesterday (Dec. 11) also acknowledged that their 14nm node will have a 20nm node metal pitch and, just like GlobalFoundries, a similar die size and increase in per-transistor cost.
In other words, it seems that the Luc van den Hove keynote is in-line with the cost road map of the non-Intel foundries!

Intel might indeed be different, yet something did cause Intel to take what seems like an extreme measure, when it put $4.1B in ASML just recently.

If, however, Mark Bohr has not been misled by the Intel accounting department, and the Intel process is still providing a nice cost reduction at every node of scaling, then clearly Intel has a true competitive edge relative to all other foundries. I have no doubts that Intel has filed enough patents to protect its unique process advantage, but then I wonder why did Mark say: "However...we don't intend to be in the general-purpose foundry busines ... [and] I don't think the [foundry] volumes ever will be huge [for Intel]."
If Mark Bohr is right, with such a competitive edge Intel should aggressively expand its foundry business, which would achieve both a great profit margin and rapid business growth. Now that Intel is looking for a new CEO its Board should consider it as a major criterion for who should lead Intel into the future.

P.S.

Clearly, dimensional scaling (and its cost reducing benefits) is not what it used to be, and the market appetite for cheaper-faster-better consumer-oriented products grows stronger. Both Intel and non-Intel fabs should start development of monolithic 3D technology.  ;-)

"Only the paranoid survive"

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about Qualcomm overtaking Intel in market capitalization.

On Nov 9, 2012 we learned that Qualcomm overtook Intel in market capitalization. Quite shocking news if one considers that Intel’s revenue is almost three times that of Qualcomm and its net margin is more than twice that of Qualcomm. Clearly investors evaluate Qualcomm using a different scale than what they use for Intel, as is evidenced by Qualcomm’s P/E of 20.12 vs. Intel's mere 9.07. EE Times explained it in an article that day stating: "In the eyes of investors who have driven up its market capitalization, the fact that Qualcomm is a fabless company relieves it of the burden of having to invest billions of dollars each year in process development and wafer fabs." However, given that TSMC, a pure foundry, has a P/E of 15.67, it behooves us to look for another explanation. It’s also worth noting that TSMC had a revenue growth of 2% in the last year, far less than Intel's 25.6%, and its net income actually went down vs. a net income growth by Intel of 213%!

My explanation is that it is all about IP strength. I will expand on it in the rest of this blog but as prime evidence I offer SanDisk, who sports a P/E of 20.78  yet has continued to invest heavily, together with its partner Toshiba, in fab capacity upgrades.

Let’s first look at the previous two decades as Intel grew consistently year after year while riding the PC business growth. During those years the team Intel + Microsoft was the exclusive vendor in the PC 'game'. All others had to compete neck to neck in this fast growing commodity market.  And as we all know, broad competition erodes margins and allows only the lowest cost producer to achieve some profits. In the case of PC this erosion actually pushed out the market creator - IBM - which eventually exited the market and sold its business to Lenovo. The only real winners back then were Microsoft and Intel, who had pivotal differentiating IP. Yes, Intel had a licensor - AMD - but as a licensor, AMD had to pay heavy royalties that impacted its profits, and helped those of Intel.

Both Intel and Microsoft were able to leverage there unique IP into years of growth and became the largest companies in their field.

But being the largest today does not guarantee the tomorrow. Or, as Andy Grove famously said, "only the paranoid survive".

The technology world is about change. While many of the changes are incremental, at times the paradigm changes too. The change that took away Intel’s and Microsoft’s unchallenged market and IP position was the shift to "smart mobile," or mobile internet, as is illustrated in the following chart.

And with these changes new technology leaders have been emerging: companies such as  Apple, Qualcomm, and Google.

To make matters even worse, a small company - ARM - was able to create a disruptive change in the computing engine with its preferred computing architecture, first for 'smart mobile,' then for tablets, and now it seems to penetrate the PC and the server markets.

In my view, as soon as the investment community realized that Intel’s exclusive market and IP position is not relevant to the new market of Mobile Internet, it started to tune down Intel’s P/E. This trend even got stronger as investors became concerned regarding Intel’s position in the PC and server market.

It should be noted that in this context IP is not counted by the number of patents or the amount of trade secrets but rather by the ability to exclude competitors from major markets or extract royalties from those competitors, which may make you a winner even when you loose business. This is a status that Qualcomm and other companies such as SanDisk enjoy.


Economists estimate that two-thirds of the value of large businesses in the U.S. can be traced to intangible assets.[18] "IP-intensive industries" are estimated to generate 72 percent more value added (price minus material cost) per employee than "non-IP-intensive industries".[19][dubious – discuss] , as is illustrated by the following chart

So, is the game over for Intel??? Is the Market irrational, or is the Market perceptive?

Some pundits clearly think so, but given its leadership semiconductor technology, strong leading edge manufacturing infrastructure, and balance sheet, it is way too soon to call game over for Intel. But it would seem that Intel needs to introduce some real change in order to correct its course. Perhaps Intel should look back at what Andy Grove’s said and ask itself: does it really act like a paranoid company, or perhaps it is just the inverse.

We at MonolithIC 3D believe that the whole semiconductor industry is about to go through a major disruptive change. After 50 years of successful growth and progress by dimensional scaling, the time has come for a direction change, and the time is now for starting to embrace scaling-up, going for monolithic 3D. The current leaders in dimensional scaling, the NAND Flash vendors, seem to be leading the way. They are pushing ahead with monolithic 3D-NAND. This disruptive change will bring vast new opportunities, and those who will be early to embrace the change may be able to reap the IP reward.

We have a guest contribution today from Ze'ev Wurman, MonolithIC 3D Inc.'s Chief Software Architect. Ze'ev discusses about where is the semiconductor industry heading to.

The semiconductor industry is in the doldrums. The PC market shrinks, Intel shares sink, Applied Materials cuts staff, and even Apple suddenly experiences its share price drop by $100 in a month. Are things really so bad?

But other news seems different. TSMC shares are close to their historical high; Global Foundries leapfrogs TSMC technology and nips at Intel’s heels with 14nm; Samsung reports record quarterly profit. Things seem to be going swimmingly.

Semiconductor business has had its ups and downs since its inception. As demand followed, more and more capacity was put on line, which caused the next overcapacity and slump, inevitably followed by the next spike in demand as the technology inexorably marched down the scaling curve. So, perhaps, nothing is really new here after all.

Yet, perhaps, we should not be so sanguine anymore. We did cope with 193nm light to define our chips down to 20 nm, but at an ever-increasing cost of expensive phase shift masks, immersion lithography, and double exposure. EUV has been talked about for at least 15 years (following another 15 years of x-ray lithography development fiasco) and has been “late” since at least 2005. Despite the impressive progress shown by ASML, the industry greats – Intel, Samsung, and TSMC --banding around EUV is possibly more a sign of desperation than a strong vote of confidence. The drastic reduction in foundry players – from 20 or so in 90nm to four or less for 14nm has been noticed by many and cannot be good for the long-term health and vitality of the industry. 

ASML is the last remaining game in town and, even if it works, building a foundry at over $10B a pop, and developing a technology node at well north of $1B, does wonders at keeping everyone but the most committed (and with deep pockets) out of the game. And the unanswered question is still in place: at what price point will the industry effectively become the domain of the few mass-produced designs such as Apple’s or Samsung’s phones and nothing else? 

Clearly pressures have been building up and the industry can’t pretend everything is as usual for much longer.  3D devices has been talked about for decades, yet implementing this dream was considered infeasible until recently. 3D designs are, in a sense, the holy grail of the industry:

• They allow for shrinkage of the average source to destination distances, shrinking power dissipation and improving performance;
  

• They can include inexpensive built-in fault detection and repair as described here, allowing for as large as needed yielded dies, which cuts further on power by saving on off-chip I/O power;
• They allow cheap and high performance integration of dies with disparate technologies, so advanced (and expensive)  logic can be stacked with reduced-cost technology for memory dies, or specialized analog and RF functions;
• They allow the reuse of older fab lines as much of density improvement is achieved through stacking dies rather than shrinking features;
  

• They allow efficient heat removal without exotic cooling technologies through use of power delivery networks, to be presented in the upcoming IEDM, paper 14.2 ;
  

In recent years TSVs started to show up. Yet, while TSVs are good for designs that need limited vertical connectivity between disparate sub-systems such as processors with memory, they do not really open the door to a true monolithic 3D design.  What true monolithic devices offer is a much higher vertical connectivity, by a factor of up to 10,000, and enable the stacking of multiple dies.

The impact of the increased monolithic vertical integration at lower cost can be dramatic on every electronic market segment.

For mobile devices, the inexpensive integration of analog, RF, and sensors, can lower their cost and power consumption for an even broader market penetration and longer battery life.

In medicine, the footprint of devices is often critical. The availability of camera-in-a-pill, or of implantable medical devices that control drug release, improve hearing, monitor vital signs, or allow artificial vision, are all strongly dependent on heterogeneous device integration in a small footprint and with reduced power. Monolithic 3D is key to transforming the planar and bulky designs of today’s 2D to grain-of-corn and grain-of-rice shape factors that can be inserted for very long time periods into our bodies.

Fostering innovation and reducing barriers to entry of new products are considered crucial for future economic prosperity. FPGAs have been trying to fill this niche since the demise of ASICs, yet they suffer from many handicaps: they are physically large, they are power hungry, and they are available in a limited number of configurations that are often suboptimal for the application. Monolithic 3D technology allows the inexpensive creation of a nearly infinite number of FPGA configurations that can be tailored to every application, as described here. And it does so while dramatically reducing both the device footprint and power.

Large-scale computing is facing enormous challenges to reduce its power consumption. Server farms of the likes of Google, Amazon, or Facebook consume tens and hundreds of megawatts of energy, while the government struggles mightily to keep its planned Exascale supercomputer under 20MW. Three-dimensional chips can play a large role in reducing power consumption by reducing the interconnect length (and hence, its capacitance), which is responsible for most of the power dissipation in modern chips. Ultra large scale integration with high yields, enabled through 3D repair structures, will further slash the power that today resides in the off-chip drivers.

In memory design, the transition to 3D technology is already taking place as described in our previous blog. Monolithic 3D structures using crystalline silicon may further the penetration and efficacy of this technology in both non-volatile memory as well as in DRAM.

The semiconductor world will inevitably move to monolithic three-dimensional technologies. The change drivers are already here: the skyrocketing cost of scaled-down lithography, the need to reduce power dissipation, and the need for heterogeneous integration. The only question is how quickly it will move there, and who will be the winners.

We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel discusses the opportunities of 3D NAND with Monolithic 3D.

NAND technology, which is a subset of NVM (Non Volatile Memory), was invented by Fujio Masuoka of Toshiba back in 1984. Flash memory was presented at IEDM1984 by Dr. Masuoka and his colleagues [1].  The following is a short quote from the original paper “the cell is programmed by a channel hot carrier injection mechanism similar to EPROM. The contents of all memory cells are simultaneously erased by using field emission of electrons from a floating gate to an erased gate in a FLASH (Hence the name FLASH)”.  

Masuoka came back to the IEDM in 1987 and suggested a Flash NAND structure [2].
Intel created the first commercial NOR type of Flash chips in 1988. For the next few years some major developments occur in the Flash arena:

• In 1989, Samsung and Toshiba created a NAND flash memory.
• In 1994, Compact Flash was invented and introduced by SanDisk.
• In 1999, the SD memory card was released by a combination of SanDisk, Toshiba and Matsushita.
• In 2001, the world’s first 1 Gigabit Compact Flash card was introduced.

From 2006 onwards, NAND became the most scaled of devices beating out the microprocessor devices (see Figure 1). The current state of the art is 20nm (2x) technology, as the world’s appetite for storage is still strong. Flash Cards, SSD, Smartphone and Tablets are the leading growing applications.

NAND memory as a true cross point array with the control gate on top of the floating gate and only one contact for a whole string of cells has the smallest memory cell size as shown in Figure 2 In addition, when one adds with the capability of MLC (Multi Level Cells) to NAND devices, the bit density dramatically increases.

The NAND market has been continuously growing for the last several years. Figure 3 shows the NAND revenue and Gigabytes increase since 2008 and the forward projection for the years 2012-2016.

As the NAND technology has been moving to smaller and smaller process nodes some serious problems, physical and electrical surfaced:
           Physical Limitations:

• Pattern scaling - lack of EUV is a major issue
• Structure formation, Figure 4 depicts a 27nm NAND cell that shows how close the cells are getting to each other, and how much the aspect ratio is getting out of hand. This is a limiter to obtaining high yield.

          Electrical Limitations:

• There is an increase in cell-to-cell interference in the word lines.
• Capacitive coupling ratio has decreased
• Dielectric leakage has increased

The number of electrons on the floating gate has decreased dramatically so much so that a small fluctuation in the number on the floating gate can make a huge effect on the cell function. Figure 5 describes the scaling induced phenomenon.

It is a common understanding among the experts that the current NAND technology will not be able to be scaled down to the 10nm node.

The solution for this dilemma is the 3D NAND, which was initially proposed by Toshiba at the 2007 VLSI Symposium [3]. Toshiba unveiled its Bit Cost Scalable (BiCS) technology. BiCS makes use of a “punch-and plug” structure and charge trap memory films. Toshiba has fabricated a prototype 32-Gbit BiCS flash memory test array with a 16-layer memory cell using 60nm design rules, see Figure 6. Hynix, Samsung and Macronix have also come with their versions of the 3D NAND.

The following are the key advantages of the 3D NAND:

• With 3D NAND, scaling is no longer driven by lithography. The gate length is defined by deposition
  
• The key steps to 3D NAND are
  

                                        - Build a multitude of oxide/nitride or oxide/doped polysilicon stacked layers
                                - Fill the deep memory holes or trench slits. The top foreseeable challenges are ultra-high-aspect ratio (>40:1) conductor etch and dielectric etch with high etch selectivity to the hard mask

• 3D NAND is relatively straightforward for a DRAM maker since it has stacked SiO2 and polysilicon layers like a stacked capacitor DRAM, and trenches like a trench cell DRAM. 
  
• 3D NAND is evolutionary, not revolutionary. 
  
• The good news is continued cost reduction, smaller die sizes and more capacity. 
  
• Installed NAND toolsets in the wafer Fabs can, for the most part, be reused, thereby extending the useful life of Fab equipment. 
  
• 3D NAND technology is still basically NAND with all its inherent limitations of data reliability and performance: hence, generally well understood (evolutionary).
  

At this point all the NAND companies are putting a lot of effort to bring this process to high volume manufacturing; the current expectations are that in 2014-2015 it will be ready for prime time. 3D NAND will be a technology that will take us between the 2D planar NAND and whichever post-NAND technology emerges in the future.

Figure 7 describes the essence of the advantage of moving from 2D to 3D NAND. The adoption of 3D NAND technology will remove the burden from the Litho (and hence EUV) into the much easier process steps (deposition). Of course there are other advantages as described above.

It is not too difficult to see the similarity between the up and coming 3D NAND and the Monolithic 3D approach. As we describe in our web site (www.monolithic3d.com) the advanced technology patented by MonolithIC 3D Inc. enables the fabrication of Monolithic 3D Integrated Circuits with multiple stacked transistor layers and ultra-dense vertical connectivity. Thus, it appears monolithic 3D-ICs with 2 device layers provide benefits similar to a generation of conventional scaling. Furthermore, just as conventional scaling reduces feature sizes every generation, monolithic 3D opens the road for many years of continuous scaling by ‘folding’ once, twice, and so forth without necessarily reducing feature sizes.

1. F. Masuoka et. al IEDM 1984 pp464-467
2. F. Masuoka et. al IEDM 1987 pp552-555
3. H. Tanaka et al., Symp. on VLSI Tech. Dig., pp 14-15, 2007

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about the latest news regarding the reversal of the trend from Foundry model back to the IDM model.

Are we facing a dramatic reversal of the trend from the Foundry model back to the IDM model???

Recently Rick Merritt of EE Times reported on his interview with Mark Bohr, "Mr. Process Technology at Intel," and wrote: "It’s the beginning of the end for the fabless model according to Mark Bohr."

Quite naturally this caused many responses, with the majority of them hinting that Intel is trying to break into the smart mobile space by sowing doubt in the future of the existing ecosystem around TSMC-ARM and multiple fabless vendors.

We recently wrote two very relevant blog entries:

Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies? 04/02/2012
and
Why Samsung will give Morris Chang sleepless nights 02/05/2012


With recent reports about Qualcomm having issues with TSMC, Apple not being able to shift out from Samsung (their competitor) to TSMC, AMD having severe issues and trying to shift some of manufacturing from GlobalFoundries to TSMC, and straight out statements such as:  "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless," one can't avoid the question: Are we facing a dramatic reversal of the trend from the Foundry model back to the IDM model???


It does seem that advanced scaling these days provides a significant advantage to the integrated model, where trade-offs between design, library EDA, and manufacturing, provide a better end product. Such an integration advantage manifests itself with respect to yield, now that the majority of the yield losses are design-related rather than random defects, and to manufacturing cost, as some of the layers needs double or even triple/quad patterning. 


Accordingly, this might explain why both TSMC and GlobalFoundries recently announced investment in 3D IC processing lines (TSMC plans 3-D IC assembly launch early in 2013, GlobalFoundries installs gear for 20-nm TSVs). As the current scaling trend works against them, they both chose to move the game to a court where an ecosystem would be more powerful than corporate vertical integration.


We at MonolithIC 3D Inc. are very pleased to see 3D ICs becoming a key business strategy, and truly believe that adding monolithic 3D manufacturing capabilities will extend foundries’ strategic benefits even further. Monolithic 3D, with its 10,000x better vertical connectivity, provides an exciting alternative to pure dimensional scaling. Moore's law is about doubling the number of transistors, which could be easily achieved using existing process and lithography by simply doubling the number of layers carrying transistors. Scaling through the third dimension provides power, speed, and cost benefits similar – or even better -- than we once used to get from dimensional scaling (see "Why Monolithic 3D" for more information).


In addition, monolithic 3D provides benefits that cannot be achieved with dimensional scaling such as pulling out embedded memory into another layer on top of the logic. In a typical SoC the embedded memory may represent 50% of the die area and include hundreds of memory macros, requiring too many vertical connections for TSV but is a very simple task for monolithic 3D integration. A dedicated memory layer also allows optimizing the first layer for logic and the second layer for memory, which could be even a DRAM rather than SRAM, and would need fewer costly metal layers. Another advantage is the realization of logic-cone-level logic redundancy, as described in Monolithic 3D IC Could Increase Circuit Integration by 1,000x and in Redundancy & Repair with Monolithic 3D.


In summary, the current trend in the semiconductor industry indicates that IDMs have a significant advantage in the leading edge dimensional scaling race. Foundries recognize it and are responding by adding 3D capabilities. They could do even better by also adding monolithic 3D. 

We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel discusses about TSVs. 

Have you read some of the recent TSV headlines?

1. January 31, 2012 - CEA-Leti launched a major new platform, Open 3D, that provides industrial and academic partners with a global offer of mature 3D packaging technologies for their advanced semiconductor products and research projects.

2. March 7, 2012 - Semiconductor fab equipment supplier Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore's Science Park II with its partner in the endeavor, the Institute of Microelectronics (IME)

3. March 26, 2012 - PRNewswire - Semiconductor design/manufacturing software supplier Synopsys Inc. (Nasdaq: SNPS) is combining several products into a 3D-IC initiative for semiconductor designers moving to stacked-die silicon systems in 3D packaging.

It is amazing that after so many years of development and efforts and great presentations we are still not in a full production and still basic R&D as well as EDA still in infancy.

Most people in the Industry consider Merlin Smith and Emanuel Stern of IBM the inventors of TSV based on their patent “Methods of Making Thru-Connections in Semiconductor Wafers” filed on December 28, 1964 and granted on September 26, 1967, as shown below patent  number 3,343,256

In April 12, 2007 IBM announced a breakthrough new 3D technology:
Armonk, NY - 12 Apr, 2007: IBM (NYSE: IBM) today announced a breakthrough chip-stacking technology in a manufacturing environment that paves the way for three-dimensional chips that will extend Moore’s Law beyond its expected limits. The technology – called “through-silicon vias” - allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems… IBM is already running chips using the through-silicon via technology in its manufacturing line and will begin making sample chips using this method available to customers in the second half of 2007, with production in 2008.

Figure 2 is taken from Ignatowski’s presentation made shortly after IBM’s TSV announcement. This type of argument where chip stacking is compared to 2 chips side by side has become the corner stone of the TSV story (http://www.sematech.org/meetings/archives/3d/8334/pres/Ignatowski.pdf).

Already at that point (2007) it was clear to IBM that there were many issues with the technology that needed to be resolved.  Figure 3 shows the IBM slide discussing some of the problems for implementing TSV for mass production.

During the years following and through to today there have been many attempts to bring the technology to the mass production. All have been without real success. 
The professional literature is full of beautiful road maps showing how TSV is going to change the industry with “more than Moore” as the next scaling methodology. 
Figure 4 is the Advanced Packaging road map for Texas Instruments which is typical of most companies Packaging/TSV road maps.

There are several issues that are facing the industry when trying to implement TSV technology: (not in any specific order)
Process issues:

• Via etching and filling are extremely slow since the dimensions are very different from the “normal” dimensions the industry uses (single/multiple digit microns for depth and diameter vs. nanometers, plus aspect ratios>5)
• Via, first, middle or last which way to go? Each affects the whole process logistics in differing ways
  
• How to integrate wafers from different sources Logic from IDM and/or foundry and memory from a memory Fab
  
• Wafer thinning, how to handle fully processed wafer 20-80 micron thick including bonding and de-bonding. Rumors are that both Applied Materials and TEL are developing this kind of a tool
  
• Wafer-to-wafer (W2W) or die-to-wafer (D2W) bonding: each  have processing challenges
  
• Singulation of the final product
• Substrate (carrier)for TSV

Design and EDA:

•  Design rules are currently not compatible with TSV
  
•  Who is responsible for the “system” design if there are several sources for product to be integrated?
  
• EDA is way, way behind
  
• Thermal simulation and heat removal issues

Back end issues:

• Foundries/IDM vs. OSAT, who is doing what and who picks up yield loss
  
• Final test
• Reliability
• The major foundries have no memory knowledge or how to integrate the memory on top of logic

Cost:

            - Currently the cost associated with implementing TSV is at least for now higher than other solutions. This is hampering the motivation to develop and implement the TSV technology.

Also the CapEx to implement TSV needs to be addressed, Figure 5 is a table put together by ASE that shows the readiness of the various equipment needed to run a typical TSV process.

One of the key issues that some people are neglecting right now is the fact that we do have an interim solution to the problem. It may- probably not be the best solution and perhaps not the most elegant one but it does work. These are the variety of packaging techniques using chip on chip with wire bonding, and assortment solutions (PoP etc).

The following are some of the comments made by industry experts over the last few months.

TSMC
Doug Yu’s keynote address at the 3D Architectures for Semiconductor Integration and Packaging Conference in December, he noted that TSMC intends to provide full 2.5F and 3D service including chip design and fabrication, stacking and packaging. Yu, who is senior director of integrated interconnect and packaging, R&D at TSMC, outlined the key technologies that offer the best path to commercializing 3D integration technologies, with the implication that TSMC is well positioned to provide them all.

(http://www.infoneedle.com/posting/100745?snc=20641)

“TSV is much more complex and challenging than ever before,” noted Yu. “There’s a new ballgame and a small window.” He said a conventional collaboration infrastructure is becoming harder. Integration must be simplified to reduce handling and an investment beyond conventional back-end (in other words, middle-end-of-line tools and processes) is required. In short, Yu said a full spectrum of expertise is needed that includes manufacturing excellence, capacity and customer relationships where there is no competition with the customer 


Hynix
Nick Kim VP of Packaging  announced that for Hynix, production of 3D devices is no longer a matter of if but when and how (http://www.infoneedle.com/posting/100669?snc=20641)

Kim provided a detailed cost breakdown illustrating why 3D TSV stacks are more expensive (1.3x more) than wire bond stacks to manufacture. Overall, TSVs alone add 25% to the manufacturing cost because there is additional cost at each step:  

•  Design: net die area decreases due to TSV array. 
•  Fab: increased process steps due to TSVG formation, and capex for TSV equipment. 
•  Packaging: Bumping, stacking, low yield and CapEx for backside processing equipment such as temporary bond and de-bond. 
  
• Test: Probe and final package test time is increased because of the need to test at each layer as well as final. 
  
• Hynix 3D roadmap: volume TSV production will officially start after 2013:
  
• DRAM on Logic for mobile applications in a known good stacked die (KGSD) driven by form factor and power, are in development in 2012 with low production expected early 2013 ramping to volume late 2014. 
  
• DRAM on interposer in a 2.5D configuration for graphics applications, driven by bandwidth and capacity is in development in 2012 with low production expected by the end of the year and ramping to HVM early in 2014. 
  
• 3D DRAM on substrate for high performance computing (HPC) driven by bandwidth and capacity is in development in 2012, with low production expected early 2013, ramping to volume late 2014. 
  

In terms of supply chain management, Kim sees Hynix favoring the open ecosystem where logic and memory prepared with/for TSV from foundries and IDMs going to OSATs for assembly.

Overall it looks almost like a nightmare to implement TSV in a manufacturing facility. Even if all the processes steps will be taken care of, the logistics and co-ordination with different Fabs and OSAT are definitely no fun!!!

It looks like when we sum all the issues regarding the TSV methodology for achieving 3D, the approach of monolithic 3D suggested by MonolithIC 3D could resolve many of these issues and offer a far greater cost/performance gain from going 3D. Most of these advantages were already discussed in previous blogs and are part of the company web site,

Just few items that I would like to highlight:

•  Practically no limit on the amount of vias between the different chips in the stack.
  
• No deep TSV – nanometers, not microns!
  
•  All done within the IDM or the foundry – better yield control & ramp, and no pointing fingers.

Please comment and let’s get a discussion going.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses NVIDIA's presentation at the International Trade Partner Conference (ITPC) forum last November.

Recently I read a very uncommon report title: "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless". Quoting directly: “One of the unspoken rules of customer-foundry relations is that you virtually never see the former speak poorly of the latter. Only when things have seriously hit the fan do partners like AMD or NVIDIA admit to manufacturing problems... That’s why we were surprised - and our source testified to being stunned - that Nvidia gave the following presentation at the International Trade Partner Conference (ITPC) forum last November”

The only explanation I can come up with is that NVIDIA is in a panic. And according to Andy Grove’s “Only the Paranoid Survive” I believe NVIDIA will overcome the challenge, and at the later part of this blog we will present our view for an action plan. But first let’s try to understand what the issue is about.

It all starts with the diminishing return of dimensional scaling. This time it is about costs. Dimensional scaling requires continual improvements in lithography capability, and is primarily driven by the rapidly escalating cost of lithography, as illustrated by the following chart:

Now that the cost of lithography dominates the cost of Fabs and accordingly the cost of a finished wafer, the cost reduction associated with getting more dies per wafer (scaling) becomes neutralized by the higher cost of wafers. This was recently articulated in View Point in EE Times by Dr. Handel Jones and illustrated by the following chart.

Furthermore, pure foundry leader TSMC publicly showed the issue as seen in the following chart

And accordingly the following charts from NVIDIA present the same trend in a very clear way:

Moreover, another chart by NVIDIA shows the higher cost of wafers eating away at the benefits of dimensional scaling:

But this is clearly not TSMC’s fault. So why: "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless"? And why would NVIDIA care? If the price will stop going down they should be happy to be able to charge more as long as their competitors need to do the same. And it is hard to believe AMD would see different curves from TSMC??

But careful review of the bullet slide above and the bullet slide below might reveal NVIDIA’s underlying  concerns.

Both slides indicate real concerns and reflect some form of panic.

It seems to me that the key words are “Virtual IDM”, which are the only highlighted words of the second bullet slide but do appear also in the first one.
“When business ($) gets in the way, apply “First principle”, the principle of one company, one virtual IDM company”. I was not aware of this “First principle”. I thought our first principle is open competition, and individual companies are supposed to work as such and not as one company I believe we have some laws - Antitrust - against acting as one company instead of individual company.
Yet, NVIDIA does have one strong IDM competitor - Intel. Could it be that Intel’s costs are different??

I don't know but it does remind me of a previous blog I wrote: Required Change in EDA Vendors’ Role and Reward vs. Scaling Yield. In that blog we tried to understand the implication of dimensional scaling on yield, and more specifically on the systematic yield losses which are design related. The following chart was presented then

In that blog we suggested that an IDM would have a significant advantage over the “partnership” of Fabless-Fab-EDA.

Looking again on the cost related chart one can clearly see NVIDIA pointing to the importance of yield. But I believe they should not blame just TSMC as it would seem to me that the EDA part is just as important.
NVIDIA, TSMC and the other fabless companies and partners (EDA, etc.) should strategically consider the issues associated with dimension scaling, which seem to strongly benefit the IDMs. Such strategic evaluation should include a serious look into the better alternative to dimensional scaling - the monolithic 3D, or as we call it, scaling Up!!!

A recent book review by Peter Clarke on this wonderful new book by Bernd Hoefflinger caught my eye, and also reminded me of an old connection I have with Hoefflinger.

Early in the 90's I had the pleasure to collaborate with Hoefflinger, who at that time was the director of the Institute for Microelectronics Stuttgart (IMS CHIPS). I was the CEO of Chip Express then and we worked together to demonstrate that applying Direct-Write-eBeam to a Chip Express wafer could lead to a very effective Gate-Array prototyping scheme and to low volume production of those Gate-Arrays.

It was great pleasure to reconnect and to read "Chip 2020"
I highly recommend this book as it provides an update view of the Semiconductor Industry by a group of known experts in our field.
The book provides a concise review how we got here and what is ahead for us up to the year 2020.

The book presents a now more common view that the scaling that got us here is gone, and that there are concrete red-bricks for dimensional scaling beyond 2020. Primarily:

1. As gate sizes reach ~10nm we would have nominally 6 atoms of impurity in the channel with a commensurate variation that would constrain effective use of the transistor -see Fig. 1.1

2. As lithography tools are already forced to use double exposure/processing it has became unclear if an effective lithography is going to be available to move forward. See the Table 8.3 below, provided by Burn J. Lin of TSMC

Clearly the future cost of lithography eats away at the cost advantage of dimensional scaling.

Hoefflinger presents some options to tackle these challenges as detailed through the book and with respect to specific segments of the industry. The following Fig. 3.1 presents these future technologies:

At MonolithIC 3D we were pleased to see the important role given to 3D IC in the book as shown in the Fig. 3.1 above.

In short I fully agree with Peter Clarke’s statement: "The book offers some far-reaching and fundamental insights" and I highly recommend the book to semiconductor technologists who are looking forward toward the next decade of progress in the field.

2011 was a big year for consolidation in the semiconductor equipment manufacturing industry. The year started with the Varian acquisition by Applied Materials and was ended with the merger announcement of Novellus and Lam Research (not concluded when this blog is written).

The equipment business is relatively conservative and for many years only few noticeable successful M&A were done. Few past M&A were of a strategic nature. In these cases a large corporation buys a smaller one to either develop a product line or to buy into a growing product line. Table 1 is a snapshot of some past M&A activities in the short history of the semiconductor equipment industry-by far not a complete list.

As one can see many of the M&A turned to be a failure and became a big drain on the acquirer balance sheet. In several cases the company seized operation of the acquired company after several years, in other cases it is still going on with a moderate or very limited success. To mention two cases of a real success I can point to the Veeco acquisition of the MOCVD from Emcore and the merger of KLA with Tencor. In both cases the M&A dramatically boosted the company’s position, market cap and market share.

Going back to the two recent M&A namely Applied Materials Varian and Lam Novellus the question is how this will affect the semiconductor industry and who is going to benefit from it.

I definitely view these two activities in a positive way.

1.   Applied Materials and Varian: Looks like Varian had practically all the implant market and really didn’t have any room to grow (beside the new solar implant business-highly speculative). So selling the company to Applied Materials helped a lot… the employees and the top executives that suddenly got their stock price almost double…From Applied Materials point of view they now controlling most of the front end equipment and can influence the transistor technology more than before. Though I might emphasize as I mentioned in a previous Blog that the percentage of the implant business in the whole semi CapEx pie is shrinking in the last few years and probably with the introduction of the FINFET-Tri gate it will shrink even more. Still for Applied strong position in the Epi, RTP and Implant market they do have good position in the front end. The missing link of course is a good position in the ALD technology (controlled by ASMI).

In other hand customers don’t like to see too much power at the hand of one equipment vendor; they do like to see competition. Not clear how it will be played in the implant arena since no other real competitor in the horizon.

2.   LAM Novellus: This merger was proposed many years ago and almost every year was rumored to go through without actually happening to the dismay of analysts and others. However eventually it did happen! By combining the winning position of Lam in the etch and Novellus in the CVD the new combined company could expand and offers new modules and combinations of products especially in the back end and in the emerging double (quadruple) patterning that becomes a very important module in the advanced lithography.

In order to complete this discussion we need to look at the future, and in the future new technology of 3D devices will become a reality. Let’s discuss now how these M&A will affect the new world of 3D devices.

1. TSV
1. No real effect from the Applied Materials Varian deal since the implant is only a front end technology. Not clear if the Plasma Doping (PLAD) that supposes to do material modifications has any impact in the back end.
2. For the Lam Novellus deal it could enhance the TSV technology since they could bring a more comprehensive solution to the TSV module that will include the etching, deposition and Cu plating. Of course they are missing the market leading position that Applied Materials has in the Cu barrier seed PVD equipment.
2. Monolithic 3D
1. Since Applied Materials own now the implant business they could easily get involved in the smart cut technology from point of view of proliferate it to the rest of the world, as it is currently dominate only by the SOI wafers manufacturing. Owning the RTP and Epi helps well in the Monolithic 3D module.
2. No real effect from the Lam Novellus deal.
3. The future introduction of Monolithic 3D technology into the Fab present an opportunity to all the equipment manufacturing companies from several new tools that need to be proliferate into the process flow.