 We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about the latest news regarding the reversal of the trend from Foundry model back to the IDM model.
Are we facing a dramatic reversal of the trend from the Foundry model back to the IDM model???Recently Rick Merritt of EE Times reported on his interview with Mark Bohr, "Mr. Process Technology at Intel," and wrote: "It’s the beginning of the end for the fabless model according to Mark Bohr."
Quite naturally this caused many responses, with the majority of them hinting that Intel is trying to break into the smart mobile space by sowing doubt in the future of the existing ecosystem around TSMC-ARM and multiple fabless vendors.
We recently wrote two very relevant blog entries:
Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies? 04/02/2012
and
Why Samsung will give Morris Chang sleepless nights 02/05/2012
With recent reports about Qualcomm having issues with TSMC, Apple not being able to shift out from Samsung (their competitor) to TSMC, AMD having severe issues and trying to shift some of manufacturing from GlobalFoundries to TSMC, and straight out statements such as: "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless," one can't avoid the question: Are we facing a dramatic reversal of the trend from the Foundry model back to the IDM model???
It does seem that advanced scaling these days provides a significant advantage to the integrated model, where trade-offs between design, library EDA, and manufacturing, provide a better end product. Such an integration advantage manifests itself with respect to yield, now that the majority of the yield losses are design-related rather than random defects, and to manufacturing cost, as some of the layers needs double or even triple/quad patterning.
Accordingly, this might explain why both TSMC and GlobalFoundries recently announced investment in 3D IC processing lines (TSMC plans 3-D IC assembly launch early in 2013, GlobalFoundries installs gear for 20-nm TSVs). As the current scaling trend works against them, they both chose to move the game to a court where an ecosystem would be more powerful than corporate vertical integration.
We at MonolithIC 3D Inc. are very pleased to see 3D ICs becoming a key business strategy, and truly believe that adding monolithic 3D manufacturing capabilities will extend foundries’ strategic benefits even further. Monolithic 3D, with its 10,000x better vertical connectivity, provides an exciting alternative to pure dimensional scaling. Moore's law is about doubling the number of transistors, which could be easily achieved using existing process and lithography by simply doubling the number of layers carrying transistors. Scaling through the third dimension provides power, speed, and cost benefits similar – or even better -- than we once used to get from dimensional scaling (see "Why Monolithic 3D" for more information).
In addition, monolithic 3D provides benefits that cannot be achieved with dimensional scaling such as pulling out embedded memory into another layer on top of the logic. In a typical SoC the embedded memory may represent 50% of the die area and include hundreds of memory macros, requiring too many vertical connections for TSV but is a very simple task for monolithic 3D integration. A dedicated memory layer also allows optimizing the first layer for logic and the second layer for memory, which could be even a DRAM rather than SRAM, and would need fewer costly metal layers. Another advantage is the realization of logic-cone-level logic redundancy, as described in Monolithic 3D IC Could Increase Circuit Integration by 1,000x and in Redundancy & Repair with Monolithic 3D.
In summary, the current trend in the semiconductor industry indicates that IDMs have a significant advantage in the leading edge dimensional scaling race. Foundries recognize it and are responding by adding 3D capabilities. They could do even better by also adding monolithic 3D.
 We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel discusses about TSVs.
Have you read some of the recent TSV headlines? 1. January 31, 2012 - CEA-Leti launched a major new platform, Open 3D, that provides industrial and academic partners with a global offer of mature 3D packaging technologies for their advanced semiconductor products and research projects. 2. March 7, 2012 - Semiconductor fab equipment supplier Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore's Science Park II with its partner in the endeavor, the Institute of Microelectronics (IME) 3. March 26, 2012 - PRNewswire - Semiconductor design/manufacturing software supplier Synopsys Inc. ( Nasdaq: SNPS) is combining several products into a 3D-IC initiative for semiconductor designers moving to stacked-die silicon systems in 3D packaging. It is amazing that after so many years of development and efforts and great presentations we are still not in a full production and still basic R&D as well as EDA still in infancy. Most people in the Industry consider Merlin Smith and Emanuel Stern of IBM the inventors of TSV based on their patent “Methods of Making Thru-Connections in Semiconductor Wafers” filed on December 28, 1964 and granted on September 26, 1967, as shown below patent number 3,343,256  Figure 1: IBM TSV patent In April 12, 2007 IBM announced a breakthrough new 3D technology:
Armonk, NY - 12 Apr, 2007: IBM (NYSE: IBM) today announced a breakthrough chip-stacking technology in a manufacturing environment that paves the way for three-dimensional chips that will extend Moore’s Law beyond its expected limits. The technology – called “through-silicon vias” - allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems… IBM is already running chips using the through-silicon via technology in its manufacturing line and will begin making sample chips using this method available to customers in the second half of 2007, with production in 2008.
 Figure 2: Original story on TSV advantages followed IBM announcement Figure 2 is taken from Ignatowski’s presentation made shortly after IBM’s TSV announcement. This type of argument where chip stacking is compared to 2 chips side by side has become the corner stone of the TSV story (http://www.sematech.org/meetings/archives/3d/8334/pres/Ignatowski.pdf).
Already at that point (2007) it was clear to IBM that there were many issues with the technology that needed to be resolved. Figure 3 shows the IBM slide discussing some of the problems for implementing TSV for mass production.
 Figure 3: Issues per IBM with the TSV technology During the years following and through to today there have been many attempts to bring the technology to the mass production. All have been without real success.
The professional literature is full of beautiful road maps showing how TSV is going to change the industry with “more than Moore” as the next scaling methodology.
Figure 4 is the Advanced Packaging road map for Texas Instruments which is typical of most companies Packaging/TSV road maps.
 Figure 4: TI Packaging Technology Trends Dec 2011 There are several issues that are facing the industry when trying to implement TSV technology: (not in any specific order) Process issues: - Via etching and filling are extremely slow since the dimensions are very different from the “normal” dimensions the industry uses (single/multiple digit microns for depth and diameter vs. nanometers, plus aspect ratios>5)
- Via, first, middle or last which way to go? Each affects the whole process logistics in differing ways
- How to integrate wafers from different sources Logic from IDM and/or foundry and memory from a memory Fab
- Wafer thinning, how to handle fully processed wafer 20-80 micron thick including bonding and de-bonding. Rumors are that both Applied Materials and TEL are developing this kind of a tool
- Wafer-to-wafer (W2W) or die-to-wafer (D2W) bonding: each have processing challenges
- Singulation of the final product
- Substrate (carrier)for TSV
Design and EDA: - Design rules are currently not compatible with TSV
- Who is responsible for the “system” design if there are several sources for product to be integrated?
- EDA is way, way behind
- Thermal simulation and heat removal issues
Back end issues: - Foundries/IDM vs. OSAT, who is doing what and who picks up yield loss
- Final test
- Reliability
- The major foundries have no memory knowledge or how to integrate the memory on top of logic
Cost: - Currently the cost associated with implementing TSV is at least for now higher than other solutions. This is hampering the motivation to develop and implement the TSV technology. Also the CapEx to implement TSV needs to be addressed, Figure 5 is a table put together by ASE that shows the readiness of the various equipment needed to run a typical TSV process.  Figure 5: TSV equipment readiness per ASE One of the key issues that some people are neglecting right now is the fact that we do have an interim solution to the problem. It may- probably not be the best solution and perhaps not the most elegant one but it does work. These are the variety of packaging techniques using chip on chip with wire bonding, and assortment solutions (PoP etc).
 Figure 6: Alternative methods for 3D chip connectivity The following are some of the comments made by industry experts over the last few months. TSMCDoug Yu’s keynote address at the 3D Architectures for Semiconductor Integration and Packaging Conference in December, he noted that TSMC intends to provide full 2.5F and 3D service including chip design and fabrication, stacking and packaging. Yu, who is senior director of integrated interconnect and packaging, R&D at TSMC, outlined the key technologies that offer the best path to commercializing 3D integration technologies, with the implication that TSMC is well positioned to provide them all.
(http://www.infoneedle.com/posting/100745?snc=20641)
“TSV is much more complex and challenging than ever before,” noted Yu. “There’s a new ballgame and a small window.” He said a conventional collaboration infrastructure is becoming harder. Integration must be simplified to reduce handling and an investment beyond conventional back-end (in other words, middle-end-of-line tools and processes) is required. In short, Yu said a full spectrum of expertise is needed that includes manufacturing excellence, capacity and customer relationships where there is no competition with the customer
HynixNick Kim VP of Packaging announced that for Hynix, production of 3D devices is no longer a matter of if but when and how (http://www.infoneedle.com/posting/100669?snc=20641)
Kim provided a detailed cost breakdown illustrating why 3D TSV stacks are more expensive (1.3x more) than wire bond stacks to manufacture. Overall, TSVs alone add 25% to the manufacturing cost because there is additional cost at each step:
- Design: net die area decreases due to TSV array.
- Fab: increased process steps due to TSVG formation, and capex for TSV equipment.
- Packaging: Bumping, stacking, low yield and CapEx for backside processing equipment such as temporary bond and de-bond.
- Test: Probe and final package test time is increased because of the need to test at each layer as well as final.
- Hynix 3D roadmap: volume TSV production will officially start after 2013:
- DRAM on Logic for mobile applications in a known good stacked die (KGSD) driven by form factor and power, are in development in 2012 with low production expected early 2013 ramping to volume late 2014.
- DRAM on interposer in a 2.5D configuration for graphics applications, driven by bandwidth and capacity is in development in 2012 with low production expected by the end of the year and ramping to HVM early in 2014.
- 3D DRAM on substrate for high performance computing (HPC) driven by bandwidth and capacity is in development in 2012, with low production expected early 2013, ramping to volume late 2014.
In terms of supply chain management, Kim sees Hynix favoring the open ecosystem where logic and memory prepared with/for TSV from foundries and IDMs going to OSATs for assembly.
Overall it looks almost like a nightmare to implement TSV in a manufacturing facility. Even if all the processes steps will be taken care of, the logistics and co-ordination with different Fabs and OSAT are definitely no fun!!!
It looks like when we sum all the issues regarding the TSV methodology for achieving 3D, the approach of monolithic 3D suggested by MonolithIC 3D could resolve many of these issues and offer a far greater cost/performance gain from going 3D. Most of these advantages were already discussed in previous blogs and are part of the company web site,
Just few items that I would like to highlight:
- Practically no limit on the amount of vias between the different chips in the stack.
- No deep TSV – nanometers, not microns!
- All done within the IDM or the foundry – better yield control & ramp, and no pointing fingers.
Please comment and let’s get a discussion going.
 We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses NVIDIA's presentation at the International Trade Partner Conference (ITPC) forum last November.
Recently I read a very uncommon report title: "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless". Quoting directly : “One of the unspoken rules of customer-foundry relations is that you virtually never see the former speak poorly of the latter. Only when things have seriously hit the fan do partners like AMD or NVIDIA admit to manufacturing problems... That’s why we were surprised - and our source testified to being stunned - that Nvidia gave the following presentation at the International Trade Partner Conference (ITPC) forum last November”  Figure 1 The only explanation I can come up with is that NVIDIA is in a panic. And according to Andy Grove’s “Only the Paranoid Survive” I believe NVIDIA will overcome the challenge, and at the later part of this blog we will present our view for an action plan. But first let’s try to understand what the issue is about.
It all starts with the diminishing return of dimensional scaling. This time it is about costs. Dimensional scaling requires continual improvements in lithography capability, and is primarily driven by the rapidly escalating cost of lithography, as illustrated by the following chart:
 Figure 2 Now that the cost of lithography dominates the cost of Fabs and accordingly the cost of a finished wafer, the cost reduction associated with getting more dies per wafer (scaling) becomes neutralized by the higher cost of wafers. This was recently articulated in View Point in EE Times by Dr. Handel Jones and illustrated by the following chart.  Figure 3 Furthermore, pure foundry leader TSMC publicly showed the issue as seen in the following chart
 Figure 4 And accordingly the following charts from NVIDIA present the same trend in a very clear way:
 Figure 5 Moreover, another chart by NVIDIA shows the higher cost of wafers eating away at the benefits of dimensional scaling:
 Figure 6 But this is clearly not TSMC’s fault. So why: "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless"? And why would NVIDIA care? If the price will stop going down they should be happy to be able to charge more as long as their competitors need to do the same. And it is hard to believe AMD would see different curves from TSMC?? But careful review of the bullet slide above and the bullet slide below might reveal NVIDIA’s underlying concerns.  Figure 7 Both slides indicate real concerns and reflect some form of panic. It seems to me that the key words are “Virtual IDM”, which are the only highlighted words of the second bullet slide but do appear also in the first one. “When business ($) gets in the way, apply “First principle”, the principle of one company, one virtual IDM company”. I was not aware of this “First principle”. I thought our first principle is open competition, and individual companies are supposed to work as such and not as one company I believe we have some laws - Antitrust - against acting as one company instead of individual company. Yet, NVIDIA does have one strong IDM competitor - Intel. Could it be that Intel’s costs are different?? I don't know but it does remind me of a previous blog I wrote: Required Change in EDA Vendors’ Role and Reward vs. Scaling Yield. In that blog we tried to understand the implication of dimensional scaling on yield, and more specifically on the systematic yield losses which are design related. The following chart was presented then  Figure 8 In that blog we suggested that an IDM would have a significant advantage over the “partnership” of Fabless-Fab-EDA.
Looking again on the cost related chart one can clearly see NVIDIA pointing to the importance of yield. But I believe they should not blame just TSMC as it would seem to me that the EDA part is just as important.
NVIDIA, TSMC and the other fabless companies and partners (EDA, etc.) should strategically consider the issues associated with dimension scaling, which seem to strongly benefit the IDMs. Such strategic evaluation should include a serious look into the better alternative to dimensional scaling - the monolithic 3D, or as we call it, scaling Up!!!
 We have a guest contribution from Iulia Morariu, who does marketing for us. Iulia has a bachelor's degree in computer science and a master’s degree in computer networking. She shares her point of view about her experience as an outsourcing engineer for the company.
Outsourcing is the main focus of this post. Since early 1990s outsourcing captured the attention of some of the biggest companies in the world. Growing along with the Internet, outsourcing came as a natural thing for those who seek cheap work force and skilled engineers. According to The International Center for Peace and Development “It began on a large scale with the migration of manufacturing jobs to lower wage developing countries in the 1960s and 70s, when countries such as Singapore, Taiwan, South Korea became major manufacturing hubs for global corporations.” It accelerated in the 1990s when other countries became major destinations for foreign investment in manufacturing for export. XMG Global, an ITC Research and Advisory Company noted that the global outsourcing industry was estimated in 2010 to $425 billion having a growth of 13.9% from 2009’s $374 billion.  Figure 1: Global Outsourcing Industry. Source: XMG Global Among the first industries that saw the advantages for this was the IT sector. This is now reflected into global IT services spending in excess of $3.5B last year (table 1), much of it outsourced:
 Table 1. IT Spending by Sector, Worldwide, 2008-2015 According to Gartner's U.S. dollar growth forecast for global IT spending in 2012 has been revised downward from 4.6% in the previous quarter to 3.7%. “Faltering global economic growth, the Eurozone crisis and the impact of Thailand's floods on hard-disc drive production have taken their toll on IT spending”, remarked Richard Gordon, VP of Research for Gartner Inc.
European engineers are spread all over the world, mostly the ones that continued their studies in a foreign country and then managed to obtain positions in international corporations. “While reliable projections are difficult in a field that is evolving so rapidly, it has been estimated that by 2015, US companies will offshore 3.3 million jobs valued at $135 billion a year”, The International Center for Peace and Development states in its “Employment Trends in the 21st Century” research.
“European firms prefer nearshoring to countries in Eastern Europe such as Romania where wages are only 10% of the level in the West. More than 80% of world's top 2000 companies operate significant outsourcing operations overseas”, says the research report. So why shouldn’t US companies take on the trend to a next level? I am sure they will continue to outsource their business throughout European countries. Gaining not only cheap labor but also an inside view of how the European market evolves. Evolving technology and the hunger for money will spread knowledge in the most remote places on Earth.
Projections from The International Labour Office in Geneva for unemployment from 2011-2016 indicate that there will be a large untapped pool of skilled talent in Europe for the foreseeable future:
 Table 2. Unemployment projection from The International Labour Office in Geneva I believe that international companies should invest more in foreign countries, keeping the “wheels spinning” and the money coming. Speaking from my experience as one such engineer – I myself live in Romania -- I can say that it is a life changing opportunity and that there is much more we can learn from each other. When working in an international company you don’t just have the world at your feet (by reducing the distance from 3,000 kilometers to a click away) but also have the chance to interact in a multicultural environment.
References:
1 – “Employment Trends in the 21st Century”, The International Center for Peace and Development, www.icpd.org
2. – “Global Employment Trends 2012”, The International Labour Office in Geneva, http://www.ilo.org
3. – Gartner Worldwide IT Spending Forecast, http://www.gartner.com/technology/research/it-spending-forecast/
 We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about "Chip 2020" book review.
A recent book review by Peter Clarke on this wonderful new book by Bernd Hoefflinger caught my eye, and also reminded me of an old connection I have with Hoefflinger. Early in the 90's I had the pleasure to collaborate with Hoefflinger, who at that time was the director of the Institute for Microelectronics Stuttgart (IMS CHIPS). I was the CEO of Chip Express then and we worked together to demonstrate that applying Direct-Write-eBeam to a Chip Express wafer could lead to a very effective Gate-Array prototyping scheme and to low volume production of those Gate-Arrays. It was great pleasure to reconnect and to read "Chip 2020" I highly recommend this book as it provides an update view of the Semiconductor Industry by a group of known experts in our field. The book provides a concise review how we got here and what is ahead for us up to the year 2020. The book presents a now more common view that the scaling that got us here is gone, and that there are concrete red-bricks for dimensional scaling beyond 2020. Primarily: 1. As gate sizes reach ~10nm we would have nominally 6 atoms of impurity in the channel with a commensurate variation that would constrain effective use of the transistor -see Fig. 1.1 2. As lithography tools are already forced to use double exposure/processing it has became unclear if an effective lithography is going to be available to move forward. See the Table 8.3 below, provided by Burn J. Lin of TSMC
Clearly the future cost of lithography eats away at the cost advantage of dimensional scaling.
Hoefflinger presents some options to tackle these challenges as detailed through the book and with respect to specific segments of the industry. The following Fig. 3.1 presents these future technologies:
At MonolithIC 3D we were pleased to see the important role given to 3D IC in the book as shown in the Fig. 3.1 above.
In short I fully agree with Peter Clarke’s statement: "The book offers some far-reaching and fundamental insights" and I highly recommend the book to semiconductor technologists who are looking forward toward the next decade of progress in the field.
 We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel discusses about the semiconductor equipment manufacturing: "Who wins from the recent consolidation?"
2011 was a big year for consolidation in the semiconductor equipment manufacturing industry. The year started with the Varian acquisition by Applied Materials and was ended with the merger announcement of Novellus and Lam Research (not concluded when this blog is written).
The equipment business is relatively conservative and for many years only few noticeable successful M&A were done. Few past M&A were of a strategic nature. In these cases a large corporation buys a smaller one to either develop a product line or to buy into a growing product line. Table 1 is a snapshot of some past M&A activities in the short history of the semiconductor equipment industry-by far not a complete list.  Table 1 - Past M&A activities As one can see many of the M&A turned to be a failure and became a big drain on the acquirer balance sheet. In several cases the company seized operation of the acquired company after several years, in other cases it is still going on with a moderate or very limited success. To mention two cases of a real success I can point to the Veeco acquisition of the MOCVD from Emcore and the merger of KLA with Tencor. In both cases the M&A dramatically boosted the company’s position, market cap and market share. Going back to the two recent M&A namely Applied Materials Varian and Lam Novellus the question is how this will affect the semiconductor industry and who is going to benefit from it. I definitely view these two activities in a positive way. 1. Applied Materials and Varian: Looks like Varian had practically all the implant market and really didn’t have any room to grow (beside the new solar implant business-highly speculative). So selling the company to Applied Materials helped a lot… the employees and the top executives that suddenly got their stock price almost double…From Applied Materials point of view they now controlling most of the front end equipment and can influence the transistor technology more than before. Though I might emphasize as I mentioned in a previous Blog that the percentage of the implant business in the whole semi CapEx pie is shrinking in the last few years and probably with the introduction of the FINFET-Tri gate it will shrink even more. Still for Applied strong position in the Epi, RTP and Implant market they do have good position in the front end. The missing link of course is a good position in the ALD technology (controlled by ASMI). In other hand customers don’t like to see too much power at the hand of one equipment vendor; they do like to see competition. Not clear how it will be played in the implant arena since no other real competitor in the horizon. 2. LAM Novellus: This merger was proposed many years ago and almost every year was rumored to go through without actually happening to the dismay of analysts and others. However eventually it did happen! By combining the winning position of Lam in the etch and Novellus in the CVD the new combined company could expand and offers new modules and combinations of products especially in the back end and in the emerging double (quadruple) patterning that becomes a very important module in the advanced lithography. In order to complete this discussion we need to look at the future, and in the future new technology of 3D devices will become a reality. Let’s discuss now how these M&A will affect the new world of 3D devices. - TSV
- No real effect from the Applied Materials Varian deal since the implant is only a front end technology. Not clear if the Plasma Doping (PLAD) that supposes to do material modifications has any impact in the back end.
- For the Lam Novellus deal it could enhance the TSV technology since they could bring a more comprehensive solution to the TSV module that will include the etching, deposition and Cu plating. Of course they are missing the market leading position that Applied Materials has in the Cu barrier seed PVD equipment.
- Monolithic 3D
- Since Applied Materials own now the implant business they could easily get involved in the smart cut technology from point of view of proliferate it to the rest of the world, as it is currently dominate only by the SOI wafers manufacturing. Owning the RTP and Epi helps well in the Monolithic 3D module.
- No real effect from the Lam Novellus deal.
- The future introduction of Monolithic 3D technology into the Fab present an opportunity to all the equipment manufacturing companies from several new tools that need to be proliferate into the process flow.
Samsung contributes just 7% to the world’s foundry revenue today. But here’s why it could be TSMC’s biggest challenge yet...
Most people will agree that Andy Grove has been the semiconductor industry's most successful CEO. After co-founding Intel and serving as COO for many years, he took over the CEO role and oversaw a 2400% increase in the company’s stock price. Among the present set of semiconductor CEOs, does anyone possess Grove’s high levels of performance, dynamism and vision? There can be only one answer: Morris Chang, the founder and CEO of TSMC.
I’m sure many of you have read Andy Grove’s classic book, “Only the Paranoid Survive”. Let’s now apply the principles in Grove’s book to the foundry industry. If you were Morris Chang and had 50% market share in the foundry industry, which competitor of yours would you be “paranoid” about?
Figure 1: Foundry Revenue in 2011 (Source: SemiMD).
Fig. 1 shows the foundry landscape at the end of 2011. Many competitors show up: there’s Globalfoundries with its plentiful oil money, UMC with its excellent customer service and high yields and SMIC with its Chinese government backing. But, to me, Samsung is undoubtedly the biggest threat to TSMC, even though its foundry market share today is just 7%. Let me explain why... Economies of Scale due to Memory Business Semiconductor manufacturing costs are heavily dependent on economies of scale. Fig. 2 [1][2], which is an estimate of DRAM costs and selling prices in 2003, illustrates this point. The highest volume producer, Samsung, has the lowest raw material costs in Fig. 2. The same goes for semiconductor equipment purchases. A higher volume producer gets a lower price per tool. You’ll notice the highest volume producer (Samsung) has the lowest depreciation cost in Fig. 2. Figure 2: DRAM industry landscape in 2003. Costs are a function of production volumes. (Source: [1][2])
What does this mean for the foundry industry? Well, TSMC, since it has 50% market share, should benefit from economies of scale and build a lead over its rivals, right? That certainly gives TSMC an advantage over UMC and Globalfoundries, but doesn’t work with Samsung. Why? Because Samsung owns a huge chunk of the world’s memory business (~40%). It buys tools and raw materials in huge volumes for those markets, and you use pretty similar tools and raw materials for logic foundry manufacturing. Fig. 3 illustrates that Samsung’s capital expenditure for tools in 2012 is actually double that of TSMC. Samsung might therefore have lower raw material costs and depreciation costs than TSMC.
Figure 3: Samsung buys more semiconductor equipment than TSMC (numbers shown for 2012). Scale of equipment buying provides low prices. (Source: SemiMD)
Yield improvement methodologies Samsung has a great set of yield improvement methodologies developed over its years in the competitive memory industry. Fig. 5 [2] illustrates yields of different DRAM manufacturers in 2003. You’ll notice Samsung has, by far, the best yields. Based on this data and Samsung’s reputation for high-yield memory products, you would expect Samsung to get good yields in the logic foundry business. They seem to be delivering on that front. I hear from industry contacts that Samsung is the only manufacturer getting reasonable yields for gate-first high k metal gate products at 28nm. Figure 4: Samsung’s yield enhancement methodologies gave it an advantage over competitors in the memory industry. (Source: [2]) Low cost fabs In cost sensitive markets such as memory and foundries, the location of a fab makes a difference. Fig. 5 [3] shows a chart from the US National Academy of Engineering which reveals that fab costs in the US are ~25% higher than fab costs in the Far East. Some of TSMC’s competitors have fabs in Europe and the US, but Samsung is building a good portion of its capacity in Korea (they do have one facility in Texas though). The fab cost advantage TSMC has over its other competitors doesn’t necessarily exist with Samsung. Figure 5: Cost of US fabs higher than those in Korea, Taiwan or Singapore. (Source: [3]) Sensible partnership strategy One of the barriers to entry for the foundry business is availability of Intellectual property (IP) blocks and CAD tool support. Intel, which is looking to enter the foundry business, has difficulties with this, since IP blocks haven’t been developed for its technologies yet. SoC makers today show a marked preference for foundries offering competitive IP blocks at low prices. When Samsung entered the foundry industry, it addressed this issue by joining the IBM alliance, and so its customers could use IP blocks developed for the IBM alliance. Samsung did not have much experience developing logic technologies either, and the alliance helped Samsung learn from existing players in the logic business such as IBM and Globalfoundries. In spite of having a similar technology offering to Globalfoundries and IBM, Samsung retains an advantage over these competitors since it is better at ramping up yields and because it has low cost fabs. R&D costs for next-generation logic technologies are $1-2 billion today. Sharing the cost with IBM and Globalfoundries gives Samsung a R&D cost advantage over companies such as TSMC and UMC which develop new technologies alone. Ability to fund large capital expenditures TSMC, UMC, Globalfoundries and SMIC derive almost all their sales from the foundry industry. This limits the amount of capacity they can add every year, since their balance sheets place restrictions on maximum cap-ex to revenue ratio (Globalfoundries is an exception here due to its oil money). Samsung, on the other hand, is a diversified company that sells everything from TVs to DRAM to NAND flash to cell phones. It routinely takes profits from other divisions and invests it in the logic foundry industry. Fig. 6 [4] illustrates this trend. Samsung’s capex to revenue ratio for its foundry business is way higher than anyone else. This added capacity is helping Samsung’s foundry business grow rapidly – notice how Samsung’s froundry revenues increased almost 7x between 2010 and 2012. Samsung used this “capacity-add-like-there-is-no-tomorrow” strategy to become our industry’s biggest DRAM producer, so the foundry folks had better watch out! Figure 6: Samsung has the highest cap-ex to revenue ratio among all foundries. (Source: SemiMD)
Proven Research Expertise
If you talk with engineering folks in our industry and ask them which companies do the best research, you will find Samsung near the top of the list. Let me illustrate Samsung’s research capabilities using Monolithic 3D as an example. They started working on the technology almost 10 years back, and have developed monolithic 3D technologies for NAND flash, SRAM and resistive memories. In addition, their roadmap calls for commercialization of Monolithic 3D NAND flash memories within 2 years. Check out Fig. 7. This is some of the best work I’ve seen on monolithic 3D so far. This phenomenal research capability will help Samsung make strides in the logic space.
Figure 7: Samsung has a long history of developing monolithic 3D technologies.
Caveat While the above capabilities of Samsung threaten TSMC in the long term, there are stormy clouds looming for Samsung in the short term. Apple, which accounts for more than 75% of Samsung’s foundry revenues [4] today, is flirting with TSMC due to its increasingly litigious competition with Samsung in the mobile space. If TSMC executes well and takes this business away from Samsung, it could be a big blow to Samsung’s ambitions. To summarize I explained why I believe Morris Chang will consider Samsung his biggest competitor in the long-term. The economies of scale Samsung has due to its memory business could help its logic operations. Samsung’s superb yield ramp capabilities and low cost Korean fabs are another key asset. Probably the biggest weapon Samsung has is its conglomerate ( chaebol) structure, which allows it to make huge capital investments and grow rapidly. At the start of this write-up, I talked about how Morris Chang has grown TSMC the way Andy Grove grew Intel. One of Andy Grove’s strengths was that he recognized Intel’s biggest challenges, and channelized his “paranoia” and limitless energy into finding counter-measures. What can Morris Chang do to deal with “the Samsung challenge”? In a future blog post, I will describe strategies for this... stay tuned! - Post by Deepak Sekar
 We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses why he believes Monolithic 3D-IC could be less risky than scaling or TSV.
I recently saw this great 5 minute video by Applied Material’s Richard Lewington [AMAT 3D Blog Video] where three types of 3D-IC construction are demonstrated. Note that the first two 3D-IC options he shows (with those plastic blocks) are monolithic. Only the third option is TSV based. What’s going on here? Why is this major equipment vendor talking about monolithic 3D when it seems that most of what the industry is talking about these days are scaling, interposers, and Thru-Silicon-Vias(TSVs)? Let’s take a look. Being a fab-guy (built parts of and worked in Chartered Fab-1 & Fab-2, Sierra Semi’s fab inside National Semi’s Bldg#4, AMI Poci Fab-4, Synertek Fab-3, etc.) I am going to approach this from a process/fab-rat perspective. Because this is a key point to what monolithic 3D is about: it is supposed to bring 3D-IC back into the wafer batch economics of semiconductor processing. No piece part handling expense, TSV/interposer reliability & cost issues, or OSAT troubles (I applaud TSMC for trying to remedy this OSAT part, but am surprised that Global Foundries did not do it first….they could have beaten TSMC to the punch here). The major rule for wafer fabs is Take no Risks….. Everything you do is focused on control: understanding, eliminating, controlling variables. Protect and preserve that huge capital investment so you can pay it down. By definition & nature, fab managers are very conservative. But scaling forced us to do dramatically different and risky things. That’s a major reason why it takes 10+ years for new process/technologies to get into a large production fab. Think about HKMG, Cu BEOL, CMP, strain, plasma metal etching rather than wet (caused lots of corrosion issues/mousebites), to name a few. Even platen cooling (instead of aluminum mask layers) for high current implantation took a long time. Changing from flats on the starting material wafers to the notch took about 10yrs too. At its root, many of these changes took new machines, new chemistries, and/or new process methods (think APCVD, LPCVD, UHVCVD, PECVD, SACVD, ALCVD, MOCVD, RTCVD, …..) Another large risk factor with scaling has been the use of more elements of the periodic table to solve scaling challenges. We did not just alter the form or compound of a known element (bad enough risk-wise); we changed to and added new elements to our expensive wafer fabs. (In fab parlance, all this “newness” added up to what is called the Sphincter Effect) When I started in the industry we used only six elements from the periodic table:  Here is the current periodic table usage: Yet, all of us scientists and engineers, as well as fab managers, solved the problems caused by relentless scaling, and the industry grew…we had a lot of fun, we were supremely challenged, and we solved those challenges. But we also grew grey hair and permanently pinched sphincters.
At what cost? (remember, low cost is crucial to successful manufacturing!)
Here’s what Global Foundries showed about costs:
So, now we have now included the investment and banking communities into our Sphincter Effect.:-)) Enough! This is the road to ruin; well, at least to vastly diminishing returns (think Handel Jones’ chart [ElectroIQ link to ISS12 Day 2] on how transistor cost is no longer going down…) 3D-IC is the solution. OK, so…. monolithic or TSV or interposer? Above I already mentioned a few of the risks and costs to a TSV/interposer solution. Look at all the new processes and machines that had to be developed to etch and fill such deep holes at least somewhat economically. And the integration issues are significant because of the novelty and the architecture & flow: Cu/silicon stresses, keep out zones, liners, new reliability fail modes, etc. As usual, these issues will likely be solved; hence, TSV & interposers will be useful for obtaining some cost and functional/architectural gains from its limited vertical connectivity. But they are not the endgame. To get fully back onto the economic scaling path we need rich vertical connectivity. What about monolithic 3D-IC risks & costs? Fab equipment and unit processes exist. No new elements from the periodic table are necessary. And the gains resulting from this dense vertical connectivity keep us on a scaling equivalent path (no need to spend space here…lots has been written about this). Let’s instead look at the process details: Oxides for ox-ox direct bonding: Deposited oxides are well understood and cheap. No new equipment or elements are needed. Lots of manufacturing proven techniques to get there: PECVD, SACVD, etc. H Implant: Can be done on current models. No new equipment needed. Done by SOI manufacturers for 20 years. H in silicon is well understood. Bonding: Two well-known equipment vendors (EVG & SUSSMicroTec) with low temp oxide to oxide bonding capability and significant sales of machines (mostly to BSI sensor folks at this time). A recent third new entry (MHI-Mitsubishi Heavy Industries) with room temp ox-ox bonding. I recently blogged on this topic too. [BC LT direct bonding] Cleave: Lots of methods proven for SOI manufacture, sensors, and solar. Simplest is thermal … just use a furnace or RTP. We made a short movie clip showing how simple cleave is with the AG RTP at Stanford. Monolithic 3D-IC uses existing wafer-fab equipment, needs no new elements from the periodic table, and utilizes well-known unit processes and chemistries. What’s the catch? It’s the integration. Integration work ( blood, sweat, and tears) will always be there, even with no new elements, machines, chemistries, etc. Always. However, those who have done new process introductions know that integration is significantly less risky (= costly) and faster to market without than with the elements/machine/chemistry changes. New modes of defect generation are always generated from integration, but there are a lot less of them if all the unit processes are standard accepted practices, than if those unit processes are totally new. If you look very very carefully at the MonolithIC 3D Inc’s process flows, you notice we were single mindedly focused on making it simple. For example, the nm-scale thru layer vias (TLVs) are always made thru the STI (Shallow Trench Isolation); hence, no dielectric liners, minimum stress, conventional etch and fill, nothing high aspect ratio about it. Make the TLV look and feel like a regular metal to metal via. This shows in the costs. Deepak Sekar did a SEMATECH based cost estimate and talked about it in a blog. [Deepak Blog ion-cut cost] Here’s his summary chart for 300mm wafers. Validation of Monolithic 3D One may make the argument that validation of a nascent & new game-changing technology is impossible, or at least very nearly so. However, for monolithic 3D-IC there are at least two important data-points to consider. And I hope that you will be convinced that monolithic 3D-IC is neither so nascent nor new. NAND Memory Makers going 3D: People such as David Lammers of Semiconductor Manufacturing & Design Community [Lammers July 2011] have pointed to validation evidence that the time of monolithic 3D-IC is near: the bleeding edge NAND memory makers are already moving to monolithic 3D-IC. “The advent of 3D NAND memories may be only two or three years away, speakers said at Semicon West in San Francisco. By 2013 the major memory companies developing 3D NAND, including Hynix, Samsung, and Toshiba, may be ready with pilot lines, moving to volume production a year or so later. Taiwan-based Macronix International also has been developing a 3D NAND solution.” At the recent (2011) VLSI Symposium J. Choi of Samsung showed their view of how they will keep on making cheaper bits … by going 3D monolithically. Second, the global semiconductor equipment leader, AMAT, has talked about sales into that market [SemiconWest2011-new products including 3D architecture support] [OptivaCVD for BSI] and even has a video (Richard Lewington’s blog video noted above) to promote it. When both manufacturers and equipment suppliers are talking about, committing to, and executing on a specific technology change, you know that the economics are attractive and not just niche. Think back to how HKMG and copper BEOL came to production. The chicken and egg are out the window….it’s happening now. The risks are contained. Others are going for it. Whether polysilicon or monocrystalline silicon based monolithic 3D, jump in and be a part of this next important evolution of our great industry. Don’t miss out.
Today, we'll discuss why TSV pitches smaller than 500nm are useful and how one can achieve that. Evolutionary advances with today's TSV technology as well as radically new monolithic 3D approaches are options. The Silicon Valley IEEE Components, Packaging and Manufacturing Technology (CPMT) Society invited me to give a talk on "Fine-Grain 3D Integration" last week. In case you're not familiar with this IEEE chapter, they host speakers from around the Valley periodically. Check out their website if you get a chance - they have some nice talks lined up for the future. Now, let me describe the stuff I presented there. IntroductionAs many of you know, 3D technologies in the marketplace today have huge TSVs. For example, TSMC's 28nm technology has 6um diameter TSVs with 5um keep-out zone. Other manufacturers are offering similar TSV sizes too. When you start comparing these with on-chip feature sizes (28nm), you'll understand why I use the term "huge" to describe these TSVs. In contrast, fine-grain 3D technologies are defined as those having TSV pitches smaller than 500nm. Why Fine-Grain 3D Integration?There are many applications that benefit from small TSV sizes. Fig. 1 describes the basic motivation - wires consume a lot more energy than transistor-based computation today, and 3D can reduce lengths of these wires. Micron-scale TSVs can reduce chip-to-chip wire lengths, but smaller TSVs are needed to reduce on-chip wire lengths.  Figure 1: Situation in nVIDIA's 28nm chips. Below are some uses for fine-grain 3D. Note that small TSV sizes (around minimum feature size) are required for some of these applications: - Short on-chip wires in logic cores and SoCs: Components within a single logic chip can be stacked atop each other to shorten on-chip wires. This leads to smaller gates, since these gates need to drive less wire capacitance. The result is reduced power and die size. Analyses show that a 2x reduction in power, a 2x reduction in silicon area and a 4x reduction in chip footprint may be possible by doubling the number of 3D stacked layers (link).
- Logic-SRAM stacking: The requirements of logic devices and SRAM on a chip are very different today. SRAM circuits typically require just 4 metal levels compared to 12 for logic circuits. SRAM transistors have different channel length, oxide thickness and threshold voltage compared to logic transistors too. In this scenario, it makes sense to stack SRAM and logic in 3D. The SRAM layer can be optimized for 4 metal levels and SRAM-type transistors, thereby saving cost.
- nMOS and pMOS stacking: Today's nMOS and pMOS transistors have different gate stacks, strain layers, implants and wells. Separate lithography steps are required for all of these. To save cost, one could stack the nMOS and pMOS atop each other. This reduces standard cell area too. Analysis from IBM shows that 30-40% reduction in standard cell area is possible for inverters, NAND and NOR cells by stacking nMOS and pMOS layers atop one another. Smaller standard cells result in shorter wires, improving power and performance.
Limitations of today's TSV technologyLike many engineers, I believe understanding a problem is important for figuring out a solution. So, let's analyze why today's TSVs are so fat. Fig. 2 shows a typical process for high-density 3D-ICs.  Figure 2: Process flow for a bumpless bonded 3D TSV technology. The limiting steps for TSV size in these face-to-back bonded technologies are: Step 5: Wafer thinning - Aspect ratio limitations of TSV manufacturing processes nowadays are around 10:1. To get 1um diameter TSVs, one needs to have a 10um thick silicon layer. For this scenario, during the thinning step, a 775um thick wafer needs to be thinned down to 10um +/- 1um (10% tolerance). This 1um tolerance is very hard to achieve at high throughput. Many manufacturers take the easy way out and thin the silicon wafer from 775um to 50um +/- 5um (10% tolerance). For an aspect ratio of 10:1, a 50um silicon thickness will lead to 5um diameter TSVs. Step 7: Wafer alignment - In this step, the top and bottom layers are aligned with each other and bonded. Misalignment occurs due to several reasons: - 3D align and bond tools on the market often do not have the stable alignment stages and image capture/storage required for sub-500nm pitch TSVs.
- Co-efficient of thermal expansion (CTE) mismatch between the top and bottom layers, wafer bow, thermal and stress induced flow of temporary bonding adhesives, localized bonding imperfections and other issues can cause um-scale misalignment.
Evolutionary Improvement of Today's TSV Technologies
In this section, I will summarize evolutionary ways to improve today's TSV technologies. IBM and MIT Lincoln Labs are the pioneers in this area, as are image sensor makers such as Sony and Omnivision.
Wafer thinning techniques - Fig. 3 shows approaches to reduce wafer thickness from 775um to less than 1um. The method in Fig. 3(a) works for SOI wafers. Buried oxide layers of SOI wafers are used as etch stops to get low silicon thickness with sufficient precision. An alternative approach for bulk silicon wafers is shown in Fig. 3(b). Silicon etch solutions such as EDP have orders of magnitude lower etch rates for p++ silicon compared to p silicon. One could therefore use a p++ layer in a silicon wafer as an etch stop. Both these techniques are starting to be used in manufacture of back-side illuminated image sensors.
 Figure 3: Next generation wafer thinning technologies that use etch stop layers. Techniques to improve alignment accuracy - For high density TSVs, companies prefer to use glass carrier wafers at present. The transparency of glass, combined with low silicon thickness of transferred films, allows one to look through the top wafer and align. Limitations of 3D alignment tools can be overcome with this technique. In addition, if glass carrier wafers are used, adhesives for attaching silicon to a carrier wafer can be optically debondable. Optically debondable adhesives are more stable at the high temperatures needed for bumpless bonding. Besides using glass carriers, one could do a few more things: - Use CTE matched carrier wafers - Even if you use borosilicate glass with an excellent CTE match with Si, a small CTE mismatch is introduced at bond temperatures. For example, at 300C, silicon wafer diameter can increase by 314um while borosilicate glass diameter can increase by 264um. This difference in diameter can introduce alignment error. If you want to get sub-500nm pitch, costlier glasses that have CTE-match with silicon at various temperatures are required (Fig. 4(a)).
- Use oxide-to-oxide bonding - For fine-grain 3D, oxide-to-oxide bonding is the technique of choice due to the low temperatures involved vs. Cu-Cu bonding. Lower temperatures reduce CTE mismatch errors. In an oxide-to-oxide bonding process, a weak bond is formed at room temperature. Following this, a post-bond anneal (~300C) is done to get a stronger bond. The alignment got at room temperature is largely maintained. Less than 400nm misalignment is introduced by the post-bond anneal (Fig. 4(b)).
- Use wafer bow compensation - Wafers can frequently have bow of 50-100um, making sub-micron alignment accuracy difficult while bonding. IBM and MIT have developed wafer bow compensation schemes to reduce this. For example, one could deposit thin films on back sides of wafers to compensate partially for the wafer bow. See Fig. 4(c).
Click to enlarge.
Figure 4(a)-(c) from left to right: (a) CTE match of various glasses with silicon. (b) Change of alignment after post-bond anneal. (c) Wafer bow compensation schemes.
IBM built prototypes utilizing many of these techniques. SOI wafers and buried oxide etch stop layers enabled transfer of thin silicon. CTE-matched borofloat glass carriers, oxide-to-oxide bonding and wafer bow compensation schemes were used. IBM's best prototypes had a TSV pitch of 6.7um, and they said 2um pitch would be possible when bonders with sub-0.5um alignment accuracy are available (which is the case today). Essentially, we can reduce TSV pitches from the 20um we get in the marketplace today to around 2um. I believe it may be possible to lower TSV pitches to less than 500nm by improving processes further. Please see slides of my talk for details.The Monolithic 3D PathWith monolithic 3D technology, additional transistor layers are constructed monolithically atop Cu/low k layers. This could lead to TSV size close to minimum feature size, which is needed for many of the fine-grain 3D applications described above. Fig. 5 indicates the main barrier to creating high-quality transistors at Cu/low k compatible temperatures (sub-400C) is dopant activation.  Figure 5: Steps required for constructing a silicon transistor. Fig. 6 describes one approach to overcome this problem, which utilizes recessed channel transistors. These have been used in DRAM manufacturing since the 90nm node, and are known to be competitive with standard planar transistors. As can be seen in Fig. 6, high temperature dopant activation steps are conducted before transferring bilayer n+/p silicon layers atop Cu/low k using ion-cut. For ion-cut, hydrogen is implanted into a wafer at a certain depth creating a defect plane. Following this, the wafer is bonded to the bottom device layer using oxide-to-oxide bonding. The bonded structure can now be cleaved at the hydrogen plane using a 400C anneal or a sideways mechanical force. CMP is done to planarize the transferred surface. Transferred layers are unpatterned, therefore no misalignment issues occur while bonding. Following bonding, sub-400C etch and deposition steps are used to define the recessed channel transistor. This is enabled by the unique structure of the device. These transistor definition steps can use alignment marks of the bottom Cu/low k stack since transferred silicon films are thin (usually sub-100nm) and transparent. Minimum feature size through-silicon connections can be produced due to the excellent alignment.  Figure 6: (a) A recessed channel transistor (b) Process flow for monolithic 3D logic. Bottom device layer with Cu/low k does not see more than 400C. Through-silicon connections can be close to minimum feature size due to the thin-film process.
A few points about Fig. 6: (i) All materials, process steps and device structures are well-known and are used in high-volume manufacturing (ii) The original donor wafer with n+ and p layers can be reused after layer transfer. This is an advantage over today's TSV processes, where one spends time and cost etching away a 300mm wafer that costs $120. (iii) Though-silicon via connections are minimum feature size, enabling large improvements (As described previously, benefits can be 2x lower power, 2x lower silicon area by doubling the number of device layers. nMOS and pMOS stacking is possible.) The main risk is the use of DRAM-type recessed channel transistors in logic technologies. My somewhat biased view is that recessed channel transistors have been used in DRAM manufacturing since the 80nm node, so they may not be difficult for logic manufacturers to bring up and make competitive (especially for low-power applications).
Anyway, it is time to sign off now. If you are at the IEEE 3D System Integration Conference in Japan next week, don't forget to attend MonolithIC 3D Inc.'s presentation. I will be giving an invited talk titled "Monolithic 3D-ICs with Single Crystal Silicon Layers".
Disclosure: I work at MonolithIC 3D Inc., a company developing monolithic 3D technologies. I have tried to be as unbiased as possible while describing 3D-TSV and monolithic 3D technologies. However, if you disagree with something written in this blog post, please let me know in the comments section. I would welcome the discussion. Thank you.- Post by Deepak Sekar
 _We have a guest contribution today from Ze'ev Wurman, MonolithIC 3D Inc.'s Chief Software Architect. Ze'ev discusses yield and repair issues with 3D stacked chips.
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