We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about Intel vs. TSMC.

On Nov 21, 2013 Intel CEO Brian Krzanich, in the company Investor Meeting, presented company expansion focused on a foundry plan. “You will see us focusing on a broader set of customers,” said Krzanich. “If somebody can use our silicon, and make computing better, than we want it to run better on Intel. It’s inclusive, it’s all-inclusive,” Krzanich added, as covered by Barron's blog Intel: Competitors Have Given Up ‘Scaling’ Advantage in Moore’s Law

Intel clearly believes that it can beat the pure play foundries by an ongoing reduction of transistor cost while improving performance and power with dimensional scaling – essentially maintaining the trend of Moore's law just as in the past. Intel will “not take our foot off the pedal” of process technology, Krzanich explained, and he expects the company to be making parts as small as 10 nanometers in transistor size by 2015, versus today’s 22 nanometer parts. He was followed by Bill Holt, Intel’s EVP and head of semiconductor manufacturing, showing the following slide describing Intel expectations to drive down the cost per transistor. 

 Maintaining dimensional scaling is in-line with Holt’s previous slide presented at the Jefferies May 2013 Analyst Meeting:

Here we observe the first discrepancy where Intel says they are "continuing to scale while others are pausing to do FinFETS”, while the other foundries say that their transistor cost will not be reduced for nodes below 28nm. This was made very clear by GlobalFoundries in it recent seminars and is nicely illustrated in this ASML Semicon West 2013 slide:

This has also been generally accepted by analysts. Below is a slide from IBS’s Handel Jones presentation at the CEA-LETI day in June of this year:

       Some may argue that Intel will have a hard time competing as a foundry due to potential customer concern of Intel as a competitor. This is a valid point but it did not stop Apple to buy cell phone devices from Samsung.

           Some may argue that Intel will have hard time competing due to the lack of broad EDA and IP support. This is also a valid point but Intel does not need to win all fabless designs. If Intel wins just the few super high volume designs, it may well win the war.

           Some may argue that “Intel announced their high volume mobile SoFIA chips are mask fabricated at external foundry and do not use Intel internal manufacturing for at least next 2 years (2014-15). ALL of Intel's production for standalone modem chips today is outside Intel. Conclusion being Intel still does not have the right silicon technology for mobile computing which is why X86 less than 0.1% of Smartphone market" as one commenter at Intel Nears Foundry Inflection Point blog. This might be why Holt presented Intel’s plan to develop Foundry type processes. “Those products were optimized primarily for performance, and so Intel had avoided the problem that can crop up when transistors are packed more densely, namely that performance of the wires connecting transistors, the interconnects, can degrade. We didn’t scale the wires as much as we could have, because the products we were building didn’t demand that.” Now, he said, "the company’s technology would be focused more on those interconnects as Intel takes the scaling lead. The result would be the ability to more nimbly move between transistors optimized for performance, on the one hand, as in server and desktop chips, and transistors optimized for low-power mobile devices." as illustrated below:

It would seem that if Intel could scale transistor cost as they have done in the last 40 years then they could win these super high volume consumer-oriented designs where cost is extremely important. And TSMC is clearly taking this seriously. As was made public after they lost Altera to Intel, TSMC aligned itself to face head-on Intel’s challenge by expediting the development of FinFet technology.

As TSMC's P/E is 14.42 while Intel's P/E is only 12.87 the market should have responded very well to these presentations but apparently it did not — and in reverse to NASDAQ trend, Intel stock fell more than 5% the day after:

Nor did Altera's stock perform well since announcing the move to Intel as a foundry, especially when compared to Xilinx who choose to stay with TSMC, as the stock price chart below illustrates:

The Stock market might be wrong, as it been wrong many times before, but then there are other concerns:

• Why did Intel feel the need to put so much money in the ASML EUV program if they can do just as well without EUV?
  
  
• Does Intel reduced cost per transistor account for its escalating cost of R&D, which in 2013 averaged more than 20% of revenue vs. less than 14% in 2005?
  
  
• Does Intel reduced cost per transistor account for its escalating cost of capital, which, per their balance sheet on Depreciation/Depletion, averaged in 2013 more than 26% of revenue vs. less than 10% in 2011?
  
  

It is not clear what the Intel proprietary technology is that allows it to do so much better than the foundries to produce a per transistor cost reduction. It does seem that their fab equipment and especially lithography is the same. And it also unclear why the Intel per transistor costs are not impacted by the much higher cost of lithography with the double and quadruple litho steps needed in manufacturing these advanced process nodes and the extra development and process steps required.

There is one more important issue that seems to be ignored. For SoC applications the embedded SRAM is a key factor because it dominates the die area, as we recently presented in our blog Are we using Moore’s name in vain?. If Intel’s embedded SRAM is scaling each node as before then it would represent an important advantage over the foundries. Yet Intel recently announced integration of DRAM into Haswell and promised future Xeon and Xeon Phi models that integrate memory atop processors in 3D packages instead. Will these be aggressive enough to keep the on-system memory costs scaling?  

In short, if Intel could keep the traditional 30% cost reduction per node from 28nm to 10nm, and the foundry’s cost per transistor is staying flat, then Intel would be able to provide their foundry customers SoC products at a third of ther other foundries cost, and accordingly Intel should be able to do very well in its foundry business.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about Moore's Law and the impact of it on the industry today.

The assertion that Moore made in April 1965 Electronics paper was:"Thus there is a minimum cost at any given time in the evolution of the technology. At present, it is reached when 50 components are used per circuit. But the minimum is rising rapidly while the entire cost curve is falling (see graph below)." 

"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years."

Clearly Moore's law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays - transistors) to achieve minimum cost will double every year.
The reduction of cost per component for many years was directly related to the reduction in feature size - dimensional scaling. But many other technology improvements made important contributions as well, such as increasing the wafer size from 2" all the way to 12".
But many observers these days suggest that 28nm will be the optimal feature size with respect to cost for many years to come. Below are some charts suggesting so:

And more analytical work by IBS’ Dr. Handel Jones

Graphically presented in the following chart

Or as nicely drawn by Globalfoundries

Recently EE Times reported that EUV Still Promising on IMEC's Road Map. IMEC provided a road map to transistor scaling all the way to 5nm, as illustrated in the following chart:

Yes, we probably can keep on scaling but, clearly, at escalating complexity and with completely new materials below 7nm. As dimensional scaling requires more advanced lithography it is clear that costs will keep moving up, and the additional complexity of transistor structures and all other complexities associated with these extreme efforts will most likely drive the costs even higher.
Looking at the other roadmap chart provided by IMEC and focusing on the SRAM bit cell in the first row, the situation seems far worse:

Since at 28 nm SRAM bit cell is already 0.081μm2, this chart indicates that future transistor scaling is barely applicable to the SRAM bit cell, which effectively is not scaling any more.
Unfortunately, most SoC die area is already dominated by SRAM and predicted to be so even more in the future, as illustrated by the following chart:

Source:. Y. Zorian, Embedded memory test and repair: infrastructure IP for SOC yield, in Proceedings the International Test Conference (ITC), 2002, pp. 340–349
Dimensional scaling was not an integral part of Moore's assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore. The following chart captures Samsung’s view of the future of dimensional scaling for NV memory, and it seems relevant to the future of logic scaling just as well.