We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc.
Next week, as part of the IEEE S3S 2017 program, we will present a paper (18.3) titled “A 1,000x Improvement in Computer Systems by Bridging the Processor Memory Gap”. 

Next week, as part of the IEEE S3S 2017 program, we will present a paper (18.3) titled “A 1,000x Improvement in Computer Systems by Bridging the Processor Memory Gap”. The paper details a monolithic 3D technology that is low-cost and ready to be rapidly deployed using the current transistor processes. In that talk, we will also describe how such an integration technology could be used to improve performance and reduce power and cost of most computer systems, suggestive of a 1,000x total system benefit. This game changing technology would be presented also in the CoolCube open workshop, a free satellite event of the conference 3DI program.

In an interesting coincidence DARPA just came out with a calls for >50x improvement in SoC

The 3DSoC DARPA solicitation reads: “As noted above, the 3DSoC technology demonstrated at the end of the program (3.5 Years) should also have the following characteristics:

–Capability of > 50X the performance at power when compared with 7nm 2D CMOS technology.
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The 3DSoC program goal of 50x is to allow proposals suggesting US-built device at 90nm node vs. 7nm of computer chip using conventional 2D technologies. Looking at the table below we can see that if 7nm technology is used the benefit would be over 300x

This represents a paradigm shift for the computer industry and high-tech world, as normal scaling would provide 3x improvement at best. The emergence of AI and deep learning system makes memory access a key challenge for future systems, and indicate the far larger benefits offered by monolithic 3D integration.
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The following charts were presented by the 3DSoC program manager Linton Salmon at the 3DSoC proposers day. The program calls for the use of monolithic 3D to overcome the current weakest link in computers – the memory wall.

Leading to the 3DSoC solicitation was work done by Stanford, MIT, Berkeley and Carnegie Mellon

Proposals are due by Nov 6.
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There is a unique opportunity to hear the 3DSoC DARPA Program Manager, Dr. Linton Salmon, articulate the program and what DARPA is looking for during his invited talk at the S3S 2017 conference next week.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc.
As recently reported, in an effort to initiate resurgence of the U.S. electronics industry, some $500-$800 million will be invested in post-Moore's Law technologies.

Quoting from the BAA: “As noted above, the 3DSoC technology demonstrated at the end of the program (3.5 Years) should also have the following characteristics:

1. Capability of > 50X the performance at power when compared with 7nm 2D CMOS technology.
2. …” This is a paradigm shift for the computer industry and to high-tech world as normal scaling would provide as 3x at best, as indicated by the following well known chart:

The following charts were presented by the 3DSoC program manager Linton Salmon at the 3DSOC proposal day. The program calls for the use of monolithic 3D to overcome the current weakest link in computers – the memory wall. This is illustrated in the following slides:

Leading to the 3DSoC solicitation was work done by Stanford, MIT, Berkeley and Carnegie Melon, summarrized in the following two slides.

Proposals are due by Nov 6. Everyone has a unique opportunity to hear an invited talk about the program on October 16 from the 3DSoC DARPA Program Manager, Dr. Linton Salmon during this year’s IEEE S3S conference at the Hyatt Regency at the San Francisco Airport. The IEEE S3S conference has dedicated focus on monolithic 3D technologies.
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3D integration is considered expensive and monolithic 3D is considered extremely challenging requiring high technology, investment, and major changes to the foundry process. In an interesting entanglement, the S3S 2017 program includes a paper by us, MonolithIC 3D Inc., in which we will present a monolithic 3D technology that is low cost and ready to be rapidly deployed using the current transistor processes. In that talk we will also describe how such an integration technology could be used to improve performance and reduce power and cost of most computer systems, suggestive of a 1,000x total system benefit. I hope to see you there to talk further about this upcoming disruptive change.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc.
A technology that could bridge the processor memory gap, Monolithic 3D has DARPA's attention. The agency wants proposals by Nov 6. Learn more at an upcoming IEEE conference.

On Sept 13 the Defense Advanced Research Projects Agency (DARPA) launched a giant funding effort to ensure the United States will sustain the pace of electronic innovation vital to both a flourishing economy and a secure military. Under the banner of the Electronics Resurgence Initiative (ERI), some $500-$800 million will be invested in post-Moore’s law technologies.

Among those is the 3DSoC program. “The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program" DARPA wrote in a statement, "is to develop 3D monolithic technology that will enable > 50X improvement in SOC digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures for future designs while utilizing U.S. fabrication capabilities.” As is illustrated in the following chart:

The foundation for the 3DSoC program were formed in prior DARPA research work performed by Stanford University in collaboration with Berkeley and CMU, Energy-Efficient Abundant-Data Computing: The N3XT 1,000×
The underlying problem enabling these orders of magnitude improvement is often called “The Memory Wall” illustrated by the following chart from Hennessy and Patterson:

The main source of the gap is the limited number of long wires connecting memory to processor. This is driven by the fact that typically the process line for memory is very different than of processor, resulting in memory chips aggregated to memory modules and being connected to the processor using printed circuit board or, at best, carrier substrate. A technology that could bridge this gap — Monolithic 3D — has the potential to provide more than 1,000x better computers.

DARPA kept the target enhancement to only 50x to allow use of chip manufactured in domestic older fab (~90nm) instead of off-shore 7nm fab lines.

Proposals are due by Nov 6, allowing everyone a unique opportunity to hear an invited talk about the program on October 16 from the 3DSoC DARPA Program Manager, Dr. Linton Salmon during this year’s IEEE S3S 2017 at the Hyatt Regency at the San Francisco Airport. The IEEE S3S conference is dedicated to monolithic 3D technologies. It provides unparalleled opportunity for quick catch up with the broad spectrum of monolithic technologies.

At the conference’s start Al Fazio, Intel Senior Fellow, will deliver a plenary talk on how 3D NAND and 3D XPoint ended being the trailblazing monolithic 3D IC technologies that have matured to volume production, taking over the fast growing memory market. The first day will conclude with two 3D IC focus sessions comprised of a mix of invited and submitted papers covering exotic technologies and the use of the emerging nano-wire transistors for 3D scaling.

The first half of the second day includes a collaborative event organized by Qualcomm and CEA Leti — the COOLCUBE/3DVLSI Open Workshop. The second half includes an open 3D tutorial providing full coverage of the various 3D integration technologies from TSV to Sequential Integrations. 

The third day is made of four sessions of invited and submitted talks on monolithic and other forms of 3D integration. These sessions include a talk by MonolithIC 3D Inc. in which we will present a monolithic 3D technology that is ready to be rapidly deployed using the current transistor process. We will also describe how such an integration technology could be used to improve performance, reduce power and cost of most computer systems, suggestive of a 1,000x total system benefit.

In addition, the IEEE S3S conference includes full coverage of SOI and low-power technologies, making it the place to be and to learn about alternative technologies to dimensional scaling. I am looking forward to seeing you at the S3S from October 16th thru 19th, 2017.
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