We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about "Chip 2020" book review.
A recent book review by Peter Clarke on this wonderful new book by Bernd Hoefflinger caught my eye, and also reminded me of an old connection I have with Hoefflinger.
Early in the 90's I had the pleasure to collaborate with Hoefflinger, who at that time was the director of the Institute for Microelectronics Stuttgart (IMS CHIPS). I was the CEO of Chip Express then and we worked together to demonstrate that applying Direct-Write-eBeam to a Chip Express wafer could lead to a very effective Gate-Array prototyping scheme and to low volume production of those Gate-Arrays.
It was great pleasure to reconnect and to read "Chip 2020"
I highly recommend this book as it provides an update view of the Semiconductor Industry by a group of known experts in our field.
The book provides a concise review how we got here and what is ahead for us up to the year 2020.
The book presents a now more common view that the scaling that got us here is gone, and that there are concrete red-bricks for dimensional scaling beyond 2020. Primarily:
1. As gate sizes reach ~10nm we would have nominally 6 atoms of impurity in the channel with a commensurate variation that would constrain effective use of the transistor -see Fig. 1.1
Early in the 90's I had the pleasure to collaborate with Hoefflinger, who at that time was the director of the Institute for Microelectronics Stuttgart (IMS CHIPS). I was the CEO of Chip Express then and we worked together to demonstrate that applying Direct-Write-eBeam to a Chip Express wafer could lead to a very effective Gate-Array prototyping scheme and to low volume production of those Gate-Arrays.
It was great pleasure to reconnect and to read "Chip 2020"
I highly recommend this book as it provides an update view of the Semiconductor Industry by a group of known experts in our field.
The book provides a concise review how we got here and what is ahead for us up to the year 2020.
The book presents a now more common view that the scaling that got us here is gone, and that there are concrete red-bricks for dimensional scaling beyond 2020. Primarily:
1. As gate sizes reach ~10nm we would have nominally 6 atoms of impurity in the channel with a commensurate variation that would constrain effective use of the transistor -see Fig. 1.1
2. As lithography tools are already forced to use double exposure/processing it has became unclear if an effective lithography is going to be available to move forward. See the Table 8.3 below, provided by Burn J. Lin of TSMC
Clearly the future cost of lithography eats away at the cost advantage of dimensional scaling.
Hoefflinger presents some options to tackle these challenges as detailed through the book and with respect to specific segments of the industry. The following Fig. 3.1 presents these future technologies:
Hoefflinger presents some options to tackle these challenges as detailed through the book and with respect to specific segments of the industry. The following Fig. 3.1 presents these future technologies:
At MonolithIC 3D we were pleased to see the important role given to 3D IC in the book as shown in the Fig. 3.1 above.
In short I fully agree with Peter Clarke’s statement: "The book offers some far-reaching and fundamental insights" and I highly recommend the book to semiconductor technologists who are looking forward toward the next decade of progress in the field.
In short I fully agree with Peter Clarke’s statement: "The book offers some far-reaching and fundamental insights" and I highly recommend the book to semiconductor technologists who are looking forward toward the next decade of progress in the field.
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