Hughes Metras, Leti’s VP of Strategic Partnerships North America, introduced the lead talk at their SemiconWest 2014 Leti Day about monolithic 3D technology as the “solution for scaling.” Hughes presented the Leti device technology roadmap which showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to well past 5nm. Here’s the important piece of that roadmap, which highlights the partnership with Qualcomm (ST and IBM helped with some of the work as well):

The lead talk was given by device scientist Olivier Faynot, Leti’s Device Department Director.  He titled his talk “M3D, a disruptive approach for further scaling,” and began with why the industry needs a solution for scaling.

Most in the industry are in agreement that scaling past the 22nm node, while still quite technically feasible, has priced itself out of most markets. Olivier discussed the what (transistor costs are no longer decreasing) and the why (litho cost escalation and connectivity inefficiencies of energy and delay). And then he made the statement: “if we just keep the current (2Xnm) technology, we can go farther in cost scaling.” [note: see the following blogs and comments for more info on this crucial topic:  Tech Design Forums summary "3D and EDA need to make up for Moore’s Law, says Qualcomm" and Zvi-Or-Bach’s EETimes blogs Qualcomm Calls for Monolithic 3D IC and  28nm - The Last Node of Moore's Law.]

Oliver showed a summary of a DAC2014 paper and a Qualcomm/GeorgiaTech DAC2014 paper Power/Performance/Area analysis of M3D for an FPGA:

The solution is to build the stack sequentially, in a monolithic fashion. Olivier described their monolithic 3D, or sequential 3D, process flow where the lower-level (first layer) of transistors and its interconnect are conventionally made, then inter-level metal is crafted to help the vertical interconnection, and then a second layer of monocrystalline silicon is layer transferred and oxide-oxide low temperature bonded to the top of the inter-level metal dielectric. This is a blanket layer so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin (10-200nm final), so that direct alignment thru that thin layer to the lower level alignment marks can be made with conventional equipment and achieve conventional alignment tolerances (single digit nanometers).

Now upper-level transistors are formed utilizing SPER (Solid Phase Epitaxial Regrow) for junction doping at 475-600°C and other lower (<400°C) temperature processing for gate stacks, etc. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. Note that the lower level transistor Ni salicides are stabilized with platinum co-deposition and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.

Oliver also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. He called the laser (pulsed and short wavelength) option of solving the thermal challenge of monolithic 3D as the “crème brûlée” of methods and they were ‘seeing good results.’ Hopefully we will see published data soon. For more information on SPER and laser processing please see my recent blog Monolithic 3DIC: Overcoming silicon defects.

Oliver was also asked in the Q&A if stress was a big issue. He replied that stress was not an issue, rather, the biggest challenges were integration ones (how to form a low temp top transistor, stability of the local interconnect level, and the bottom transistor salicide stability). Olivier was asked in the Q&A what the observed performance differences were between the upper-level and lower-level transistors. He replied” Currently we are achieving 95% (of the lower for the upper). We believe we can make 100%.”

Leti has a 14nmPDK ready to go for those who want to design a test circuit in their monolithic 3D flow. They have ELDO, HSPICE, Virtusoso, Calibre, StarRC, etc. files available.

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December 2013, Leti signed an agreement to work with Qualcomm – Qualcomm to Evaluate Leti’s Non-TSV 3D Process. ST and IBM have also been working with Leti in various aspects, for example, IBM & Leti used COMPOSE3 to simulate a monolithic InGaAs nFET monolithically over a SiGe pFET on SOI.

CEA-Leti has been busy working on processing flows to enable monolithic 3D devices since before 2009. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper entitled, “Advances in 3D CMOS Sequential Integration,” where she showed results for a sequentially processed P over N (no metal between transistors layers) testchip Batude’s 2011 IEDM paper showed a 50nm 3D sequential structure on 10nm channel silicon:

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications, both parallel and monolithic, with an inauguration event in January 2011. As well, back in December 2013, Soitec and CEA renewed their long-standing partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. I would like to invite you to the IEEE S3S Conference: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference will be held October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

See you there!

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about monolithic 3d technology for future scaling.

At the CEA-Leti Day July 8 during Semicon West, Hughes Metras, Leti's vice president of strategic partnerships for North America, introduced the lead talk about monolithic 3D technology as the "solution for scaling." The Leti device technology roadmap that Hughes presented showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to past 5 nm.Olivier Faynot, Leti's device department director and a well-known device scientist (with more than 170 papers/publications), entitled his talk "M3D, a disruptive approach for further scaling" and started with why the industry needs such a solution.

The majority of people in the industry agree that scaling past the 22nm node, though still quite technically feasible, has priced itself out of most markets. Faynot discussed the "what" (transistor costs are no longer decreasing) and the "why" (litho cost escalation and connectivity inefficiencies of energy and delay). Then he said, "If we just keep the current [2Xnm] technology, we can go farther in cost scaling."

Tech Design Forum's summary of a Qualcomm executive's DAC 2014 keynote offers more information on this crucial topic. So do a pair of EE Times blogs by Zvi Or-Bach.

The solution is to build the stack sequentially in a monolithic fashion. (See Monolithic 3D IC Technologies.) Faynot described a process flow wherein the lower level (first layer) of transistors and its interconnect are made conventionally, some interlevel metal is crafted to help the vertical interconnection, and a second layer of monocrystalline silicon is layer transferred and oxide-oxide bonded at low temperature to the top of the interlevel metal dielectric. This is a blanket layer, so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin, so that direct alignment to the lower-level alignment marks can be made with conventional equipment, and conventional alignment tolerances (single-digit nanometers) can be achieved.

Upper-level transistors are formed utilizing solid-phase epitaxial regrow (SPER) for junction doping at 475-600°C and lower-temperature processing (less than 400°C) for things like gate stacks. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. (Note that the lower-level transistor salicides are stabilized with platinum and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.)

In the Q&A session, Faynot was asked what the observed performance differences were between the upper-level and lower-level transistors. "Currently, we are achieving 95%" of the lower for the upper, he said. "We believe we can make 100%."

He also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. The laser option of solving the thermal challenge of monolithic 3D is the "crème brûlée" of methods, and Leti is "seeing good results." Hopefully, we will see published data soon. My recent Solid State Technology blog offers more information on SPER and laser processing.

Faynot was also asked if stress is a big issue. He replied that stress is not an issue. Rather, the biggest challenges are integration ones.

Leti has a PDK ready to go for those who want to design a test circuit in their monolithic 3D flow. The company has ELDO, HSPICE, Calibre, StarRC, and other files available, and it has said that monolithic 3D offers savings of at least 55% on area, 23% on performance, and 25% on power over 2D.

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December, Leti signed an agreement to work with Qualcomm. ST and IBM have also been working with Leti in various areas.

Since before 2009, CEA-Leti has been busy working on processing flows to enable monolithic 3D devices. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper "Advances in 3D CMOS Sequential Integration" (subscription required). In that paper, she and her co-authors showed results for a sequentially processed P over N (no metal between transistor layers) test chip. In an IEDM 2011 paper, she and her colleagues showed a 50nm 3D sequential structure on 10nm channel silicon, illustrated below.

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications -- both parallel and monolithic -- with an inauguration event in January 2011. In December 2013, Soitec and CEA renewed their longstanding partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference is scheduled for Oct. 6-9 at the Westin San Francisco Airport. CEA-Leti will present its work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon. With five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories, this would be a great opportunity to learn more about monolithic 3D technology.

-- Brian Cronquist is vice president of technology and IP at MonolithIC 3D Inc. He has 35 years of semiconductor industry experience as senior director of technology development and foundry at the nonvolatile FPGA provider Actel (now Microsemi), starting and building Chartered Semiconductor-Singapore (now GlobalFoundries), running startup wafer fab engineering teams at Sierra Semiconductor (now PMC-Sierra), and developing process technology at AMI and Synertek/Honeywell. He has published more than 100 technical papers in the fields of semiconductor microelectronic radiation effects and hardening, as well as new 3D-IC, logic, antifuse, and flash processes, devices, and reliability. He holds more than 60 issued/pending patents.

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about overcoming silicon defects in monolithic 3d.

As dimensional scaling has reached the diminishing return era there is a buildup of interest in monolithic 3D as an alternative path forward. Both memory and logic vendors are moving to monolithic 3D. The memory vendors are in transition to 3D NAND and Samsung has already announced mass production of their V-NAND. BeSang has been working in monolithic 3D memory for many years and has recently signed a license agreement with SK Hynix. And now, in the logic arena, Qualcomm has voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling.” The reason is economic: … “although we are still scaling down, it’s not cost-economic anymore” (Karim Arabi, DAC 2014).

A key aspect of monolithic 3D is engineering the second layer to be especially thin, on the order of 100nm or less. This provides for tiny (10s of nm diameter) vertical connections which are dense, manufacturable, and stress-free.  They can be manufactured with well understood processing as these vertical connections would look very much like the metal to metal vias that the industry has been making for decades. This avoids the 10+ micron sized TSVs of parallel 3D and their associated reliability hazards, process cost, Keep Out Zones, and ‘newness risk’.

When performance is important, single crystal silicon based transistors are the way to go for stacked layers. So far, it seems that the best technique to form such thin mono-crystal layers with the required thickness control is to use the volume production and well proven ion-cut process. Many of the high performance monolithic 3D process flows utilize ion-cut techniques, sometimes called ‘Smart-Cut’.

However, use of ion-cut creates a small number of crystal defects in the very thin single crystal layer-transferred film. I’ll talk about some techniques that may be employed to solve this but, first, let’s explore why defects are created in the ion-cut process.

The high dosage of ions used in the process creates damage to the silicon lattice at, and near, the ion-stopping depth, such that the lattice becomes brittle there; hence, can be ‘cut’ or ‘exfoliated’ with a force (e.g., knife, water jet) or thermal anneal. After separation of the layer to be transferred from the donor substrate, this ‘donor layer’ will still have some of the silicon lattice damage from the embrittlement on one surface, and may also have some damage from the splitting process itself. Soitec, in the manufacture of SOI wafers, utilizes 1100-1200°C thermal anneals (both oxidizing and non-oxidizing) in combination with chemical-mechanical polishing (CMP) to repair the crystalline damage, as part of its SmartCut (ion-cut) process. However, these damage repair anneals are not compatible with the commonly used low melting point/hi-diffusivity interconnect metals like copper or aluminum of the lower device layer in a 3D stack. BeSang has a nice tutorial video explaining this on their website. Here’s a snapshot:

Further, the passage of the ions used in the ion-cut process creates a lower level of damage to the silicon lattice of the bulk of the to-be-transferred donor layer as the ions pass thru the lattice. This bulk lattice damage can cause junction leakage, and lower the performance of devices. Annealing this type of lattice damage requires temperatures of about 600°C or greater, which – again – is incompatible with the commonly used interconnect metals of the lower device layers in a 3D stack.

Now let’s look at two silicon device proven methods that are available to overcome the ion-cut induced defects and can be applied to the ion-cut layer transfer for monolithic 3D devices and  structures.

Radu et al. of Soitec, in U.S. Patent Application Publication 2013/0026663, describe a method for curing defects associated with ion-cut implantation by a CMP and then a laser anneal of the transferred singe crystal silicon layer.

Singe crystal silicon donor wafer 1 is ion-implanted with a heavy dose of hydrogen or helium ions to create a brittle region 11 as shown in Fig. 1A. Then the donor wafer is flipped over and bonded to the top of a receiver substrate 2 that may have transistors and interconnect metallization 20, shown in Fig. 1B. Layer 3 is a low thermal conductivity or thermal insulating layer that will help thermally protect the transistors and interconnect metallization 20 of substrate 2.

Fracturing along the brittle region 11 may be done with any number of techniques, such as mechanical knife, water or gas jet, etc., leaving behind transferred silicon layer 10. The transferred layer surface 12 may be CMP’d to remove the majority of the roughness and surface defects, resulting in Fig. 1C.

However, there are still bulk lattice damage centers in transferred silicon layer 10. Radu et al. takes care of them thermally by applying pulses of electromagnetic energy. Specifically mentioned are the pulsed lasers of Excico and JPSA.

The wavelength of the irradiation is chosen such that the majority of the pulsed energy is absorbed in transferred layer 10. The low thermal conductivity or thermal insulating layer 3 minimizes the thermal diffusion from the heated transferred layer 10 to the interconnect metallization and must be designed properly to handle the thermal pulse of the layer above. Temperatures high enough to cure the ion-cut induced defects and reactivate any ion-cut deactivated dopants in transferred layer 10 can be achieved. For example, as Figs. 5A and B show, the transferred thin (0.8um in this case) silicon layer (a) may achieve a temperature well above 1000°C from the laser pulse, and the interface (b) between substrate 2 and thermal insulating layer 3 will stay well below 400°C.

Fig. 5A shows the JPSA laser at 193nm and 20ns pulse FWHM (Full-Width Half-Max) and Fig. 5B shows the Excico laser at 308nm and 160ns pulse FWHM.

We have also published work on laser annealing at 2013 IEEE 3DIC and 2013 IEEE S3S Conferences showing how scaling trends can make monolithic 3D practical and the substantial design space of the laser wavelength/energy/pulse width, top layer thickness, and shielding/thermal protection layers which can make single crystal monolithic 3D possible.

Clearly, stacking of ultra-thin layers of defect free single crystal silicon can be readily accomplished and the tools to realize this are available from at least two vendors.

At ESSDERC (43rd Solid State Device Research Conference) in September of 2013, Radu et al. in collaboration with CEA-Leti, presented a different way of obtaining low defect single crystal silicon stacks. Low temperature Solid Phase Epitaxial Re-grow (SPER) is combined with ion-cut to demonstrate defect free diodes with processing temperatures less than 500°C.

SPER utilizes a small amount of crystalline silicon as a template to re-crystallize an amorphous silicon layer at temperatures just above 475°C and can be used to activate dopants above the solubility limit.

SPER can be combined with low temperature ion-cut (SmartCut) and bonding techniques to obtain defect free single crystal devices. Donor wafer doped silicon is amorphized before bonding and ion-cut implanted to create the brittle zone, flipped and bonded to the handle, SPER processed, and then thinned to remove the End Of Range defects.

No crystalline defects were seen utilizing the usual physical means:

However, the tougher test to satisfy is always the electrical one. Radu showed excellent diode characteristics, resistivity, concentration and mobility recovery. Here are some of their diode I(V) curves:

I would not be surprised if demonstration of transistors is published in the near future.

So, hopefully I have given you at taste of how ready an important piece of the monolithic 3D puzzle is to delivering on its promises. Back in December 2013, Soitec and CEA-Leti renewed their long-standing partnership for five additional years. I think it is safe to say that more will be coming soon.

Give me a call or email if you want to talk more…

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about MonolithIC 3D Inc.'s participation at Semicon West 2013.

Thanks to everybody who came by poster exhibition at the Silicon Innovation Forum at SemiconWest 2013 [SemiWest]! We really enjoyed talking with you about all the exciting possibilities for new products and processes that are enabled by monolithic 3D IC.

Here is Zvi 'guarding' the poster:

Atoms Don't Scale: Dennard type scaling is already reached diminishing returns and looks like going to 'hit the wall' near this decade's end. P. Farrar of IBM said it succinctly: Atoms Don't Scale, and Steve Punta of Intel said "hard to imagine good devices smaller than 10 lattices across - reached in 2020":

As well, Bob Cowell of Intel microprocessor fame, who is currently the head of DARPA's MTO (Microelectronic Technology Office)...the folks who are supposed to be looking way ahead...is publicly saying that Moore's Law is at its end and we will have (at least) a decade long gap (2020-2030) in device improvements:

We all know the trends...much higher lithography costs and litho driven defects, interconnect resistance and capacitance slowing performance, the connectivity is driving power budgets awry, and so on. And the result is that the historical cost trends that we have been enjoying are going to soon no longer be there. Will carbon nano-tubes, graphene, nanowires, InGaAs, spintronics,... save us? Not likely, and certainly not by 2020.

What's the Answer?

Monolithic 3D can utilize the existing infrastructure, so the usual 5-10 years of development of evolutionary concepts places this solution as being capable for answering the 2020 call. TSVs (parallel 3D), if the costs can be contained, can only address a very small part of the solution space.

Take a look at the monolithic 3D techniques and potential for more than Moore ever predicted. http://www.monolithic3d.com/3d-ic-edge1.html

As an industry, how are we going to fill the decade gap?

Give me a call or email if you want to talk more...

BC

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses how can heat be removed from 3D-IC Stacks.

Thanks to everybody who came to IEDM this year, and especially to those I met and who came to paper 14.2, delivered by Hai Wei of Stanford University. You can find the meeting paper and slides here.

One of the big challenges facing 3D-IC is how to remove the heat dissipated on the upper layers to keep a high performance chip temperature within the system and reliability constraints and prevent hot spots. Most existing proposed techniques rely on arrays of TSVs and thick (xxum) silicon layer to conduct and spread the heat laterally and vertically. We propose that properly designed PDNs* (Power Delivery Networks) can significantly contribute to heat removal in both parallel (think TSV and xx um thick Si layers) and monolithic/sequential (think 100nm Si layer) 3D-ICs.

We investigated both parallel and monolithic in the paper. Here, I will, of course, focus more on the monolithic challenges and solutions, but I will make some important comparisons to parallel at the end.

Since the 130nm node, we have entered an era in our industry where we are not only using new materials, but also new device structures. I have written previously about the risk associated with this, and (hopefully…) made a case for monolithic 3D technology being the best way for the industry to move forward, still enjoying Moore’s Law type economics (i.e., lower cost) but with a much lower development risk.

Life is getting thin and narrow in our business….so, how best to take advantage of this nanometer and angstrom era and avoid the economic (think EUV at 110+M$ a pop, or double/quad patterning) and atomistic (think 7 nm) brick walls coming? Monolithic 3D stacking technology is the answer: keeping the next evolutionary step of our industry in the wafer fab, where the batch economics of the silicon wafer can be enjoyed, and avoiding the costly piece-part assembly processes of TSVs.

One of the basic tenets of monolithic 3D is the ability to have thin (preferably monocrystalline) silicon layers that enable very small vertical interconnect manufacturing, and hence a large (>1 million/cm2) layer to layer vertical interconnect density in the stack. This opens up the possibility for powerful new architectures and devices, such as Amdahl's wafer scale computer (see blog, website, technology) and cost effective MLC 3D memories.

Two implications arise from the thin (on the order of 100nm or less) silicon layer stacking. First, that fully depleted (FD) devices, and hence silicon islands floating in an insulator such as silicon dioxide, will be the norm. Second, taking full advantage of a manufacturable aspect ratio etching (5:1 to 10:1), we will end up with a large density of very small layer to layer vias (of 1-2 lambda diameter), where vertical interconnect density rivals the horizontal density of interconnect that we have enjoyed thru the many cycles of Dennard scaling.  FD devices are soon to be the norm in 2DICs; for example, the thin UTBBOX of STMicro/GlobalFoundries and the narrow FinFets of Intel/TSMC (incidentally, at IEDM12, Intel was criticized for doping the fins…).

Both of these implications, FD devices in islands of Si and very dense vertical interconnect, play a significant role in how we propose to solve a major challenge in 3D stacking. 

                                                           Since the stacked layers are not in direct contact with the heat sink:
                                                          How do we get the heat out of the stacked layers???


In short, the answer is to take the heat out of each silicon island with the power delivery network, move it laterally in the metal interconnect of that stack layer (just as if we had a thick silicon layer underneath), and then vertically move the heat to the heat sink with that large density of interlayer vias (which we can now make due to the thin stacked layer being very thin).

Here’s a picture of what we are doing:

Sounds at least plausible, right?

Well, that’s what we set out to show, with the heavy lifting done by our friends at Stanford. Hai Wei & Tony Wu of Professor Subhasish Mitra's group, Professor Mitra, and Professor Fabian Pease, were the drivers in creating the simulation approach and engine to see if this works as we thought it might. It did, and then ended up developing a tool that may be very useful for future 3DIC design work.

Hai and Tony describe in the paper and the presentation the details of the simulation approach, engine, assumptions, and methodologies developed. Quite a nice piece of work! They have built an analysis framework that can be adapted for exploring technology-circuit-application interactions for a wide variety of 3D technologies, cooling options, and PDN designs. Types of 3DIC technologies modeled are conventional TSVs, called parallel 3D integration by many in the industry, and monolithic 3D integration, a type of sequential 3D integration. Cooling options range from conventional air cooling of the heat sink (2 W/K·cm2) to external liquid cooling (10 W/K·cm2) for high power systems. PDN designs studied ILV densities from 0 to 4 million/cm2.

That said, what are the essential takeaways?

First, the cooling benefits of PDNs are essential to achieve monolithic 3D integration. Without accounting for PDNs in the 3DIC thermal model, it will be next to impossible to achieve the desirable thermal characteristics and result of a 3D IC stack. Further, the density of ILVs is important to achieving the system thermal constraint. In the 100nm thick Si example below, the desired maximum chip temperature is 85°C or less.

Second, a processor can be effectively cooled, with no hot spots, using PDNs in a monolithic 3D configuration. Hai and Tony’s thermal analyses of core-on-core and memory-on-core designs, utilizing the OpenSPARC T1 industrial multi-core design operating running an 8-threaded program that solves the Black-Scholes application (i.e., hot), showed significant improvement and no hot spots. The top silicon layer is 100nm thick and the hottest parts of the chips were operating at 138 W/cm2. Those hottest parts, the EXU units, were stacked directly on top of each other to show the worst case.

Combining these two seems to indicate that no PDN in the model versus designing and optimizing with thermal-aware PDNs makes the difference between being able to run the design (processor on processor in this example) at only 1/3 of the full power density or at a full power.

That’s the essential take-away for monolithic. Mimic the lateral heat conduction of thick silicon with the PDNs of the thin silicon stack layer, and then get that heat vertically to the heat sink with the dense network of vias provided by the monolithic 3D integration.

For the parallel 3D integration case, the 5um thick silicon greatly helps with the lateral heat conduction to the TSVs. With a properly designed PDN; however, there can be a significant savings in the number of TSVs (ILVs on chart below) used to vertically conduct the heat away, and thus offers a significant area savings by eliminating many of those big TSVs and Keep Out Zones (KOZs). (Note: for both the parallel and monolithic cases, Hai made the KOZ twice the ILV diameter as a conservative choice)

Moreover, by use of a properly designed PDN and an optimized density of TSVs, the maximum power density of the top layer in can be increased considerably …. from 35 to 50 W/cm2 for the parallel 3D case.

It is worth noting an important point from these graphs: At the optimum design point, where the density of ILVs coupled to the PDN satisfies the desired 50W/cm2 max allowed power density, the required number of TSVs to effectively conduct the heat costs about 3% of the chip area. For the monolithic case, the chip area cost is about half that. 

A high density of small vias not only makes possible some powerful product architectures such as logic-cone level redundancy, but is also key to producing area efficient vertical heat conduction networks.

BC

*Patent Pending technology

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses low temperature cleaving.

Thanks to everybody who came by our booth at SemiconWest SemiconWest 2012 this second year! We really enjoyed talking with you about all the exciting possibilities for new products and processes that are enabled by monolithic 3D IC.

For those who could not make it, here is what our booth looked like:

Nice tie again Zvi! You can still visit us at www.monolithic3d.com.

The most common area that you asked us was about low temperature (less than 400°C) bonding and low temperature cleaving processes. The two topics are quite inter-related: One must make the bond stronger than the energy it takes to cleave at the plane you want, rather than cleave at th at fresh bond. In October last year I wrote a blog about the many low temperature bonding techniques and strategies available and their respective bond strengths. Today, I would like to briefly address some of the low temperature cleaving methods available. Generally they involve either a mechanically induced (blade, gas jet, water jet) method, a lower temp thermal (co-implantation, microwave, etc.) cleaving/layer-transfer method, or a combination of both.

Here are a few papers, with some industrial announcements at the end.

One of the earliest methods published is co-implantation by Q.Y. Tong et al. of Duke University at the 1997 IEEE SOI Conference.  Tong could greatly affect the kinetics of the hydrogen blister formation by co-implantation of Boron. They were able to transfer a 0.4um silicon layer onto a quartz substrate with a 150°C exposure to the quartz by pre-annealing the co-implanted silicon for 10 minutes at 250°C.

Tong with colleagues at the Max-Planck-Institute followed up with more co-implantation

kinetics data in a 2008 Applied Physics Letter. They again demonstrated a 200°C silicon cleave.


In 1998 App. Phys. Lett., Agarwal et al. showed that He implanted with the H could lead to a significant decrease in the total implant fluence (and hence cost) necessary to achieve Si layer transfer. The total implantation dose can be three times smaller than that which is necessary using H alone.

Nguyen et al. of Soitech/CEA-Leti, at the 2003 IEEE SOI Conference showed that He co-implantation could be used to control the kinetics, so time, dose and temperature trades could be made.

Ma, et al. showed in Semcond Sci. Technol. 2006 that a co-implanted cleave has a smoother

surface than a hydrogen-only implanted cleave.

In 2000 App. Phys. Lett., Henttinen et.al showed mechanical cleaving, blade or N2 gas, on low temperature bonded silicon wafers (ox-ox bond). Depending on the H dose, Henttinen could

cleave the silicon wafers at 200°C or 300°C. Henttinen et.al followed up later in 2002 in J. Nucl. Instr. and Meth. in Phys with fundamental mechanistic studies and also demonstrated that with enough B doping one can enable H-implanted layer exfoliation below 200°C.

Cho et al., in 2003 App. Phys. Lett. reported that full wafer layer transfer could be achieved with a mechanical cleave (edge initiated crack propagation) after a 250°C annealing that enabled the bonding strength at the acceptor/donor interface to exceed the required cleave energy at the hydrogen implant plane.

En, et al., of Silicon Genesis, described a room temperature H implant using PLAD (Plasma Immersion Ion Implantation), plasma assisted oxide to oxide bonding, and a room temperature mechanical cleave process at the 1998 IEEE SOI Conference.

Current, et al. of Silicon Genesis, showed a wafer separation tool in MRS 2001 where they utilized a pressurized N2 jet to cleave silicon bonded pairs at room temperature.

Recently from the industrial side:

Soitec announced at SemiconWest 2012 the availability of a room temperature smart cut:
"Soitec’s low-temperature Smart Cut process uses oxide-oxide molecular bonding and atomic-level cleaving to transfer mono-crystalline silicon films as thin as 0.1 micron onto partially or fully processed wafers. On this new material layer, a second level of devices can be processed and this integration can be repeated in an iterative mode. Transferring an extremely thin layer enables higher interconnect density, higher signal throughput and simpler TSV processing. Benefits include increased computing bandwidth, lower overall manufacturing cost, and power savings due to the reduced wiring distance between connected devices. This final benefit is well suited for producing advanced memory or CMOS logic 3D IC systems.” See: http://www.soitec.com/en/news/press-releases/article-346/

SiGen (Silicon Genesis) has tools (some shown above) available that will bond and cleave at or near room temperature: http://www.sigen.net/semi_debondCleave.html

References:

TONG, Q.-Y., et al., "Low Temperature Si Layer Splitting", Proceedings 1997 IEEE International SOI Conference, Oct. 1997,  pp. 126-127

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NGUYEN, P., et al., "Systematic study of the splitting kinetic of H/He co-implanted substrate",  SOI Conference, 2003, pp. 132-134

MA, X., et al., "A high-quality SOI structure fabricated by low-temperature technology with B+/H+ co-implantation and plasma bonding", Semiconductor Science and Technology, Vol., 21, 2006, pp. 959-963

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We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses why he believes Monolithic 3D-IC could be less risky than scaling or TSV.

I recently saw this great 5 minute video by Applied Material’s Richard Lewington [AMAT 3D Blog Video] where three types of 3D-IC construction are demonstrated. Note that the first two 3D-IC options he shows (with those plastic blocks) are monolithic. Only the third option is TSV based.

What’s going on here? Why is this major equipment vendor talking about monolithic 3D when it seems that most of what the industry is talking about these days are scaling, interposers, and Thru-Silicon-Vias(TSVs)? Let’s take a look.

Being a fab-guy (built parts of and worked in Chartered Fab-1 & Fab-2, Sierra Semi’s fab inside National Semi’s Bldg#4, AMI Poci Fab-4, Synertek Fab-3, etc.) I am going to approach this from a process/fab-rat perspective. Because this is a key point to what monolithic 3D is about: it is supposed to bring 3D-IC back into the wafer batch economics of semiconductor processing. No piece part handling expense, TSV/interposer reliability & cost issues, or OSAT troubles (I applaud TSMC for trying to remedy this OSAT part, but am surprised that Global Foundries did not do it first….they could have beaten TSMC to the punch here).

The major rule for wafer fabs is Take no Risks….. Everything you do is focused on control: understanding, eliminating, controlling variables. Protect and preserve that huge capital investment so you can pay it down. By definition & nature, fab managers are very conservative. But scaling forced us to do dramatically different and risky things. That’s a major reason why it takes 10+ years for new process/technologies to get into a large production fab. Think about HKMG, Cu BEOL, CMP, strain, plasma metal etching rather than wet (caused lots of corrosion issues/mousebites), to name a few. Even platen cooling (instead of aluminum mask layers) for high current implantation took a long time. Changing from flats on the starting material wafers to the notch took about 10yrs too.

At its root, many of these changes took new machines, new chemistries, and/or new process methods (think APCVD, LPCVD, UHVCVD, PECVD, SACVD, ALCVD, MOCVD, RTCVD, …..) Another large risk factor with scaling has been the use of more elements of the periodic table to solve scaling challenges.  We did not just alter the form or compound of a known element (bad enough risk-wise); we changed to and added new elements to our expensive wafer fabs. (In fab parlance, all this “newness” added up to what is called the Sphincter Effect)

When I started in the industry we used only six elements from the periodic table:

Yet, all of us scientists and engineers, as well as fab managers, solved the problems caused by relentless scaling, and the industry grew…we had a lot of fun, we were supremely challenged, and we solved those challenges. But we also grew grey hair and permanently pinched sphincters.

At what cost? (remember, low cost is crucial to successful manufacturing!)

Here’s what Global Foundries showed about costs:

So, now we have now included the investment and banking communities into our Sphincter Effect.:-))

Enough! This is the road to ruin; well, at least to vastly diminishing returns (think Handel Jones’ chart [ElectroIQ link to ISS12 Day 2] on how transistor cost is no longer going down…)

3D-IC is the solution. OK, so…. monolithic or TSV or interposer? Above I already mentioned a few of the risks and costs to a TSV/interposer solution. Look at all the new processes and machines that had to be developed to etch and fill such deep holes at least somewhat economically. And the integration issues are significant because of the novelty and the architecture & flow: Cu/silicon stresses, keep out zones, liners, new reliability fail modes, etc. As usual, these issues will likely be solved; hence, TSV & interposers will be useful for obtaining some cost and functional/architectural gains from its limited vertical connectivity. But they are not the endgame. To get fully back onto the economic scaling path we need rich vertical connectivity.

What about monolithic 3D-IC risks & costs? Fab equipment and unit processes exist. No new elements from the periodic table are necessary. And the gains resulting from this dense vertical connectivity keep us on a scaling equivalent path (no need to spend space here…lots has been written about this). Let’s instead look at the process details:

Oxides for ox-ox direct bonding: Deposited oxides are well understood and cheap. No new equipment or elements are needed. Lots of manufacturing proven techniques to get there: PECVD, SACVD, etc.

H Implant: Can be done on current models. No new equipment needed. Done by SOI manufacturers for 20 years. H in silicon is well understood.

Bonding: Two well-known equipment vendors (EVG & SUSSMicroTec) with low temp oxide to oxide bonding capability and significant sales of machines (mostly to BSI sensor folks at this time). A recent third new entry (MHI-Mitsubishi Heavy Industries) with room temp ox-ox bonding. I recently blogged on this topic too. [BC  LT direct bonding]

Cleave: Lots of methods proven for SOI manufacture, sensors, and solar. Simplest is thermal … just use a furnace or RTP. We made a short movie clip showing how simple cleave is with the AG RTP at Stanford.

Monolithic 3D-IC uses existing wafer-fab equipment, needs no new elements from the periodic table, and utilizes well-known unit processes and chemistries.

What’s the catch? It’s the integration. Integration work (blood, sweat, and tears) will always be there, even with no new elements, machines, chemistries, etc. Always. However, those who have done new process introductions know that integration is significantly less risky (= costly) and faster to market without than with the elements/machine/chemistry changes. New modes of defect generation are always generated from integration, but there are a lot less of them if all the unit processes are standard accepted practices, than if those unit processes are totally new.

If you look very very carefully at the MonolithIC 3D Inc’s process flows, you notice we were single mindedly focused on making it simple. For example, the nm-scale thru layer vias (TLVs) are always made thru the STI (Shallow Trench Isolation); hence, no dielectric liners, minimum stress, conventional etch and fill, nothing high aspect ratio about it. Make the TLV look and feel like a regular metal to metal via.

This shows in the costs. Deepak Sekar did a SEMATECH based cost estimate and talked about it in a blog.  [Deepak Blog ion-cut cost] Here’s his summary chart for 300mm wafers.

Validation of Monolithic 3D

One may make the argument that validation of a nascent & new game-changing technology is impossible, or at least very nearly so. However, for monolithic 3D-IC there are at least two important data-points to consider. And I hope that you will be convinced that monolithic 3D-IC is neither so nascent nor new.

NAND Memory Makers going 3D: People such as David Lammers of Semiconductor Manufacturing & Design Community [Lammers July 2011] have pointed to validation evidence that the time of monolithic 3D-IC is near: the bleeding edge NAND memory makers are already moving to monolithic 3D-IC.

“The advent of 3D NAND memories may be only two or three years away, speakers said at Semicon West in San Francisco. By 2013 the major memory companies developing 3D NAND, including Hynix, Samsung, and Toshiba, may be ready with pilot lines, moving to volume production a year or so later. Taiwan-based Macronix International also has been developing a 3D NAND solution.”

At the recent (2011) VLSI Symposium J. Choi of Samsung showed their view of how they will keep on making cheaper bits … by going 3D monolithically.

Deepak Sekar has also talked in detail about this 3D monolithic push by the NAND industry (Sekar hails from flash maker SanDisk) in his recent blog [12/11/2011: where-is-the-nand-flash-industry-heading].

Second, the global semiconductor equipment leader, AMAT, has talked about sales into that market [SemiconWest2011-new products including 3D architecture support]

[OptivaCVD  for BSI] and even has a video (Richard Lewington’s blog video noted above) to promote it.

When both manufacturers and equipment suppliers are talking about, committing to, and executing on a specific technology change, you know that the economics are attractive and not just niche. Think back to how HKMG and copper BEOL came to production.

The chicken and egg are out the window….it’s happening now. The risks are contained. Others are going for it.

Whether polysilicon or monocrystalline silicon based monolithic 3D, jump in and be a part of this next important evolution of our great industry.

Don’t miss out.