A key aspect of monolithic 3D is engineering the second layer to be especially thin, on the order of 100nm or less. This provides for tiny (10s of nm diameter) vertical connections which are dense, manufacturable, and stress-free. They can be manufactured with well understood processing as these vertical connections would look very much like the metal to metal vias that the industry has been making for decades. This avoids the 10+ micron sized TSVs of parallel 3D and their associated reliability hazards, process cost, Keep Out Zones, and ‘newness risk’.
When performance is important, single crystal silicon based transistors are the way to go for stacked layers. So far, it seems that the best technique to form such thin mono-crystal layers with the required thickness control is to use the volume production and well proven ion-cut process. Many of the high performance monolithic 3D process flows utilize ion-cut techniques, sometimes called ‘Smart-Cut’.
However, use of ion-cut creates a small number of crystal defects in the very thin single crystal layer-transferred film. I’ll talk about some techniques that may be employed to solve this but, first, let’s explore why defects are created in the ion-cut process.
The high dosage of ions used in the process creates damage to the silicon lattice at, and near, the ion-stopping depth, such that the lattice becomes brittle there; hence, can be ‘cut’ or ‘exfoliated’ with a force (e.g., knife, water jet) or thermal anneal. After separation of the layer to be transferred from the donor substrate, this ‘donor layer’ will still have some of the silicon lattice damage from the embrittlement on one surface, and may also have some damage from the splitting process itself. Soitec, in the manufacture of SOI wafers, utilizes 1100-1200°C thermal anneals (both oxidizing and non-oxidizing) in combination with chemical-mechanical polishing (CMP) to repair the crystalline damage, as part of its SmartCut (ion-cut) process. However, these damage repair anneals are not compatible with the commonly used low melting point/hi-diffusivity interconnect metals like copper or aluminum of the lower device layer in a 3D stack. BeSang has a nice tutorial video explaining this on their website. Here’s a snapshot:
Now let’s look at two silicon device proven methods that are available to overcome the ion-cut induced defects and can be applied to the ion-cut layer transfer for monolithic 3D devices and structures.
Radu et al. of Soitec, in U.S. Patent Application Publication 2013/0026663, describe a method for curing defects associated with ion-cut implantation by a CMP and then a laser anneal of the transferred singe crystal silicon layer.
Singe crystal silicon donor wafer 1 is ion-implanted with a heavy dose of hydrogen or helium ions to create a brittle region 11 as shown in Fig. 1A. Then the donor wafer is flipped over and bonded to the top of a receiver substrate 2 that may have transistors and interconnect metallization 20, shown in Fig. 1B. Layer 3 is a low thermal conductivity or thermal insulating layer that will help thermally protect the transistors and interconnect metallization 20 of substrate 2.
We have also published work on laser annealing at 2013 IEEE 3DIC and 2013 IEEE S3S Conferences showing how scaling trends can make monolithic 3D practical and the substantial design space of the laser wavelength/energy/pulse width, top layer thickness, and shielding/thermal protection layers which can make single crystal monolithic 3D possible.
Clearly, stacking of ultra-thin layers of defect free single crystal silicon can be readily accomplished and the tools to realize this are available from at least two vendors.
At ESSDERC (43rd Solid State Device Research Conference) in September of 2013, Radu et al. in collaboration with CEA-Leti, presented a different way of obtaining low defect single crystal silicon stacks. Low temperature Solid Phase Epitaxial Re-grow (SPER) is combined with ion-cut to demonstrate defect free diodes with processing temperatures less than 500°C.
SPER utilizes a small amount of crystalline silicon as a template to re-crystallize an amorphous silicon layer at temperatures just above 475°C and can be used to activate dopants above the solubility limit.
So, hopefully I have given you at taste of how ready an important piece of the monolithic 3D puzzle is to delivering on its promises. Back in December 2013, Soitec and CEA-Leti renewed their long-standing partnership for five additional years. I think it is safe to say that more will be coming soon.
Give me a call or email if you want to talk more…