The Boiling Frog Syndrome and the Semiconductors Industry

We have a guest contribution today from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. In this post, Zvi shares his perspective on where the industry is going.

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For almost 50 years we been scaling at about 0.7x every two years. For the majority of this time, it was extremely rewarding and relatively easy.

The first step of "heating the water" came as we moved to 0.65 micron node. After many years of stable mask cost at ~$1,500 per mask it moved up, almost doubling to ~$2,500. And making it even more painful, we moved from just two metal layers to multiple metal layers, increasing the over all mask set cost soon after. This was discussed in more details in a previous blog-post here.

The table below presents the mask cost trend since then.

And following the trend of escalating mask set cost so did the design cost, as presented in the following chart (IBS)

Being part of the ASIC industry, I remember most of us chose to ignore the alarming trend. But a few years later, starting at the 0.25 micron node, we can see the evaporation of the ASIC market. To the point that from tens of ASIC vendors then, we dropped down to none.

So we kept on "heating the water" and the interconnect issue popped up. We first introduced repeaters and larger drive, than moved to copper and recently to low-k. So we were able (at great cost) to push the issue for more than a decade but as we can see from the chart below - it is not going away.

And in fact, it is starting to escalate and get pretty painful, as you can see from the charts below:

And talking about water is so appropriate as we are using water extended lithography for few years (at some modest increase of stepper cost). But now it seems the water is really getting hot, as we can from the following chart that shows the escalating cost of lithography:

The increased cost of lithography is starting to dominate the cost of fabs. The following chart presents the escalating trend of fab costs:

The escalating cost of fabs, increased mask costs and the implication of escalating cost of lithography without the compensation of a corresponding increase in throughput, reflects badly on the cost of transistors for many SoCs, as is presented in the following chart from IBS:

Not surprisingly, a trend we saw in the past in the number of ASIC vendors can now be seen in the number of semiconductor logic vendors, as presented in the following chart from iSuppli:

It does look like the "water is boiling" or at least is almost boiling.

Yet we don't need to get boiled - we are not frogs, so let's not behave like them.

Lets slow down the heating and adopt a complementing path to maintain the integration trend (Moore's Law)
- the monolithic 3D IC.