We have a guest contribution today from Ze'ev Wurman, MonolithIC 3D Inc.'s Chief Software Architect. Ze'ev discusses about where is the semiconductor industry heading to.

The semiconductor industry is in the doldrums. The PC market shrinks, Intel shares sink, Applied Materials cuts staff, and even Apple suddenly experiences its share price drop by $100 in a month. Are things really so bad?

But other news seems different. TSMC shares are close to their historical high; Global Foundries leapfrogs TSMC technology and nips at Intel’s heels with 14nm; Samsung reports record quarterly profit. Things seem to be going swimmingly.

Semiconductor business has had its ups and downs since its inception. As demand followed, more and more capacity was put on line, which caused the next overcapacity and slump, inevitably followed by the next spike in demand as the technology inexorably marched down the scaling curve. So, perhaps, nothing is really new here after all.

Yet, perhaps, we should not be so sanguine anymore. We did cope with 193nm light to define our chips down to 20 nm, but at an ever-increasing cost of expensive phase shift masks, immersion lithography, and double exposure. EUV has been talked about for at least 15 years (following another 15 years of x-ray lithography development fiasco) and has been “late” since at least 2005. Despite the impressive progress shown by ASML, the industry greats – Intel, Samsung, and TSMC --banding around EUV is possibly more a sign of desperation than a strong vote of confidence. The drastic reduction in foundry players – from 20 or so in 90nm to four or less for 14nm has been noticed by many and cannot be good for the long-term health and vitality of the industry. 

ASML is the last remaining game in town and, even if it works, building a foundry at over $10B a pop, and developing a technology node at well north of $1B, does wonders at keeping everyone but the most committed (and with deep pockets) out of the game. And the unanswered question is still in place: at what price point will the industry effectively become the domain of the few mass-produced designs such as Apple’s or Samsung’s phones and nothing else? 

Clearly pressures have been building up and the industry can’t pretend everything is as usual for much longer.  3D devices has been talked about for decades, yet implementing this dream was considered infeasible until recently. 3D designs are, in a sense, the holy grail of the industry:

• They allow for shrinkage of the average source to destination distances, shrinking power dissipation and improving performance;
  

• They can include inexpensive built-in fault detection and repair as described here, allowing for as large as needed yielded dies, which cuts further on power by saving on off-chip I/O power;
• They allow cheap and high performance integration of dies with disparate technologies, so advanced (and expensive)  logic can be stacked with reduced-cost technology for memory dies, or specialized analog and RF functions;
• They allow the reuse of older fab lines as much of density improvement is achieved through stacking dies rather than shrinking features;
  

• They allow efficient heat removal without exotic cooling technologies through use of power delivery networks, to be presented in the upcoming IEDM, paper 14.2 ;
  

In recent years TSVs started to show up. Yet, while TSVs are good for designs that need limited vertical connectivity between disparate sub-systems such as processors with memory, they do not really open the door to a true monolithic 3D design.  What true monolithic devices offer is a much higher vertical connectivity, by a factor of up to 10,000, and enable the stacking of multiple dies.

The impact of the increased monolithic vertical integration at lower cost can be dramatic on every electronic market segment.

For mobile devices, the inexpensive integration of analog, RF, and sensors, can lower their cost and power consumption for an even broader market penetration and longer battery life.

In medicine, the footprint of devices is often critical. The availability of camera-in-a-pill, or of implantable medical devices that control drug release, improve hearing, monitor vital signs, or allow artificial vision, are all strongly dependent on heterogeneous device integration in a small footprint and with reduced power. Monolithic 3D is key to transforming the planar and bulky designs of today’s 2D to grain-of-corn and grain-of-rice shape factors that can be inserted for very long time periods into our bodies.

Fostering innovation and reducing barriers to entry of new products are considered crucial for future economic prosperity. FPGAs have been trying to fill this niche since the demise of ASICs, yet they suffer from many handicaps: they are physically large, they are power hungry, and they are available in a limited number of configurations that are often suboptimal for the application. Monolithic 3D technology allows the inexpensive creation of a nearly infinite number of FPGA configurations that can be tailored to every application, as described here. And it does so while dramatically reducing both the device footprint and power.

Large-scale computing is facing enormous challenges to reduce its power consumption. Server farms of the likes of Google, Amazon, or Facebook consume tens and hundreds of megawatts of energy, while the government struggles mightily to keep its planned Exascale supercomputer under 20MW. Three-dimensional chips can play a large role in reducing power consumption by reducing the interconnect length (and hence, its capacitance), which is responsible for most of the power dissipation in modern chips. Ultra large scale integration with high yields, enabled through 3D repair structures, will further slash the power that today resides in the off-chip drivers.

In memory design, the transition to 3D technology is already taking place as described in our previous blog. Monolithic 3D structures using crystalline silicon may further the penetration and efficacy of this technology in both non-volatile memory as well as in DRAM.

The semiconductor world will inevitably move to monolithic three-dimensional technologies. The change drivers are already here: the skyrocketing cost of scaled-down lithography, the need to reduce power dissipation, and the need for heterogeneous integration. The only question is how quickly it will move there, and who will be the winners.

We have a guest contribution today from Ze'ev Wurman, MonolithIC 3D Inc.'s Chief Software Architect. Ze'ev discusses the upcoming IITC and the contribution of 3D technology to minimizing wire-length distribution.

Does Size Matter?

The next International Interconnect Technology Conference (IITC 2012) will be held in San Jose in a couple of weeks (June 4-6). This is a good opportunity to recall that, in some sense, the reason for scaling silicon down has changed in recent years from packing more transistors in a square (or cubic) millimeter to increasing functionality and performance at reduced power. An ever higher fraction of the power dissipation resides in the interconnect – both in the net switching itself as well as in the ever-increasing number of repeaters required to re-power more and more “long” nets.

Estimates of the area dedicated to repeaters as technology shrinks vary but even if the early predictions of 70% cells being dedicated to repeaters at 32 nm may have not come to pass (Saxena, TCAD 2004), a large fraction of chip power is now dissipated by interconnect structures. This is particularly true in FPGAs where the interconnect share of routing-related dynamic power may easily reach 2/3 of the power, but even non-programmable devices have been reported to have half of their power dissipated in the wires already at 90nm. The following slide is from the 2006 High Performance Embedded Computing workshop.

Last year IITC included a paper from Georgia Tech (Dae Hyun Kim, et al., Impact of Through-Silicon-Via Scaling on the Wirelength Distribution of Current and Future 3D ICs) that explores the impact of 3D on the average wire-length of deep submicron ICs. This paper differs from many others in that it explores the impact as a function of TSV size, and it models TSVs from the currently feasible 5 micron, with a 5:1 aspect ratio for the corresponding 25 micron thick silicon layer, down to a futuristic 100 nm, with a 50:1 aspect ratio for a 5 micron thick layer. Such futuristic TSV actually gets close to a monolithic process, which can achieve silicon thickness of one micron and below. Here is a key chart from this paper:

As we can see, a small-sized TSV can significantly reduce the average wire-length by up to 50%, and reflects an improvement equivalent to two or three technology generations. In other words, a 4-way stacked 32nm chip with monolithic-style vertical connectivity can have wire-length distribution as good as a 16nm cutting edge technology, with the associated reduction in power and increase in performance, but using a relatively inexpensive and depreciated fab line.

Yet there is a fly in this ointment – TSVs with aspect ratio of 50:1 are not likely to happen, and using nanometer-TSV with extremely thin silicon layers to maintain AR below 10 creates problems of its own. Just recently IMEC reported stress issues at 25 micron thickness and “found that increase in the die thickness from 25 to 50 um resulted in a stress reduction of 3X. Final conclusions were that 50 um thickness die were currently much better option for scalable manufacturable process.” In other words, the road to nanometer-scale vertical connections does not go through scaling down TSVs but through monolithic process and layer transfer.

I find all this a nice illustration of the importance of the monolithic stacking approach that is also easily visible using our free simulator, IntSim.

Transformation to 3D monolithic stacking is much more than simply saving on a footprint by slicing and stacking the same design. The rich vertical connectivity offered by monolithic stacking significantly reduces the average distance between source and destination and therefore improves performance, saves power, saves total area, and allows players to continue using older process fabs to achieve cutting edge results at a cheaper cost. The chart below illustrates such savings at 22nm technology:

The future of Moore’s Law and the continued well-being of our industry is in the small nanometer-sized TSV, not in the big micron-sized TSVs used today that are so hard to manage. And let’s hope that the upcoming IITC will be at least as interesting as last year’s.

We have a guest contribution today from Ze'ev Wurman, the Chief Software Architect of MonolithIC 3D Inc. In this blog-post, Ze'ev discusses some industry implications of recent events relating to science education. Ze'ev has participated in developing California’s education standards and assessments in mathematics since the mid-1990s. Between 2007 and 2009, he served as a senior policy adviser at the U.S. Department of Education. Throughout their development Wurman analyzed the Common Core mathematics standards drafts for the Pioneer Institute. In the summer of 2010 he served on the California Academic Content Standards Commission that reviewed the adoption of Common Core for California. Wurman earned his BSEE and MSEE degrees from the Technion in Israel, and he is a recipient of the Eliyahu Golomb Israel Security Award.