We have a blog post today from Ze'ev Wurman, the Chief Software Architect of MonolithIC 3D Inc. Ze'ev spent many years leading EDA/software work at Dynachip, eASIC and Amdahl. He will discuss CAD tools for 3D-ICs.
With so many people talking about 3D chips, it’s time to focus on the CAD tool support for them. I find it easiest to look over the CAD landscape using two distinct views.
A functional view tells us what tools are available (or needed) to assist in 3D-specific design functions. For example, many people are worried about power dissipation in 3D ICs and a lot of work has been done on floor planning that avoids placement of hot spots on top of each other, or on insertion of thermal TSVs to remove power from strata that have thermally insulating layers – such as silicon oxide – between them and the heat sink. A 3D partitioning tool is important if you plan on distributing your logic across multiple strata, while if all you plan is to place logic on one stratum and memory on another, you can probably live without one. A good collection of work on 3D CAD can be found at UCLA (here and here), NCSU (here and here), Penn State (here) and Georgia Tech (here, here, and here). Another valuable resource is CiteSeer that will point you to many papers available directly from the authors.
The other view I find useful is the granular one. Much of the industry right now is struggling with designing the 3D strata almost in isolation, and then placing them on top of each other with large TSVs, on the order of 10 microns diameter, connecting between those strata. Designing such large granularity strata is not really that different from designing 2D chips which we all know, and most of the 3D work is done either early in the architecting stage – how many strata, what large objects go on each one, etc. – or in the late stages when final system simulations are run. Yet this picture will change dramatically when monolithic 3D, with inter-stratum vias compatible with device lithography dimensions, will become feasible. This will bring us into the fine granularity 3D IC era where many 2D tools, even with enhancements, will not do and new true 3D CAD tools will be needed. Designing with true 3D cells that span multiple strata such as described here and here will be very different from today and will need new algorithms that will understand 3D in a more intimate manner.
But, perhaps, the most intriguing CAD aspects for fine grained monolithic 3D ICs have not been mentioned yet at all. After all, opening the door to multi-level three dimensional stacks with billions – rather than thousands – connections between them, will certainly lead not only to folding existing designs vertically, but also to discovering new and exciting ways to take advantage of this new dimension of freedom. I am looking forward to it.
A functional view tells us what tools are available (or needed) to assist in 3D-specific design functions. For example, many people are worried about power dissipation in 3D ICs and a lot of work has been done on floor planning that avoids placement of hot spots on top of each other, or on insertion of thermal TSVs to remove power from strata that have thermally insulating layers – such as silicon oxide – between them and the heat sink. A 3D partitioning tool is important if you plan on distributing your logic across multiple strata, while if all you plan is to place logic on one stratum and memory on another, you can probably live without one. A good collection of work on 3D CAD can be found at UCLA (here and here), NCSU (here and here), Penn State (here) and Georgia Tech (here, here, and here). Another valuable resource is CiteSeer that will point you to many papers available directly from the authors.
The other view I find useful is the granular one. Much of the industry right now is struggling with designing the 3D strata almost in isolation, and then placing them on top of each other with large TSVs, on the order of 10 microns diameter, connecting between those strata. Designing such large granularity strata is not really that different from designing 2D chips which we all know, and most of the 3D work is done either early in the architecting stage – how many strata, what large objects go on each one, etc. – or in the late stages when final system simulations are run. Yet this picture will change dramatically when monolithic 3D, with inter-stratum vias compatible with device lithography dimensions, will become feasible. This will bring us into the fine granularity 3D IC era where many 2D tools, even with enhancements, will not do and new true 3D CAD tools will be needed. Designing with true 3D cells that span multiple strata such as described here and here will be very different from today and will need new algorithms that will understand 3D in a more intimate manner.
But, perhaps, the most intriguing CAD aspects for fine grained monolithic 3D ICs have not been mentioned yet at all. After all, opening the door to multi-level three dimensional stacks with billions – rather than thousands – connections between them, will certainly lead not only to folding existing designs vertically, but also to discovering new and exciting ways to take advantage of this new dimension of freedom. I am looking forward to it.
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