We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the emergence of monolithic 3D technology in the near future.

The coming 2014 IEEE S3S conference (October 6-9) is first one to focus on the emergence of monolithic 3D technology. It is fitting that it would be the forum at which a key decisive breakthrough for monolithic 3D IC ("M3DI") technology will be presented. This game changing breakthrough is the first ever monolithic 3D flow that allows a fab to build a monolithic 3D integrated device while using the fab’s existing transistor process flow, without the need to develop and qualify new transistors and a new transistor formation flow.

Recent blogs such as Established Nodes Getting New Attention and Moore's Lag Shifts Paradigm of Semi Industry have articulated the building up of interest in SOI, Sub-threshold and 3D IC technologies. The IEEE S3S is the conference to learn and get updated on these technologies and M3DI is that newest part integrated into the conference. The 3D part of S3S 2014 will have a full day of tutorial presentations by leading researchers in the space, a full session of invited papers, and will conclude with a session dedicated to discussing the most recent breakthroughs in the field.

The M3DI short course will cover alternative process flows that enable M3DI, discuss the challenges and solutions to removal of the operating heat of monolithic 3D stacks, and describe the range of powerful advantages provided by M3DI. Subsequently, Prof. Sung Kyu Lim of Georgia Tech will cover EDA for M3DI. This will be followed by broad coverage of M3DI for memory applications by two leading experts in the field, Akihiro Nitayama of Toshiba/Tokohu University and Deepak Sekar of Rambus. M3DI provides unparalleled heterogeneous integration options which will be covered by Prof. Eugene Fitzgerald of MIT and SMART Lee Institute of Singapore describing the integration of silicon with other crystals for electro-optic device integration. The short course will conclude with Prof. Philip Wong of Stanford, who leads research efforts to integrate silicon with carbon nanotube and advanced 2D transistors layered with memory such as STT-MRAM and RRAM.

In the special invited 3D Hot Topics session we expect to get a full spectrum of the latest progress in the field. Particularly worth noting is the recent progress on the work done by CEA Leti with involvement of ST Micro, IBM and supported by Qualcomm. This work shows both a practical path to monolithic 3D IC and cost analysis of the monolithic 3D advantages. The following chart illustrates the reasons for the high interest in the technology.

And then there is a great dessert to this 3D feast. On Thursday afternoon, in the 3D New Developments session, a game changing breakthrough technology will be presented. Leveraging the breakthrough progress in wafer bonding technology, presenting for the first time ever a monolithic 3D flow using existing fab transistor process. Any fab could utilize this breakthrough to provide far better products at minimum capital and R&D investment. This game changing flow removes the historical differentiation between sequential and parallel 3D, and should significantly reduce the time for monolithic 3D adoption throughout the semiconductor industry.

For a postprandial enjoyment, CEA Leti will present in the Late News session a fully constructed M3DI SOI device, and IBM will present its Multi Stacked Memory Wafer technology.

More information is available on the conference site: S3S Conference 2014

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the paradigm shift in the semiconductor industry. 

In our blog 28nm – The Last Node of Moore's Law, we had pointed out that the change has happened, and it is no longer a matter of forecast or prediction. In this blog we will start by reviewing some of what has transpired since that blog, and then focus on the ensuing paradigm shift in the semiconductor industry.

The following chart was presented in the IEEE IITC workshop by Globalfoundries. It illustrates the cost impact of the double patterning required for scaling below 28/22 nm. 

Soon after Rick Merritt’s coverage of Semicon West - 13 Things I Heard at Semicon West -- Rick wrote: "Moore's Law has definitely slowed" quoting Gartner semiconductor analyst Bob Johnson."No matter what Intel says, Moore's Law is slowing down" and, Bob added, "Only a few high-volume, high-performance apps can justify 20 nm and beyond."

Soon thereafter Peter Singer, in a blog post about the ConFab 2014 –  Can we take cost out of technology scaling? -- quotes Dr. Gary Patton, VP of semiconductor research and development center at IBM: “The challenge we’re facing now is two fold. Number one, we’re struggling to get that 0.7X linear scaling. It might be about 0.8X. And we’re adding a lot more complexity, especially when you adding double and triple patterning."

And now, in early August we finaly got more information from Intel about their up coming 14nm. In our blog Intel vs. Intel we articulate that Intel’s numbers indicate that Moore’s Law had stopped at 28/22 nm both in terms of the bring-up time it takes and the cost of new technology nodes.

It is hard to accept that a trend that has held strong for 50 years, and which kept going many years after multiple predictions of its imminent demise, has really stopped. And it is even harder as we watch the huge effort of bringing up the 14 nm and 10 nm nodes. Yet it seems that everybody should agree that the semiconductor industry is now going through a paradigm shift and for most designs 28nm is, at least for some time, the last node of Moore's Law.

The following charts are well known and present the reason for that change.

It shows that the design cost increases by more than $100M from 32nm to 16nm. If we assume a die cost of $10 at 32 nm and we assume that the traditional cost reduction per node still holds, then we would need a volume of more than 20 million units just to break even. If one also considers the risk associated which such a design, it would actually require more than 100 million units, or at least $1B of market, for such device to justify the investment. Clearly, very few designs have the market for 100 million units or $1B market.
The following chart by IBS presents the past trend in design starts per node. Clearly, most new designs are still done in 130 nm while the node with the fastest ramp-up is 65 nm.

The forcast for 2016 at Semiconductor Technology Nodes – History, Trends and Forecast is illustrated in the following pie chart:

Yet again it indicates a very slow shift to more advanced nodes, and the expectationis that even in 2016 most new designs will still be done in 130nm.

This is clearly a paradigm shift in the industry, and the industry is responding accordingly.

Just prior to 2014 Semicon West, we have seen the conclusions of the SEMI’s World Fab Forecast -- Technology Node Transitions Slowing Below 32 nm. The Forecast uses a bottom-up methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. The chart below illustrates this new paradigm.

The report states: “The cost per wafer has become an increasing concern below the 32nm node.   The expected cost reduction benefit of production at smaller nodes is diminishing and is not keeping pace with the scaling benefits in many cases.  This has widespread and fundamental implications for an industry long following the cadences of Moore’s Law… These may be contributing factors as to why some volume fabs are exhibiting a lag in beginning production of a new technology node.  Now evident quantitatively for the first time, there is evidence of a clear slowdown in volume production scaling of leading technology node transitions.” (emphasis added)

This was followed by another EE Times article – Silicon Highway Narrows, Twists: “Most foundries have yet to start buying the capital equipment needed for the 14/16 nm node, which for many will be the first to support FinFETs, says Trafas of KLA-Tencor. Gear companies hope the orders start coming in the fall…Indeed, he says, one of the big questions many capital equipment execs will bring to this year's Semicon West event on July 7 is, "When will the 16/14 nm investments begin?"

In the same vein, Ed Sperling continued in Established Nodes Getting New Attention: "Work is under way to improve energy efficiency and boost performance without relying on multi-patterning or finFETs. As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors."

And a week later Samuel Wang, an analyst with Gartner, in Who’s Winning The FinFET Foundry Race? wrote: “Short-term, during the first two years of finFET production, there is no need for more than 50,000 wafers a month capacity from all foundries to satisfy the market demand for finFETs, …In the long run and before 2018, there is no need to have more than 250K wafers a month capacity to support the market demand for finFETs."    The EDA industry also is recognizing this paradigm shift. Dr. Aart de Geus in his keynote to the 2014 Synopsys User Group titled Designing Change Into Semiconductor Techonomics, recognized this shift with a series of slides articulating how EDA tools that were developed to support the new technology nodes could also benefit design efforts of old nodes:  

The IP industry is recognizing this paradigm shift as well, visible in IP Reaches Back To Established Nodes: "As SoC developers shift backward to established nodes, steps can be taken to improve the IP’s functionality. Driven by the IoT and wearable market opportunity, SoC developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality."

There also a clear effort to add value and innovation to older nodes by incorporating technology such as SOI and low Vt, known as sub-threshold designs. Most notable was the recent Samsung announcement of licensing FD-SOI from ST Micro for the established node of 28 nm. Some quotes from the articles above illustrate this trend:

* Krishna Balachandran, product marketing director for low power at Cadence. “Threshold voltage manipulation like forward biasing has been selectively used to speed up critical portions of the IP at the expense of increased leakage that is restricted to those sections of the IP without significant overall impact.”

* ARM Fellow Rob Aitken said energy savings are significant using the same exact processors differently. Moreover, it’s most effective at established process geometries where there are no finFETs. But it isn’t a simple process. (For a deeper understanding of this subject, click here). “We can get 4X to 6X improvements in energy,” said Aitken. “That doesn’t come for free, because we have to make some design changes to allow the design to operate down at this low energy point. But if we do this wrong, the overhead we have to add to get these savings is more than you get in terms of a benefit.”

* Mary Ann White, director of product marketing for the galaxy design platform at Synopsys: "Body biasing is another technique that is being recycled. It entered the picture at 90nm, when design teams found they could reduce leakage by as much as 30%. Even at 45/40nm, savings were in the 20% to 25% range. But at 28nm, the benefit for bulk CMOS dropped to as low as 2%,...When you use biasing, you are using extra tracks and extra resources, which may include one or two extra rails,” said White. “But the benefit was falling off at 28nm using planar CMOS. Interest is picking up again with FD-SOI. What’s interesting about this is we used to insert biasing at the back end, where you require a bulk n-well or p-well pin. But recently we’ve had a request to add that capability into UPF. We rolled that out with skepticism on our part, but we’ve been getting a lot of interest. If you’re adding 5% area for better power, it’s worth it.” (See related discussion.)

This paradigm shift could be a real blessing to the industry. The escalating costs drove out VCs from investing in semiconductor start-ups, drastically narrowed the number of vendors and the number of advanced new designs. It left little room for innovation or anything other than rushing to the next technology node. Now it seems that a whole new industry dynamic is taking place, innovation is being embraced, new markets are being explored, and hopefully we will see the return of VCs with the increase of semiconductor vendors and technologies.

This is also the time to pay increased attention to semiconductor technologies that could offer better intrinsic devices without traditional dimensional scaling. Most notable among those would be, SOI, Monolithic 3D, and Sub-threshold design. The 2014 S3S Conference scheduled for October 6-9, 2014, at the Westin San Francisco Airport would be a great opportunity to learn more about those technologies as it provides the latest research results along with workshops, tutorials and range of invited papers. The conference advance program is now available at < http://s3sconference.org/program/ >. It looks now to be the one conference that active members of the semiconductor industry should not miss. 

Along with many in the industry, we were pleased to see the release of Intel's 14 nm technical information on Aug. 11 - Intel Outlines 14nm, Broadwell. It does look like after an extended delay the 14 nm is coming and with it some clarity about the Intel 14 nm technology. Clearly this recent 14 nm information release is being presented by Intel to continue the historical trend of cost reduction and dimensional scaling. Undoubtedly, Intel’s 14 nm technology is a significant technological achievement and deserves full respect and appreciation. Yet, if one takes a closer look at this information, and especially with respect to prior information provided by Intel, there is room for some clarification.  

The above EE Times article provides the following numbers released by Intel on August 11:
"Compared to Intel's 22nm process, it will have:

• 42nm fin pitch, down .70x
• 70nm gate pitch, down .78x
• 52nm interconnect pitch down .65x
• 42nm high fins, up from 34nm
• a 0.0588 micron2 SRAM cell, down .54x

~0.53 area scaling compared to 22nm"
Let’s review the SRAM cell size of 0.0588µm². Yes, it is the smallest published size for a SRAM bitcell we have seen so far. Yet in our blog Intel vs. TSMC: An Update we wrote:  "Accordingly, the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² =0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm, it should be about 0.03 sq. micron or even smaller."

From Intel’s 2012 information release:

In the following table we calculated the expected bitcell size for 14nm according to simple dimensional scaling rules based on each of the bitcell sizes for each of the technology nodes in the above 2012 chart:

The above table indicates that SRAM bitcell scaling has been a challenge for some time but at 14 nm it broke totally away!

The recent Intel presentation argues for the continuation of historical scaling cost reduction to the 14 nm node as illustrated in the following Intel slide:

The graph in the middle shows the exponential increase in wafer cost with scaling; however, the argument made is that the more than 2X increase in transistor density compensates for the increase in wafer cost, resulting with the rightmost chart showing a consistent reduction in cost per transistor.

But the following Intel chart does not show a better than 2X density increase from 22nm to 14nm:

Actually the basic transistor gate pitch indicates only a x1.64 increase in transistor density.

As well, this is before accounting for the increase in RC associated with the narrower metal lines. This would require insertion of many more buffers and repeaters, further reducing the effective density increase.

Furthermore, back to the SRAM bitcell. The announced size for the Intel 14nm bitcell as presented above is not going to help offset the increase in wafer cost.

So it seems this would be a subject matter for more comments and blogs. However, I see no reasons to change my prior statements published in the EE Time blog titled: 28nm – The Last Node of Moore's Law.

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about monolithic 3d technology for future scaling.

At the CEA-Leti Day July 8 during Semicon West, Hughes Metras, Leti's vice president of strategic partnerships for North America, introduced the lead talk about monolithic 3D technology as the "solution for scaling." The Leti device technology roadmap that Hughes presented showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to past 5 nm.Olivier Faynot, Leti's device department director and a well-known device scientist (with more than 170 papers/publications), entitled his talk "M3D, a disruptive approach for further scaling" and started with why the industry needs such a solution.

The majority of people in the industry agree that scaling past the 22nm node, though still quite technically feasible, has priced itself out of most markets. Faynot discussed the "what" (transistor costs are no longer decreasing) and the "why" (litho cost escalation and connectivity inefficiencies of energy and delay). Then he said, "If we just keep the current [2Xnm] technology, we can go farther in cost scaling."

Tech Design Forum's summary of a Qualcomm executive's DAC 2014 keynote offers more information on this crucial topic. So do a pair of EE Times blogs by Zvi Or-Bach.

The solution is to build the stack sequentially in a monolithic fashion. (See Monolithic 3D IC Technologies.) Faynot described a process flow wherein the lower level (first layer) of transistors and its interconnect are made conventionally, some interlevel metal is crafted to help the vertical interconnection, and a second layer of monocrystalline silicon is layer transferred and oxide-oxide bonded at low temperature to the top of the interlevel metal dielectric. This is a blanket layer, so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin, so that direct alignment to the lower-level alignment marks can be made with conventional equipment, and conventional alignment tolerances (single-digit nanometers) can be achieved.

Upper-level transistors are formed utilizing solid-phase epitaxial regrow (SPER) for junction doping at 475-600°C and lower-temperature processing (less than 400°C) for things like gate stacks. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. (Note that the lower-level transistor salicides are stabilized with platinum and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.)

In the Q&A session, Faynot was asked what the observed performance differences were between the upper-level and lower-level transistors. "Currently, we are achieving 95%" of the lower for the upper, he said. "We believe we can make 100%."

He also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. The laser option of solving the thermal challenge of monolithic 3D is the "crème brûlée" of methods, and Leti is "seeing good results." Hopefully, we will see published data soon. My recent Solid State Technology blog offers more information on SPER and laser processing.

Faynot was also asked if stress is a big issue. He replied that stress is not an issue. Rather, the biggest challenges are integration ones.

Leti has a PDK ready to go for those who want to design a test circuit in their monolithic 3D flow. The company has ELDO, HSPICE, Calibre, StarRC, and other files available, and it has said that monolithic 3D offers savings of at least 55% on area, 23% on performance, and 25% on power over 2D.

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December, Leti signed an agreement to work with Qualcomm. ST and IBM have also been working with Leti in various areas.

Since before 2009, CEA-Leti has been busy working on processing flows to enable monolithic 3D devices. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper "Advances in 3D CMOS Sequential Integration" (subscription required). In that paper, she and her co-authors showed results for a sequentially processed P over N (no metal between transistor layers) test chip. In an IEDM 2011 paper, she and her colleagues showed a 50nm 3D sequential structure on 10nm channel silicon, illustrated below.

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications -- both parallel and monolithic -- with an inauguration event in January 2011. In December 2013, Soitec and CEA renewed their longstanding partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference is scheduled for Oct. 6-9 at the Westin San Francisco Airport. CEA-Leti will present its work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon. With five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories, this would be a great opportunity to learn more about monolithic 3D technology.

-- Brian Cronquist is vice president of technology and IP at MonolithIC 3D Inc. He has 35 years of semiconductor industry experience as senior director of technology development and foundry at the nonvolatile FPGA provider Actel (now Microsemi), starting and building Chartered Semiconductor-Singapore (now GlobalFoundries), running startup wafer fab engineering teams at Sierra Semiconductor (now PMC-Sierra), and developing process technology at AMI and Synertek/Honeywell. He has published more than 100 technical papers in the fields of semiconductor microelectronic radiation effects and hardening, as well as new 3D-IC, logic, antifuse, and flash processes, devices, and reliability. He holds more than 60 issued/pending patents.

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about overcoming silicon defects in monolithic 3d.

As dimensional scaling has reached the diminishing return era there is a buildup of interest in monolithic 3D as an alternative path forward. Both memory and logic vendors are moving to monolithic 3D. The memory vendors are in transition to 3D NAND and Samsung has already announced mass production of their V-NAND. BeSang has been working in monolithic 3D memory for many years and has recently signed a license agreement with SK Hynix. And now, in the logic arena, Qualcomm has voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling.” The reason is economic: … “although we are still scaling down, it’s not cost-economic anymore” (Karim Arabi, DAC 2014).

A key aspect of monolithic 3D is engineering the second layer to be especially thin, on the order of 100nm or less. This provides for tiny (10s of nm diameter) vertical connections which are dense, manufacturable, and stress-free.  They can be manufactured with well understood processing as these vertical connections would look very much like the metal to metal vias that the industry has been making for decades. This avoids the 10+ micron sized TSVs of parallel 3D and their associated reliability hazards, process cost, Keep Out Zones, and ‘newness risk’.

When performance is important, single crystal silicon based transistors are the way to go for stacked layers. So far, it seems that the best technique to form such thin mono-crystal layers with the required thickness control is to use the volume production and well proven ion-cut process. Many of the high performance monolithic 3D process flows utilize ion-cut techniques, sometimes called ‘Smart-Cut’.

However, use of ion-cut creates a small number of crystal defects in the very thin single crystal layer-transferred film. I’ll talk about some techniques that may be employed to solve this but, first, let’s explore why defects are created in the ion-cut process.

The high dosage of ions used in the process creates damage to the silicon lattice at, and near, the ion-stopping depth, such that the lattice becomes brittle there; hence, can be ‘cut’ or ‘exfoliated’ with a force (e.g., knife, water jet) or thermal anneal. After separation of the layer to be transferred from the donor substrate, this ‘donor layer’ will still have some of the silicon lattice damage from the embrittlement on one surface, and may also have some damage from the splitting process itself. Soitec, in the manufacture of SOI wafers, utilizes 1100-1200°C thermal anneals (both oxidizing and non-oxidizing) in combination with chemical-mechanical polishing (CMP) to repair the crystalline damage, as part of its SmartCut (ion-cut) process. However, these damage repair anneals are not compatible with the commonly used low melting point/hi-diffusivity interconnect metals like copper or aluminum of the lower device layer in a 3D stack. BeSang has a nice tutorial video explaining this on their website. Here’s a snapshot:

Further, the passage of the ions used in the ion-cut process creates a lower level of damage to the silicon lattice of the bulk of the to-be-transferred donor layer as the ions pass thru the lattice. This bulk lattice damage can cause junction leakage, and lower the performance of devices. Annealing this type of lattice damage requires temperatures of about 600°C or greater, which – again – is incompatible with the commonly used interconnect metals of the lower device layers in a 3D stack.

Now let’s look at two silicon device proven methods that are available to overcome the ion-cut induced defects and can be applied to the ion-cut layer transfer for monolithic 3D devices and  structures.

Radu et al. of Soitec, in U.S. Patent Application Publication 2013/0026663, describe a method for curing defects associated with ion-cut implantation by a CMP and then a laser anneal of the transferred singe crystal silicon layer.

Singe crystal silicon donor wafer 1 is ion-implanted with a heavy dose of hydrogen or helium ions to create a brittle region 11 as shown in Fig. 1A. Then the donor wafer is flipped over and bonded to the top of a receiver substrate 2 that may have transistors and interconnect metallization 20, shown in Fig. 1B. Layer 3 is a low thermal conductivity or thermal insulating layer that will help thermally protect the transistors and interconnect metallization 20 of substrate 2.

Fracturing along the brittle region 11 may be done with any number of techniques, such as mechanical knife, water or gas jet, etc., leaving behind transferred silicon layer 10. The transferred layer surface 12 may be CMP’d to remove the majority of the roughness and surface defects, resulting in Fig. 1C.

However, there are still bulk lattice damage centers in transferred silicon layer 10. Radu et al. takes care of them thermally by applying pulses of electromagnetic energy. Specifically mentioned are the pulsed lasers of Excico and JPSA.

The wavelength of the irradiation is chosen such that the majority of the pulsed energy is absorbed in transferred layer 10. The low thermal conductivity or thermal insulating layer 3 minimizes the thermal diffusion from the heated transferred layer 10 to the interconnect metallization and must be designed properly to handle the thermal pulse of the layer above. Temperatures high enough to cure the ion-cut induced defects and reactivate any ion-cut deactivated dopants in transferred layer 10 can be achieved. For example, as Figs. 5A and B show, the transferred thin (0.8um in this case) silicon layer (a) may achieve a temperature well above 1000°C from the laser pulse, and the interface (b) between substrate 2 and thermal insulating layer 3 will stay well below 400°C.

Fig. 5A shows the JPSA laser at 193nm and 20ns pulse FWHM (Full-Width Half-Max) and Fig. 5B shows the Excico laser at 308nm and 160ns pulse FWHM.

We have also published work on laser annealing at 2013 IEEE 3DIC and 2013 IEEE S3S Conferences showing how scaling trends can make monolithic 3D practical and the substantial design space of the laser wavelength/energy/pulse width, top layer thickness, and shielding/thermal protection layers which can make single crystal monolithic 3D possible.

Clearly, stacking of ultra-thin layers of defect free single crystal silicon can be readily accomplished and the tools to realize this are available from at least two vendors.

At ESSDERC (43rd Solid State Device Research Conference) in September of 2013, Radu et al. in collaboration with CEA-Leti, presented a different way of obtaining low defect single crystal silicon stacks. Low temperature Solid Phase Epitaxial Re-grow (SPER) is combined with ion-cut to demonstrate defect free diodes with processing temperatures less than 500°C.

SPER utilizes a small amount of crystalline silicon as a template to re-crystallize an amorphous silicon layer at temperatures just above 475°C and can be used to activate dopants above the solubility limit.

SPER can be combined with low temperature ion-cut (SmartCut) and bonding techniques to obtain defect free single crystal devices. Donor wafer doped silicon is amorphized before bonding and ion-cut implanted to create the brittle zone, flipped and bonded to the handle, SPER processed, and then thinned to remove the End Of Range defects.

No crystalline defects were seen utilizing the usual physical means:

However, the tougher test to satisfy is always the electrical one. Radu showed excellent diode characteristics, resistivity, concentration and mobility recovery. Here are some of their diode I(V) curves:

I would not be surprised if demonstration of transistors is published in the near future.

So, hopefully I have given you at taste of how ready an important piece of the monolithic 3D puzzle is to delivering on its promises. Back in December 2013, Soitec and CEA-Leti renewed their long-standing partnership for five additional years. I think it is safe to say that more will be coming soon.

Give me a call or email if you want to talk more…

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the latest news shared by Qualcomm.

"Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase." Speaking in a keynote at DAC 2014 in San Francisco, vice president of engineering Karim Arabi, is reported to argue that 3D and EDA need to make up for Moore’s Law.This was the third time in the past year that Qualcomm executives have made such a call at major industry conferences. At IEDM 2013 Geoffrey Yeap, Qualcomm VP of Technology, stated in his invited talk: "As performance mismatch between transistors and interconnects continue to increase, designs have become interconnect-limited. Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law." Yeap provided the following chart for the growing gap between transistor delay and interconnect delay

Earlier that year, Robert Gilmore, Qualcomm VP Engineering, in his invited talk at VLSI 2013 (Kyoto, Japan), used almost the same words and provided the following illustration (note the wafer is face-down):

Clearly there seems to be a concentrated effort by Qualcomm to promote the development and adoption of monolithic 3D.

Qualcomm has done more than just talking. It has been investing in monolithic 3D development tools with institutions such as Georgia Tech (see their GTCAD LAB website reporting technology transfer in 2012 and 2014). Qualcomm has been filing patents in this area and recently announced an agreement to work with CEA-Leti - Qualcomm to Evaluate Leti’s Non-TSV 3D Process

It would seem that the number one motivation behind these efforts is Qualcomm’s concern about future cost reductions. Early in 2012 Jim Clifford, Qualcomm's VP and GM (at that time), in his plenary talk at the SPIE conference titled - A Mobile Wireless Phenomenon: A Continued Need for Advanced Lithography, made it very clear with his second slide. At that time there were already some concerns with EUV’s rollout schedule. Jim called on the conference attendees to make sure to solve the escalation of advanced lithography cost, which was already dominating more than 50 % of the overall advanced device cost. Jim presented the following curve, showing the historical 29% cost reduction per year, and the looming problem with the production cost beyond 28 nm.

 Jim than said: "If the next node doesn't cost less than the last node we got a problem because I don't think the demand will be there." Well it is now clear that EUV is not ready and that dimensional scaling below 28nm will require double and triple lithography with its associated extra costs.

Back to the DAC 2014 keynote: Arabi explained: “Mobile is becoming a centre of gravity for the user. It is providing a unique opportunity ... but it becomes a challenge to develop because you have to integrate them at lower power and low cost as well ... One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down, it’s not cost-economic anymore. It’s creating a big problem for us.” As we reported in our recent blog, 28nm – The Last Node of Moore's Law, dimensional scaling below 28 nm will result in increasing device cost. This was echoed multiple times at this DAC by other keynote speakers such as Hossein Yassaie, CEO of Imagination Technologies, who said: “Moore’s Law is really over from my point of view. It’s not that it can’t scale, it’s that the cost is not going down anymore".

 And cost is not the only problem with dimensional scaling. The following IBM slide illustrates that interconnect now dominates device power.   

Interconnect’s effect on power is just getting worse with dimensional scaling. Arabi also stated in his DAC keynote: “Interconnect RC is inching up as we go to deeper technology. That is a major problem because designs are becoming interconnect-dominated. Something has to be done about interconnect. What needs to be done is monolithic three-dimensional ICs ... So we are looking at true monolithic 3D. You have normal vias between different stacks. Then interconnect lengths will be smaller than with 2D. If we can connect between layers the delay becomes smaller. This is a technology for the end of the decade, but it can give us an advantage of one process node, with a 30 per cent power saving and a 40 per cent gain in performance.”

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology with 5 invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories, CEA Leti will present their work on CMOS monolithic 3D IC, and researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the FPGA as ASIC Alternative. 

In our recent blog 28nm – The Last Node of Moore's Law we outlined the recent dramatic change that has happened after many years of cost reduction associated with dimensional scaling. It is clear now that 28 nm will provide the lowest cost per gate for years to come. In this blog we will assess the potential implications for the ASIC and the FPGA markets. Over the last two decades we have seen escalating mask set costs associated with dimensional scaling and accordingly escalating NRE costs. At the recent 2014 SEMI Industry Strategy Symposium (ISS) Ivo Bolsens, Xilinx CTO, presented the following chart of ASIC design cost escalation: 

The dramatic increases of ASIC design cost have had a real effect on the ASIC market, reducing the number of new designs and dramatically reducing the number of vendors serving the ASIC market.

One would expect that such a trend would have a very positive effect on the FPGA market, as there is no mask-set cost associated with an FPGA design and, accordingly, far lower NRE costs per design. The following fictitious chart presented in the EE Times article: What’s the number of ASIC versus FPGA design starts?, illustrates these expectations.

Surprisingly, this did not really happen. The following chart presents the overall FPGA market during the last decade according to the financial results of Xilinx, Altera and Actel.

The FPGA market growth could be compared to the overall semiconductor market growth as presented in the chart below (the market in 2013 was $305B). Clearly the FPGA market growth during the last decade is similar to the overall semiconductor market growth, and there is no indication of any benefits from the escalating ASIC mask-set cost and its associated NRE.

The FPGA technology started in the mid-1980s as an alternative to the popular ASIC technology then – the Gate Array. The acronym FPGA stands for Field Programmable Gate Array. During the 1990s the Gate Array technology lost its appeal and the ~$20B Gate Array market shrunk dramatically and effectively ceased to exist. Analyst expected that this will have a dramatic positive impact on the FPGA market, which did grow some but far from the expectations. The trend of escalating NRE driven by dimensional scaling and escalating lithography costs kept on going in the 2000s and drove down the number of ASIC designs. And, again, analysts expected a huge surge in the FPGA market. Clearly, this did not happen. 

In the following we will present our theory why it did not happen and some potential implications for the future.

We believe that the stagnation of FPGA growth is mostly due to the inefficiency of the FPGA technology. Most FPGAs use SRAM as the programming or ‘switch’ technology. Interconnects are the dominating resource in modern designs. Within an SRAM based FPGA the programming of interconnects is implemented by an SRAM cell control of a pass transistor, driver, or bidirectional driver. The following chart illustrates the diffusion area associated for such Programmable Interconnect Cell (PIC) assessed in 45nm technology and compared to the size of mask-defined equivalent – the via. The results indicate that the cell area overhead for the SRAM PIC is over 30X when compared to a via, which does not include the additional circuit overhead area needed to program and control the SRAM PIC.

This number had been reported in the industry for many years. A 2007 research paper by Ian Kuon and Prof Jonathan Rose (IEEE Transaction on Computer-Aided Design of IC and System) says this clearly: “In this paper, we have presented empirical measurements quantifying the gap between FPGAs and ASICs for core logic. We found that for circuits implemented purely using the LUT based logic elements, an FPGA is approximately 35 times larger and between 3.4 to 4.6 times slower on average than a standard-cell implementation.”

This high programmability overhead suggests that many of the current ASIC designs cannot be replaced by an FPGA design. Consequently, when advanced technology NRE is too high, the alternative is to use older node ASIC technologies. Since the number one driver for cost of mask-sets and NRE is the associated capital, the cost of older technologies goes down dramatically over time. The 30X area penalty means that one could use a node that is five generations older and have a competitive solution when compared to current node FPGA. Taking into account the 60% gross margin of the FPGA companies and the overhead of using a fixed-sized device of an FPGA family rather than a custom tailored Standard Cell device, these could compensate for an additional two nodes. Looking again at the design costs as illustrated in the Xilinx chart above, we can see that at 180 nm the design costs are pretty low and the mask set costs are too small even to register on the chart.

What has really happened is that many designs chose to use older node standard cells instead of an FPGA. In his last keynote presentation at the Synopsys user group (SNUG 2014) Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys newer tools to improve older node design effectiveness. The following chart is one of them and it also includes in its left side the current distribution of design starts. One can easily see that the most popular current design node is at 180nm. Clearly even such old node provides a better product than the state of the art FPGA.  

Now we understand why the escalating mask set and NRE costs have not resulted in a surge of FPGA designs but rather pushed designers to user older technology nodes that had depreciated enough to make their NRE cost less of an issue. The following chart of Design Starts per Node by IBS was recently presented in a Synopsys article "The new landscape of advanced design". It shows the design starts trend over time and, not surprisingly, indicates that designers migrate to more advanced nodes over a longer time and that the up and coming node these days is just 65 nm.

Recently EE Times published our blog, 28nm – The Last Node of Moore's Law. In it we presented that the 28nm node will be the end of cost reduction for dimensional scaling. Most analysts accept by now that 28 nm is going to be the lowest cost per gate for many years to come. 

There are potentially many implications of this change in Moore’s Law. One of those implications could affect the future of FPGAs.
Traditionally FPGAs have been, and still are, a technology driver of new logic technology nodes. This early adoption gave the FPGA customer a constantly better programmable platform for their designs. Now that dimensional scaling does not provide better cost, it will result in a build-up of pressure for FPGA customers to use a depreciated technology node as an alternative. Over time designers would see the NRE of 65nm going down to about what the 180nm NRE is today. Comparing a 65nm Standard Cell design to an FPGA of 28nm suggests that far more designs could be better off with Standard Cell. As 20 nm and 14 nm FPGAs would not provide a better cost than the 28 nm one, it means that the FPGA market could see a growing challenge in the coming years. 
 
Designers chose older nodes not just for its lower mask-set and NRE costs but also for availability of broader embedded options such as flash memories and analog cells. But those are becoming available on newer nodes over time as well. The 65 nm node is now ramping up and would become the preferred choice for new designs in a few years, as its mask-set cost and NRE keep going down thanks to deprecation and broader availability. As volume production of older designs winds down, vendors are reducing their costs to bring new designs in, and will soon make the 65 nm as easy to access as 180 nm is now. FPGA vendors will release newer products on 20nm and 14nm but those would not offer lower production costs than the 28 nm FPGA products and will be less and less competitive versus a ‘not too old’ technology node such as 65 nm. It only seems logical that these new semiconductor industry dynamics will have a negative effect on the FPGA market and a positive effect on ASIC and Structured ASIC technologies. 

Thus it behooves us to consider what can the FPGA vendors do to keep their business growth.
Interestingly, the same trend that now works against FPGA technologies could be used to improve their competitiveness. In the early days two major FPGA technologies were competing in the market. The SRAM technology and the anti-fuse technology. The SRAM technology had higher switch overhead, but ended up winning because it benefitted from two major advantages. First, it did not need any major process changes and could be adapted to newer nodes as soon as those could be fabricated. Second was their ability to reprogram the device over and over again. Now that new process nodes do not provide lower costs, FPGA vendors could look to other than SRAM technology as a new path to improve their programmable platforms. As for anti-fuse, the significant effort in recent years to develop RRAM technology opens the possibility of adopting antifuse technology that could offer re-programmability. Even more important is the fact that re-programmability these days is far less important as all FPGA designs utilize simulation technology and other EDA tools, as the trial and error methodology no longer can be effectively used for modern designs. 

A special type of antifuse programmable technology could be most effective – Antifuse-based 3D High Density FPGA. This type of programmable fabric leverages anti-fuse metal to metal technology, which use 3D transistors for programming the anti-fuses. The 3D transistors could handle the higher voltage required for the programming and provide the interconnect programming with minimal device density impact. The 3D anti-fuse programmable fabric density is very similar to a via programmable fabric. Via programmable fabrics has been used with structured ASICs such as those offered by eASIC and Triad Semiconductors (ViASIC). They provide a programmable fabric with about a 2X area penalty vs. mask-defined standard cell technologies. These antifuses could be made as one time or reprogrammable devices and be fully replaced by mask-defined vias for even lower cost volume production, as illustrated by the following chart

Going forward, the semiconductor industry needs to go through fundamental change. No longer is it sufficient to scale using the next node of dimensional scaling to provide better overall device value. From the 28 nm node going forward, the industry needs to open up for a broad range of innovation so to continue offering better products. We can only hope that this will drive the industry back to fast growth and support the future market of Internet-of-Things and Internet-of-Everything.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the latest news in semiconductor industry, the headlines that dominated last week's news papers about TSMC and Intel. 

 On January 14, 2014 we read on the Investors.com headlines page - Intel Seen Gaining Huge Pricing Advantage Over TSMC. Just three days later comes the responding headline: TSMC: We're "Far Superior" to Intel and Samsung as a Partner Fab.
These kinds of headlines are not seen too often in the semiconductor business domain and it is not clear what the objectives are for such. It will be hard to believe that this is an attempt to manipulate the investor community, yet there are only a handful of super high volume design wins that are driving the leading edge devices, and for those wins the fight should be taking place in the 'board' room. So let’s dive a bit into the details behind these headlines.
 The first headline relates to Jefferies analyst Mark Lipaci releasing an analysis report stating: "Intel will have a die size and transistor cost advantage over Taiwan Semiconductor (TSM) for the first time by fourth-quarter 2014, which could lead to a 50% pricing advantage in processors in 12 months, and a 66% pricing advantage in 36 months". We can find more information in the blog titled: Intel: Primed for Major Phone, Tablet Share on Cheaper Transistors, Says Jefferies. Quoting Lipaci: "At the same time that Intel has started focusing on computing devices in mobile form factors, it appears that TSMC is hitting a wall on the transistor cost curve. The chart below was presented by TSMC’s CTO. We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC for the first time ever in 4Q14. We believe Intel extends that cost lead 24 months after than in 2016."
Lipaci then used the following chart to illustrate the build up of Intel advantage vs. TSMC.

The Jefferies report goes further and provides the following charts for 14nm and 10nm.

 Clearly the primary advantage that the report is pointing out is the lack of the double margin associated with the foundry model vs. the IDM model. It seems that this argument has clearly been disproven by now. In the early days of the foundry industry most IDMs would argue that the foundry model would not work because of the double margin aspect - the foundry would need about 50% gross margin and then the fables company would need an additional 50% gross margin - which would make it completely uncompetitive vs. the IDM. 20 years later it was proven, again, that there is no "free lunch". The chip fabrication business needs a margin to be sustainable and the design business needs a margin to be sustainable. And the better business model is to have those managed by different companies as each could build excellence in its own value proposition. Intel did enjoy for many years effective exclusivity in the Windows based processors. Intel has not been able so far to show much success in mobile or any other non-Windows market. Since Intel is now trying to position themselves as a better foundry than TSMC, then clearly for their potential foundry customers this double margin argument is moot.  
 The charts above also compare Intel’s cost advantage vs. TSMC older nodes (Intel's 14nm vs. TSMC's 20 nm and Intel's 10nm vs. TSMC's 16nm). It is not clear that Intel is so far ahead. Intel 14nm had been delayed to the first quarter of 2014 and TSMC has committed to be in volume production in the later part of 2014. But the real competition is on the ability to bring fabless companies to volume using one's advanced process node. Key to this is the availability of libraries, EDA full tool set support, and major IP such as ARM processors. It is far from being clear that Intel is really far ahead of TSMC in this critical area. And then, these days it is not so clear that using a more advanced process node buys one an end-device cost advantage. In fact, the foundries have already made it clear that beyond the 28nm node they do not see cost reduction, due to the extra cost associated with advanced node lithography and other issues. Even Intel admitted at their latest analyst day that advanced nodes are associated with escalating depreciation and other costs, as illustrated by the following Intel chart - see the left most graph.

We should note that the Y axes of these graphs are logarithmic which indicate a significant increase of deprecation costs. However, Intel claims it will more than neutralize this increase of costs by accelerating the dimensional scaling when going to 14nm and 10nm, as is presented with the middle graph above. This would lead to an overall sustaining of the historical cost per transistor reduction as is illustrated by the rightmost graph above. Note: the asterisk (*) on those graphs indicates that numbers relating to 14nm and 10nm are forecasts only. Since Intel is committed to be in volume production at the 14nm node any day now, the number associated with 14nm should not be a forecast anymore and we hope to see them released soon.

The simple indication of technology node effective transistor density these days would be the bit cell size. As we have presented many times before, modern SoC device area is dominated by the embedded 6T SRAM. At IEDM 2013, TSMC made public their 6T SRAM bit cell area for 16nm: 0.07 sq. micron. We could not find any Intel public release for their 14nm 6T SRAM bit cell size. We did find an Intel chart for older nodes. This 6T bit cell size chart was presented at IDF2012:

Accordingly the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² = 0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm should be about 0.03 sq. micron or even smaller. As we don't have any official number we could wait until their early production devices of the 14nm node get analyzed or to the eventual release of their number. But short of an official number, we did find a 2013 presentation from the TRAMS project, of which Intel is a partner, as illustrated in the following charts:

It is now clear that EUV will not be available for the 14nm node, and accordingly the bit cell size from the chart above is 0.062 sq. micron. This is a bit better than that of TSMC but a far cry from 0.03 sq. micron.

If Intel does have a really good number, it would be reasonable to expect that they will make it public soon, to entice the high volume fabless companies such as Qualcomm and Apple to explore Intel’s foundry option.


As for the Jefferies analyst assertion "We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC", it is not clear if Intel’s R&D budget is truly larger. TSMC’s R&D budget is dedicated to the foundry side of the business while Qualcomm, Apple, ARM and many other fabless vendors R&D budgets support the design part of any new product release. The total ecosystem behind TSMC and ARM is clearly not smaller than that of Intel. In this month’s SEMI ISS Conference, IC Insights provided very interesting numbers regarding the record of 2013 as was reported in a blog titled:Is Intel the Concorde of Semiconductor Companies?


Top 10 CAPEX Spenders in 2013:

1. Samsung $12B
   
2. TSMC $11.2B
   
3. Intel $10.5B
   
4. GF $5.5B
   
5. SK Hynix $3.7B
   
6. Micron $3B
   
7. Toshiba $2.9B
   
8. UMC $1.5B
   
9. Infineon $880M
   
10. ASE (OSAT) $770M
    

Yes, Samsung and TSMC both outspent Intel. Just wait until you see the capacity numbers and you will know why.

Top 10 IC Wafer Capacity Leaders in 2013:

1. Samsung 12.6%
   
2. TSMC 10%
   
3. Micron 9.3%
   
4. Toshiba 8%
   
5. SK Hynix 7%
   
6. Intel 6.5%
   
7. ST 3.5%
   
8. UMC 3.5%
   
9. GF 3.3%
   
10. TI 3.0%
    

Clearly Intel is not larger than TSMC as a foundry and it is not clear why would it have a sustainable per transistor cost advantage.

Cost is important but it is far from being the only parameter when choosing a foundry partner. Selecting a foundry partner is truly selecting a partner. The design of leading edge devices is a very costly and lengthy effort, and has a pivotal effect on the business success for the fabless customer. TSMC had built trustful relationships for many years with its fabless customers. It is not clear how easy it is going to be for Intel to become a trustful foundry partner. So far it seems that Intel is still a proud IDM that insists that its customer will support its branding like the "Intel Inside" campaign or the recent announcement of Branding the cloud: Intel puts its stamp on cloud services across the globe. Intel’s repeating emphasis of their transistor cost advantage vs. that of TSMC suggests that Intel considers TSMC as their main competition for the mobile and tablet business. But then their consistent offering of SoC products for the space, as illustrated by the recent Intel chart below, and the Jefferies' cost analysis above, suggests that Intel is actually an IDM competing with the likes of Qualcomm in this space. It may create concerns in the minds of potential fables customers.

And as a final note, we don't know how much better the Intel process at 14nm and 10nm is vs. that of TSMC. We do know that when we ask someone for directions, if he says ‘make a right turn’ but with his hand he is pointing left, we should go ahead and turn left. So along with all of these confusing statements we learned just this week that Intel Cancels Fab 42, which was supposed to be the most advanced large capacity fab effort of Intel. I wonder if it should be considered as the hand pointing....

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about Moore's Law and the impact of it on the industry today.

The assertion that Moore made in April 1965 Electronics paper was:"Thus there is a minimum cost at any given time in the evolution of the technology. At present, it is reached when 50 components are used per circuit. But the minimum is rising rapidly while the entire cost curve is falling (see graph below)." 

"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years."

Clearly Moore's law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays - transistors) to achieve minimum cost will double every year.
The reduction of cost per component for many years was directly related to the reduction in feature size - dimensional scaling. But many other technology improvements made important contributions as well, such as increasing the wafer size from 2" all the way to 12".
But many observers these days suggest that 28nm will be the optimal feature size with respect to cost for many years to come. Below are some charts suggesting so:

And more analytical work by IBS’ Dr. Handel Jones

Graphically presented in the following chart

Or as nicely drawn by Globalfoundries

Recently EE Times reported that EUV Still Promising on IMEC's Road Map. IMEC provided a road map to transistor scaling all the way to 5nm, as illustrated in the following chart:

Yes, we probably can keep on scaling but, clearly, at escalating complexity and with completely new materials below 7nm. As dimensional scaling requires more advanced lithography it is clear that costs will keep moving up, and the additional complexity of transistor structures and all other complexities associated with these extreme efforts will most likely drive the costs even higher.
Looking at the other roadmap chart provided by IMEC and focusing on the SRAM bit cell in the first row, the situation seems far worse:

Since at 28 nm SRAM bit cell is already 0.081μm2, this chart indicates that future transistor scaling is barely applicable to the SRAM bit cell, which effectively is not scaling any more.
Unfortunately, most SoC die area is already dominated by SRAM and predicted to be so even more in the future, as illustrated by the following chart:

Source:. Y. Zorian, Embedded memory test and repair: infrastructure IP for SOC yield, in Proceedings the International Test Conference (ITC), 2002, pp. 340–349
Dimensional scaling was not an integral part of Moore's assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore. The following chart captures Samsung’s view of the future of dimensional scaling for NV memory, and it seems relevant to the future of logic scaling just as well.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about the scaling process that makes monolithic 3D IC practical.

In the 1960s, James Early of Bell Labs proposed three-dimensional structures as a natural evolution for integrated circuits. Since then many attempts have been made to develop such a technology. So far, none have been able to overcome the 400°C process temperature limitation imposed by the use of aluminum and copper in modern IC technologies for the underlying interconnects without great compromises. The “Holy Grail” of 3D IC has been the monolithic 3D, also known as sequential 3D, where a second transistor layer could be constructed directly over the base wafer using ultra-thin silicon – less than 100nm – thus enabling a very rich vertical connectivity.

Accordingly the industry developed a 3D IC technology based on TSV (Thru Silicon Via) where each strata (wafer) could be independently processed, then after thinning at least one wafer, place in a 3D configuration, and then connect the strata with TSV using a low temperature  (<400°C) process. This independent (parallel) processing has its own advantages; however, the use of thick layers (>50 µm) greatly limits the vertical connectivity, requires development of all new processing flows, and is still too expensive for broad market adoption. On the other hand, monolithic 3D IC provides a 10,000x better vertical connectivity and would bring many additional benefits as was recently presented in the IEEE 3D IC conference.

The semiconductor industry is always on the move and new technologies are constantly being introduced making changes the only thing that is constant. For the most part dimensional scaling has been associated with introducing new materials and challenges, thereby making process steps that were once easy far more complex and difficult. But not so in respect to monolithic 3D IC.

The amount of silicon associated with a transistor structure was measured in microns in the early days of the IC industry and has now scaled down to the hundreds and the tens of nano-meters. The new generation of advanced transistors have thicknesses in nanometers as is illustrated in the following ST Micro slide.

Dimensional scaling has also brought down the amount of time used for transistor activation/annealing, to allow sharper transistor junction definition, as illustrated in the following Ultratech slide

Clearly the amount of heat associated with transistor formation has reduced dramatically with scaling as less silicon gets heated for far less time.

And unlike furnace heating or RTP annealing, with laser annealing the heat is coming from the top and directed only on small part of the wafer as illustrated below.

The following illustrates Excico pulsed excimer laser which can cover 2×2 cm2 of the wafer.

Worth noting that this week we learned of good results when utilizing Excico laser annealing for 3D memory enhancement – Laser thermal anneal to boost performance of 3D memory device.

These trends help make it practical to protect the first strata interconnect from the high temperature process required for the second strata transistor formation. As the high temperature is on small amount of silicon for a very short time and for a small part of the wafer, the total amount of thermal energy required for activation/annealing is now very small.

One of the three most newsworthy topics and papers included in the 2013 IEDM Tip Sheet for the “Advances in CMOS Technology & Future Scaling Possibilities” track was a monolithic 3D chip fabricated using a laser (reported by Solid State magazine “Monolithic 3D chip fabricated without TSVs“). Quoting: “To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then used a novel low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated high performance – 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products.”

Furthermore, in last two weeks we presented in the IEEE 3D IC and IEEE S3S conferences an alternative simulation based work. We suggested to use a smart-cut® for the formation of the second strata (and not amorphous silicon crystallization) with innovative shielding layers to protect the first strata interconnect, as illustrated below.

Currently there are at least three different laser annealing systems offered on the market. The shielding layers could be adjusted according to the preferred choice of the laser annealing system. Our simulations show that if an excimer laser such as one offered by Excico is used, then even without these shielding layers the first strata routing layers are not adversely impacted by the laser annealing process.

Summary: In short, dimensional scaling is becoming harder and yet it makes monolithic 3D easier. We should be able to keep scaling one way or the other (or even both), and keep enjoying the benefits.

Note: smart-cut® s a register TM of Soitec