Intel vs. Intel

Will Intel 14 nm Continue the Historical Cost Reduction Curve

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about Intel's decision to continue with its historical cost reduction curve.

Along with many in the industry, we were pleased to see the release of Intel's 14 nm technical information on Aug. 11 - Intel Outlines 14nm, Broadwell. It does look like after an extended delay the 14 nm is coming and with it some clarity about the Intel 14 nm technology. Clearly this recent 14 nm information release is being presented by Intel to continue the historical trend of cost reduction and dimensional scaling. Undoubtedly, Intel’s 14 nm technology is a significant technological achievement and deserves full respect and appreciation. Yet, if one takes a closer look at this information, and especially with respect to prior information provided by Intel, there is room for some clarification.  

The above EE Times article provides the following numbers released by Intel on August 11:
"Compared to Intel's 22nm process, it will have:

• 42nm fin pitch, down .70x
• 70nm gate pitch, down .78x
• 52nm interconnect pitch down .65x
• 42nm high fins, up from 34nm
• a 0.0588 micron2 SRAM cell, down .54x

~0.53 area scaling compared to 22nm"
Let’s review the SRAM cell size of 0.0588µm². Yes, it is the smallest published size for a SRAM bitcell we have seen so far. Yet in our blog Intel vs. TSMC: An Update we wrote:  "Accordingly, the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² =0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm, it should be about 0.03 sq. micron or even smaller."

From Intel’s 2012 information release:

In the following table we calculated the expected bitcell size for 14nm according to simple dimensional scaling rules based on each of the bitcell sizes for each of the technology nodes in the above 2012 chart:

The above table indicates that SRAM bitcell scaling has been a challenge for some time but at 14 nm it broke totally away!

The recent Intel presentation argues for the continuation of historical scaling cost reduction to the 14 nm node as illustrated in the following Intel slide:

The graph in the middle shows the exponential increase in wafer cost with scaling; however, the argument made is that the more than 2X increase in transistor density compensates for the increase in wafer cost, resulting with the rightmost chart showing a consistent reduction in cost per transistor.

But the following Intel chart does not show a better than 2X density increase from 22nm to 14nm:

Actually the basic transistor gate pitch indicates only a x1.64 increase in transistor density.

As well, this is before accounting for the increase in RC associated with the narrower metal lines. This would require insertion of many more buffers and repeaters, further reducing the effective density increase.

Furthermore, back to the SRAM bitcell. The announced size for the Intel 14nm bitcell as presented above is not going to help offset the increase in wafer cost.

So it seems this would be a subject matter for more comments and blogs. However, I see no reasons to change my prior statements published in the EE Time blog titled: 28nm – The Last Node of Moore's Law.