Monolithic 3D Inc., the Next Generation 3D-IC Company
  • Home
  • Technology
    • Technology
    • Papers, Presentations and Patents
    • Overview >
      • Background
      • Why Monolithic 3D?
      • Paths to Monolithic 3D
      • Applications
    • Ion-Cut: The Building Block
    • Monolithic 3D Logic >
      • RCAT
      • HKMG
      • Laser Annealing
      • RCJLT
      • 3D Embedded RAM
      • 3D Gate Array
      • FPGA
      • Ultra Large Integration - Redundancy and Repair
    • Monolithic 3D Memory >
      • 3D DRAM
      • 3D Resistive Memories
      • 3D Flash
    • Monolithic 3D Electro-Optics >
      • 3D Image Sensors
      • 3D Micro-Displays
  • 3D-IC Edge
    • 3D-IC Edge
  • News & Events
    • News & Events
    • S3S15 Game Change 2.0 Video/P
    • Webcast
    • Webinar
    • Press Releases
    • In the News
    • Upcoming Events
  • About Us
    • About Us
    • History
    • Team
    • Careers
    • Contact Us
  • Blog
  • Simulators

Can Intel Beat TSMC?

11/25/2013

0 Comments

 
Picture
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about Intel vs. TSMC.

On Nov 21, 2013 Intel CEO Brian Krzanich, in the company Investor Meeting, presented company expansion focused on a foundry plan. “You will see us focusing on a broader set of customers,” said Krzanich. “If somebody can use our silicon, and make computing better, than we want it to run better on Intel. It’s inclusive, it’s all-inclusive,” Krzanich added, as covered by Barron's blog Intel: Competitors Have Given Up ‘Scaling’ Advantage in Moore’s Law

Intel clearly believes that it can beat the pure play foundries by an ongoing reduction of transistor cost while improving performance and power with dimensional scaling – essentially maintaining the trend of Moore's law just as in the past. Intel will “not take our foot off the pedal” of process technology, Krzanich explained, and he expects the company to be making parts as small as 10 nanometers in transistor size by 2015, versus today’s 22 nanometer parts. He was followed by Bill Holt, Intel’s EVP and head of semiconductor manufacturing, showing the following slide describing Intel expectations to drive down the cost per transistor. 
Picture
Figure 1
 Maintaining dimensional scaling is in-line with Holt’s previous slide presented at the Jefferies May 2013 Analyst Meeting:
Picture
Figure 2
Here we observe the first discrepancy where Intel says they are "continuing to scale while others are pausing to do FinFETS”, while the other foundries say that their transistor cost will not be reduced for nodes below 28nm. This was made very clear by GlobalFoundries in it recent seminars and is nicely illustrated in this ASML Semicon West 2013 slide:

Picture
Figure 3
This has also been generally accepted by analysts. Below is a slide from IBS’s Handel Jones presentation at the CEA-LETI day in June of this year:
Picture
Figure 4
       Some may argue that Intel will have a hard time competing as a foundry due to potential customer concern of Intel as a competitor. This is a valid point but it did not stop Apple to buy cell phone devices from Samsung.

           Some may argue that Intel will have hard time competing due to the lack of broad EDA and IP support. This is also a valid point but Intel does not need to win all fabless designs. If Intel wins just the few super high volume designs, it may well win the war.

           Some may argue that “Intel announced their high volume mobile SoFIA chips are mask fabricated at external foundry and do not use Intel internal manufacturing for at least next 2 years (2014-15). ALL of Intel's production for standalone modem chips today is outside Intel. Conclusion being Intel still does not have the right silicon technology for mobile computing which is why X86 less than 0.1% of Smartphone market" as one commenter at Intel Nears Foundry Inflection Point blog. This might be why Holt presented Intel’s plan to develop Foundry type processes. “Those products were optimized primarily for performance, and so Intel had avoided the problem that can crop up when transistors are packed more densely, namely that performance of the wires connecting transistors, the interconnects, can degrade. We didn’t scale the wires as much as we could have, because the products we were building didn’t demand that.” Now, he said, "the company’s technology would be focused more on those interconnects as Intel takes the scaling lead. The result would be the ability to more nimbly move between transistors optimized for performance, on the one hand, as in server and desktop chips, and transistors optimized for low-power mobile devices." as illustrated below:
Picture
Figure 5
It would seem that if Intel could scale transistor cost as they have done in the last 40 years then they could win these super high volume consumer-oriented designs where cost is extremely important. And TSMC is clearly taking this seriously. As was made public after they lost Altera to Intel, TSMC aligned itself to face head-on Intel’s challenge by expediting the development of FinFet technology.

As TSMC's P/E is 14.42 while Intel's P/E is only 12.87 the market should have responded very well to these presentations but apparently it did not — and in reverse to NASDAQ trend, Intel stock fell more than 5% the day after:

Picture
Figure 6
Nor did Altera's stock perform well since announcing the move to Intel as a foundry, especially when compared to Xilinx who choose to stay with TSMC, as the stock price chart below illustrates:
Picture
Figure 7
The Stock market might be wrong, as it been wrong many times before, but then there are other concerns:

  • Why did Intel feel the need to put so much money in the ASML EUV program if they can do just as well without EUV?

  • Does Intel reduced cost per transistor account for its escalating cost of R&D, which in 2013 averaged more than 20% of revenue vs. less than 14% in 2005?

  • Does Intel reduced cost per transistor account for its escalating cost of capital, which, per their balance sheet on Depreciation/Depletion, averaged in 2013 more than 26% of revenue vs. less than 10% in 2011?

It is not clear what the Intel proprietary technology is that allows it to do so much better than the foundries to produce a per transistor cost reduction. It does seem that their fab equipment and especially lithography is the same. And it also unclear why the Intel per transistor costs are not impacted by the much higher cost of lithography with the double and quadruple litho steps needed in manufacturing these advanced process nodes and the extra development and process steps required.

There is one more important issue that seems to be ignored. For SoC applications the embedded SRAM is a key factor because it dominates the die area, as we recently presented in our blog Are we using Moore’s name in vain?. If Intel’s embedded SRAM is scaling each node as before then it would represent an important advantage over the foundries. Yet Intel recently announced integration of DRAM into Haswell and promised future Xeon and Xeon Phi models that integrate memory atop processors in 3D packages instead. Will these be aggressive enough to keep the on-system memory costs scaling?  

Picture
Figure 8
In short, if Intel could keep the traditional 30% cost reduction per node from 28nm to 10nm, and the foundry’s cost per transistor is staying flat, then Intel would be able to provide their foundry customers SoC products at a third of ther other foundries cost, and accordingly Intel should be able to do very well in its foundry business.
submit to reddit
0 Comments

Your comment will be posted after it is approved.


Leave a Reply.

    Search Blog


    Meet the Bloggers


    Follow us


    To get email updates subscribe here:


    Recommended Links

    3D IC Community
    3D IC LinkedIn Discussion Group

    Recommended Blogs

    • 3D InCites by Francoise von Trapp
    • EDA360 Insider by Steve Leibson
    • Insights From the Leading Edge by Phil Garrou
    • SemiWiki by Daniel Nenni, Paul Mc Lellan, et al.

    Archives

    March 2022
    December 2021
    August 2021
    August 2018
    July 2018
    May 2018
    October 2017
    September 2017
    December 2016
    September 2016
    August 2016
    November 2015
    October 2015
    September 2015
    July 2015
    June 2015
    May 2015
    April 2015
    March 2015
    February 2015
    October 2014
    September 2014
    August 2014
    July 2014
    June 2014
    May 2014
    April 2014
    March 2014
    February 2014
    January 2014
    December 2013
    November 2013
    October 2013
    September 2013
    August 2013
    July 2013
    March 2013
    February 2013
    January 2013
    December 2012
    November 2012
    October 2012
    August 2012
    June 2012
    May 2012
    April 2012
    March 2012
    February 2012
    January 2012
    December 2011
    November 2011
    October 2011
    September 2011
    August 2011
    July 2011
    June 2011
    May 2011
    April 2011
    March 2011

    Categories

    All
    3d Design And Cad
    3dic
    3d Ic
    3d Nand
    3d Stacking
    3d Technology
    Brian Cronquist
    Dean Stevens
    Deepak Sekar
    Dram
    Education
    Heat Removal And Power Delivery
    Industry News
    Israel Beinglass
    Iulia Morariu
    Iulia Tomut
    Monolithic3d
    Monolithic 3d
    MonolithIC 3D Inc.
    Monolithic 3d Inc.
    Monolithic 3d Technology
    Moore Law
    Outsourcing
    Paul Lim
    Repair
    Sandisk
    Semiconductor
    Semiconductor Business
    Tsv
    Zeev Wurman
    Zvi Or Bach
    Zvi Or-Bach

    RSS Feed

© Copyright MonolithIC 3D Inc. , the Next-Generation 3D-IC Company, 2012 - All Rights Reserved, Patents Pending