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Please Help Me Understand IBM - Common Platform Technology Forum 2013

2/10/2013

3 Comments

 

"Innovations for Next Generation Scaling" 

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We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses The Common Platform Technology Forum 2013.

The 2013 Forum today (Feb 5, 2013) started with a presentation by Dr. Gary Patton, VP, IBM Semiconductor Research & Development Center. Gary very clearly articulated the two irresolvable challenges the industry now faces:

  • On chip interconnect
  • Lithography
These two challenges connect very well with our recent blog IEDM 2012 - The Pivotal Point for Monolithic 3D IC. Gary showed both the exponential increase of RC which results from the dimensional scaling of copper below 100nm width and the high cost associated with double and quad patterning. In addition, he showed how the extreme scaling of the copper metallization creates reliability challenges such as fatal EM modes, and scaling of the insulator k breeds TDDB and strength issues. As a reminder, in the recent IEDM (Dec. 2012) short course, IBM presented the following slide indicating that interconnect now dominates device power!
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L. Chang, D.J. Frank - IEDM 2012 Short Course – IBM Watson Research Center
Gary also presented a multi-decade past to future slide that resembles the one presented here below. The decade ending at the year 2000 was the good old days of easy scaling of planar transistor, which he called the gate oxide limit. Then the industry followed with a decade of "Material Innovation" that he called the planar device limit, and starting in 2010 is the beginning of the "3D Era" - 3D transistors and stacked devices.
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Figure 2
Finally he shared with us his vision of 3D devices with three planes of devices:

  • Logic Plane
  • Memory Plane
  • Photonic Plane
A vision we mutually share.

Now, here is my failure to understand. As a company who has been in the forefront of 3D and TSV research, IBM is well aware of the severe limitations of TSV as an alternative for vertical interconnect. The following cross-sectional picture by IBM, presented at the recent GSA Summit, clearly illustrates how large a TSV is in comparison to an interconnect via.
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IBM Systems and Technology Group – GSA Silicon Summit 2012 (S.s lyer) – 2012 IBM Corporation
With TSVs of 5 micron diameters (and pitches of 15 micron due to keep out zones from stress issues) vs. vias of less than 50 nm, the ratio in vertical connectivity is 1:10,000 as illustrated in the following chart by Perinne Batude of CEA Leti.
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Figure 4
Clearly IBM technologists are well aware of the many research papers showing that TSVs, with their relatively huge size compared to all the other on-chip elements, diminish the performance or power benefits in folding designs to 3D. For example, the chart below was presented by Kim at the 2011 IEEE International Interconnect Technology Conference. The chart illustrates the performance benefits of folding a design twice (4 tiers of transistors) as dependent on the via size. At a via size of 5 microns there are actually no benefits, while at a via size of 0.1 micron the benefits are the equivalent of two nodes of dimension scaling!!!

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Figure 5
So can someone please explain to me how come IBM is still talking about TSV as if it is the only representative of the "3D Era"???

And particularly now, when monolithic 3D is finally practical, and the NAND Flash memory vendors are adopting it across the board!?

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3 Comments
Bob Conn link
2/15/2013 05:35:29 am

I love the idea of 100nm vias. I worry about the yield of 10,000,000 or so stacked connections (e.g. separate FPGA configuration memory from user logic). I would expect a pretty low yield for 100% connectivity.

Reply
Zvi
2/16/2013 12:40:55 pm

Yield in semiconductor processing is always something we need to worry about. The advantage with monolithic 3D is that these via are very much the same as between any two successive layers in the device. We should remember that in monolithic 3D the layers are very thin. FD SOI use `7nm of silicon and ~25nm of 'box'. Accordingly these via are through less than 100nm.

Reply
John Barwin
7/16/2013 09:30:08 pm

Great article!

You present one perspective on the comparison of the two technologies. I can think of a few that would favor the TSV's though:

1)Mixing of technologies: TSV's could mix memory and logic technologies, etc.
2)Yields – think defect density.
3)Tooling for Design – there is a robust set of tools for designing 1D chips, and yet we make mistakes in the mask all the time. I would imagine there would be a significant amount of retooling required to facilitate robust M3D designs.

Both have the conundrum of how to deal with the thermal issues, especially for high performance applications.

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