Join MonolithIC 3D Inc. at IEEE International Conference on 3D System Integration (3D IC) on October 2nd -4th, 2013 in San Francisco, CA. Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. will present a guest tutorial on 3D IC edge. The company will also give the presentation: “Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC” in session VII of the event. You can access the Technical Program of the Conference here.
Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. will be featured as guest speaker to present a tutorial on Monolithic 3D IC. The tutorial describes the advantages of monolithic 3d as an alternative to maintain the exponential increase in integration. Some of the advantages of this technology include reductions of cost, decreases in power consumption, and improvements in performance, and bring some new and compelling benefits like:
“Monolithic 3D is a disruptive semiconductor technology. It builds on the existing infrastructure and know-how, and could bring to the high tech industry many more years of continuous progress. While it provides the advantages that dimensional scaling once provided, monolithic 3D offers many more options and benefits. And the best of all is that it could be done in conjunction with dimensional scaling. Now that monolithic 3D is practical, it is time to augment dimensional scaling with monolithic 3D-IC scaling.”
Even more, the company will also give a presentation in session VII on a new path for monolithic 3D IC: “Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC”. This work was done in collaboration with the Department of Electrical Engineering, IIT Bombay, India.
Abstract of presentation: Classical dimensional scaling faces challenges from growing on-chip interconnect time delays, and escalating lithography costs and layout limitations. In this paper, we present practical integration schemes for developing cost-efficient 3D ICs in a monolithic fashion, which employ fully depleted transistor channels and laser annealing to achieve sharper junction definition.
Join us at the most important event in the 3D IC industry held this year in San Francisco, CA on October 2nd - 4th, 2013. Here you can find the registration link and fee information to attend the conference.
Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. will be featured as guest speaker to present a tutorial on Monolithic 3D IC. The tutorial describes the advantages of monolithic 3d as an alternative to maintain the exponential increase in integration. Some of the advantages of this technology include reductions of cost, decreases in power consumption, and improvements in performance, and bring some new and compelling benefits like:
- Continuing reductions in die size and power,
- Significant advantages for reusing the same fab line and design tools,
- Heterogeneous Integration
- Processing multiple layers simultaneously, offering multiples of cost improvement
- Logic redundancy, allowing 100x integration at good yields
- Modular Platforms
“Monolithic 3D is a disruptive semiconductor technology. It builds on the existing infrastructure and know-how, and could bring to the high tech industry many more years of continuous progress. While it provides the advantages that dimensional scaling once provided, monolithic 3D offers many more options and benefits. And the best of all is that it could be done in conjunction with dimensional scaling. Now that monolithic 3D is practical, it is time to augment dimensional scaling with monolithic 3D-IC scaling.”
Even more, the company will also give a presentation in session VII on a new path for monolithic 3D IC: “Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC”. This work was done in collaboration with the Department of Electrical Engineering, IIT Bombay, India.
Abstract of presentation: Classical dimensional scaling faces challenges from growing on-chip interconnect time delays, and escalating lithography costs and layout limitations. In this paper, we present practical integration schemes for developing cost-efficient 3D ICs in a monolithic fashion, which employ fully depleted transistor channels and laser annealing to achieve sharper junction definition.
Join us at the most important event in the 3D IC industry held this year in San Francisco, CA on October 2nd - 4th, 2013. Here you can find the registration link and fee information to attend the conference.
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