Join MonolithIC 3D Inc. at the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference on October 7th thru 10th, 2013 in Monterey, CA. The conference will start with three plenary talks, one for each of the conference tracks. We are most honored for being invited to give the 3D Plenary Talk. Our thanks to the organizing committee for their invitation. We are pleased to see monolithic 3D technology is rapidly becoming part of the 3D IC field. MonolithIC 3D Inc. will be represented by Zvi Or-Bach, President and CEO of the company.
The 3D Plenary Talk will describe “Practical Process Flows for Monolithic 3D”. In this session Mr. Or-Bach will present three approaches to obtain 3D logic ICs. You can access the Technical Program of the Conference here.
Zvi Or-Bach: “Monolithic 3D ICs provides a practical short term path to keep the semiconductor industry on track with Moore's Law as dimensional scaling is reaching its diminishing return phase. Monolithic 3D IC allows the existing industry infrastructure and silicon knowledge to be utilized while research activities continue the search for other alternatives. It should be mentioned that we are also honored to be giving a tutorial on monolithic 3D at the IEEE 3D System Integration Conference on Oct 2-4, 2013, in San Francisco. At the tutorial we plan to present the many significant additional benefits that are available with monolithic 3D IC."
The three approaches which will be presented at S3S for monolithic 3D ICs are:
RCAT – Process the high temperature on a generic structure prior to layer transfer , and finish with cold processes; i.e., etch & depositions.
Gate Replacement (Gate Last HKMG) – Process the high temperature on a repeating structure prior to layer transfer, and finish with 'gate replacement' cold processes.
Laser Annealing – Use short laser pulses to locally heat and anneal the top layer while protecting the interconnection layers below from the topside heat.
In addition, the company will also present at the poster session the thermal compatibility of laser annealing of newly built 3D structures with transistors and interconnect circuits lying beneath in “Thermal Considerations for Monolithic Integration of Three-Dimensional Integrated Circuits”. This work was done in collaboration with the Department of Electrical Engineering, IIT-Bombay, India.
Abstract of poster: A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.
Please join us at the 2013 S3S Conference held this year in Monterey, CA October 7th thru 10th, 2013. Here you can find the registration link and fee information to attend the conference.
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