“The combination of 3D device architecture and low power devices will usher in a new era of scaling identified in short as <<3D Power Scaling>> The increase in the number of transistors per unit area will eventually be accomplished by stacking multiple layers of transistors”
This piece of news was covered in a blog post on the Solid State Technology Magazine emphasizing on the key finding and predictions of the 2013 ITRS.
You can read the entire article on the Solid State Technology Magazine here and read the Executive Summary of the 2013 ITRS here.