EETimes had a nice report on the recent International Symposium on Physical Design (ISPD), held March 27-30, 2011 in Santa Barbara, CA. For our purposes, the particularly interesting bits were:
"Also this year, innovative "computational lithography" for moving below 22-nanometers as well as 3-D interconnection techniques for "terascale computing" were described by Intel Labs, Tezzaron Semiconductor and others. For instance, Intel Fellow Vivek Singh described multi-mask patterning, pixilated masks and other computational lithography techniques that will be key to Intel's move to the 14-nanometer node, according to Singh.
Intel researcher Tanay Karnik described floor-planning, power routing, input/output circuits, test and assembly of 3-D processors stacked on DRAM. And Bob Patti, chieftechnology officer of Tezzaron Semiconductor, gave a side-by-side comparison of the improvements enabled by 3-D chip stacking, including 40 percent power reduction, a four-times density increase, over 300 percent performance boost, and 50 percent cost reduction."
I especially appreciate the report from Tezzaron. At the risk of being repetitive: 40% reduction in power, 4X density and performance increases and a 50% cost reduction. That's why we love 3D, and why I believe that it's the only way to continue to realize the benefits that we have achieved from X/Y scaling,
- Post by Dean Stevens, VP of Marketing
- Post by Dean Stevens, VP of Marketing
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