EETimes: Momentum builds for 3-D chips

EETimes published a nice article highlighting the "rise" (hey, an EETimes joke) of die stacking.

While much of the article rings completely true, ...

"... There are fears that IC scaling is becoming too costly for most chip makers-or will end in the distant future.

So instead of scaling, there is another concept on the table: stack and connect devices in a 3-D configuration..."

I wish that they had expanded the discussion beyond TSVs.  While Through Silicon Vias are currently a mainstream solution, our solution better addresses multiple issues with alignment, die area, thermal expansion and capacitance.

- post by Dean Stevens, MonolithIC 3D VP of Marketing