As we have predicted two and a half years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.
Our march 2014 blog Moore’s Law has stopped at 28nm! has recently been re-confirmed. At the time we wrote: “From this point on we will still be able to double the amount of transistors in a single device but not at lower cost. And, for most applications, the cost will actually go up.” This reconfirmation can be found in the following IBS cost analysis table slide, presented at the early Sept FD-SOI event in Shanghai.

​Gate costs continue to rise each generation for FinFETs, IBS predicts.

​And even Intel has given up on its “every two years” but still claims it can keep reducing transistor cost. Yet Intel’s underwhelming successes as a foundry suggests otherwise. We have discussed it in a blog titled Intel -- The Litmus Test, and it was essentially repeated by SemiWiki’s Apple will NEVER use Intel Custom Foundry!
This discussion seems academic now, as the actual engineering costs of devices in advanced nodes have shown themselves to be too expensive for much of the industry. Consequently, and as predicted, the industry is bifurcating, with a few products pursuing scaling to 7nm while the majority of designs use 28nm or older nodes.
The following chart  derived from TSMC quarterly earnings reports was published last week by Ed Sperling in the blog Stepping Back From Scaling:

Yes, the 50-year march of Moore’s’ Law has ended, and the industry is now facing a new reality.

This is good news for innovation, as a diversity of choices helps support new ideas and new technologies such as 3D NAND, FDSOI, MEMS and others. These technologies will enable new markets and products such as the emerging market of IoT.
​
A good opportunity to learn more about these new scaling technologies is the IEEE S3S ’16, to be held in the Hyatt Regency San Francisco Airport, October 10th thru 13th, 2016. It starts with 3D and FDSOI tutorials, the emerging technologies for the IC future. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D, and three leading researchers from an imec, MIT, and Korea university collaboration will present their work on advanced monolithic 3D integration technologies. Many other authors will discuss their work on monolithic 3DIC and its ecosystem, in addition to tracks focused on SOI, sub-VT and dedicated sessions on IoT.
​

The industry is at a crossroads: some designs pursue scaling to 7nm while the majority stay on 28nm or older nodes.
As we have predicted more than two years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.
Our 2014 blog 28nm — The Last Node of Moore's Law has now been confirmed. At the time we wrote: “After the 28nm node, we can continue to make transistors smaller, but not cheaper.” It is illustrated in the following slide, presented by Samsung at the recent Semicon West 2016.

Intel did announce that going forward, the time between nodes will increase but it still claims it can keep reducing transistors cost. Yet Intel’s underwhelming successes as a foundry suggest otherwise. We have discussed it in a blog titled Intel — The Litmus Test, and it was essentially repeated in Apple will NEVER use Intel Custom Foundry! “Yes, Intel will argue that their 10nm and 7nm are better than the foundries (TSMC and Samsung) but that will have to be proven at the chip level which is based on PPAC (power, performance, area, AND cost). The foundries have beaten Intel at every node based on SoC PPAC and I do not expect that to change at 10nm or 7nm.”
This discussion seems academic now, as the actual engineering costs of devices in advanced nodes have shown themselves to be too expensive for much of the industry. Consequently, and as predicted, the industry is bifurcating, and few products pursue scaling to 7nm while the majority of designs use 28nm or older nodes.
The following chart  derived from TSMC quarterly earnings reports was published last week by Ed Sperling in the blog Stepping Back From Scaling:

Yes, the 50-year march of Moore’s’ Law has ended, and the industry is now facing a new reality.
Similar industry dynamic has also been shown in a blog by MentorEstablished Technology Nodes: The Most Popular Kid at the Dance. Key quote:
“designs at 65 nm and larger still account for approximately 43% of all wafer production and 48% of wafer fab capacity. Even more significant, nodes 65nm and larger account for approximately 85% of all design starts (see charts below, source: VLSI Research). Clearly, established nodes are not fading away any time soon.”

This is good news for innovation, as a diversity of choices helps support new ideas and new technologies such as 3D NAND, FDSOI, MEMS and others. These technologies will enable new products for the emerging market of IoT.
A good conference to learn more about these new scaling technologies is the IEEE S3S ’16, held in the Hyatt Regency San Francisco Airport, October 10th thru 13th, 2016. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D, and three leading researchers from imec, MIT, and Korea universities collaboration will present their work on advanced monolithic 3D integration technologies, and many other authors will discuss their work on monolithic 3DIC and its ecosystem, in addition to tracks focused on SOI, sub-VT and dedicated sessions on IoT.

Happy Thanksgiving from MonolithIC 3D Inc. Team.

We would also like to share with you our latest participation at the S3S 2015 Conference by providing you with a video tutorial: S3S Video/presentation on Game Changing 2.0

IEEE S3S 2015 could be the turning point for monolithic 3D. During Oct. 4-7 we will have the option to get a short course, invited and selected presentations from a broad range of the industry representatives. They include major vendors such as Qualcomm, Global Foundries and Applied Materials; leading research organization like CEA Leti, Taiwan National Applied Research Labs, German IMS Chips, NASA; leading Universities like Berkeley and Stanford; start-ups like SiGen and MonolithIC 3D.  
In its tutorial session Qualcomm will explain why it is investing and promoting 3D VLSI (3DV) as an alternative scaling technology, as is illustrated by the following two slides:

Yet many people still have doubts as is reflected by the title of the panel we were invited to participate in -- “Monolithic 3D: Will it Happen and if so…” -- at the IEEE 3D-Test Workshop Oct. 9, 2015.
The doubts likely relate to the technology challenge that is illustrated in the following slide:

The question, in short, is how we can add more transistors monolithically interconnected to the underlying transistors without exceeding the thermal budget for the underlying transistors and interconnect.
 
The current paths to monolithic 3D involve major changes to the front line process flow and require the development of a new logic transistors. The big concern is that leading edge vendors are too busy with dimensional scaling and if anything else could be done it seems that FD-SOI would be it, while trailing edge fabs are, in most cases, avoiding any major transistor process development. The recent failure of Suvolta could be an indication of this reality. 
Hence the importance of Game-Changing 2.0, a major technology innovation to be unveiled on Wednesday by MonolithIC 3D in a paper titled: “Modified ELTRAN® - A Game Changer for Monolithic 3D”. The paper will present a novel use of the ELTRAN® process developed by Canon about 20 years ago primarily for SOI applications. Using ELTRAN (Epi. Layer Transfer) techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change its current front-line fab process. This flow is further simplified and could be integrated with the monolithic 3D flow introduced last year that leverages the emerging precision bonders, such as EVG’s GeminiÒ XT FB. This flow provides a ​natural path for product innovation and an unparalleled competitive edge to its adopters. In addition, this game-changing breakthrough offers a very cost-competitive flow.  The following chart illustrates the original use of ELTRAN process for the fabrication of SOI wafers:

 In the “Invited Talks on M3DI” at the conference we will have an opportunity to learn from the inventor of the ELTRAN process, Dr. Takao Yonehara, currently with Applied Materials, in his “Epitaxial Layer Transfer Technology and Application” talk. Prior to Applied Materials Dr. Yonehara worked with Solexel, a Silicon Valley startup, to deploy the ELTRAN process for low cost solar cell fabrication. Yonehara’s talk will be followed by Prof. Joachin Burghartz of Institute for Microelectronics in Stuttgart, discussing “Ultra-thin Chips for Flexible Electronics and 3D ICs” that uses a variation of such flow in small scale production.
The semiconductor industry is bifurcating these days into a segment that follows aggressive scaling for few super-value applications supported by very few vendors, while the bulk of the industry is enhancing old fabs targeting mainstream applications and the emerging IoT opportunities. Further enhancing these older fabs with monolithic 3D offers a most effective return on investment. Game-Changing 2.0 means that without a need for major process R&D efforts or new equipment, the path for 3D scaling is now open with enormous advantages for IoT. Accordingly, my answer to the original question above is summarized by the title of our invited talk at the IEEE 3D-Test Workshop:“Monolithic 3D is Already Here – the 3D NAND – and Now it would be Easy to Adapt it for Logic.”
​In addition the other division – SOI and SubVt provide good complementing technology updates for the power-performance objectives that are so important for these emerging markets.
Do come to the S3S and enjoy unique key technologies update with the great wine and country pleasures of Sonoma Valley.

We were invited to join a panel session titled: "Monolithic 3D: Will it Happen and if so..." at IEEE 3D-Test Workshop Oct. 9th, 2015. So we are happy to see monolithic 3D on the title, but then the title also suggests that the industry is wondering is it real or is it a pipe dream. The doubts are in opposition to companies such as Qualcomm who strongly advocate it, and the support CAE which Leti, in collaboration with ST Micron and IBM,are presenting monolithic 3D as the "low-cost scaling" for 2018. See chart below from July 2015 Leti Day.

The doubts might relate to the technology challenge illustrated by the following slide:

The upcoming IEEE S3S Conference 2015 in Sonoma, CA, on October 5th thru 8th provides comprehensive coverage of R&D activities in the monolithic 3D space. It starts with short courses on Monday. On Tuesday there will be a planery talk - "Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration" by Prof. Tsu-Jae King Liu, followed by "3D-Invited Monolithic 3D Alternative Technologies" session with representatives of Qualcomm, CEA Leti, Taiwan National Nano Device Laboratories, Stanford University and UCLA presenting and updating on the state of monolithic 3D technologies currently being developed arround the world as being illustrated in the following slide:  

Then on Wednesday we would have an additional session of “Invited Talks on M3DI” followed by a “Selected Papers on M3DI” session.
In short the most comprehensive technical event on the emerging monolithic 3D technologies. 
Yet – the question “Monolithic 3D: Will it Happen…” is still being asked.
The concerns are that the leading edge vendors are too busy these days still with dimensional scaling and if anything else could be done it seems that FD-SOI would be it; while trailing edge fabs, are in most cases, avoiding any major transistor process development. The recent failure of Suvolta could be an indication of this reality.  
Here comes Game-Changing 2.0. A major technology innovation to be unveiled on Wednesday by MonolithIC 3D in a paper titled: “Modified ELTRAN® - A Game Changer for Monolithic 3D”. This paper will present a novel use of the ELTRAN® process developed by Canon Inc. about 20 years ago primarily for SOI applications. Using ELTRAN (Epi. Layer Transfer) techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change the current frontline fab process. This flow is further simplified and could be integrated with the game changing monolithic 3D flow introduced last year which leverages the emerging precision bonders, such as EVG’s Gemini® XT FB. This flow provides a natural path for product innovation and an unparalleled competitive edge. In addition, this game-changer breakthrough offers a very cost competitive flow.  The following chart illustrates the original use of ELTRAN process for the fabrication of SOI wafers: 

In the “Invited Talks on M3DI” we will have an opportunity to learn from the inventor of the ELTRAN process Dr. Takao Yonehara, currently with Applied Materials, in his talk “Epitaxial Layer Transfer Technology and Application”. Prior to Applied Materials Dr. Yonehara worked with Solexel, a Silicon Valley start up, to deploy the ELTRAN process for low cost solar cell fabrication. This talk would be followed by Prof. Joachin Burghartz of Institute for Microelectronics Stuttgart, talk on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” where they use a variation of the flow in small scale production.
The semiconductor industry are bifurcating these days into one a segment that follows aggressive scaling for few super-value applications supported by very few vendors, while the bulk of the industry is enhancing old fabs while targeting the main stream applications and the emerging IoT opportunities. Further enhancing these older fabs with monolithic 3D would be a most effective return on investment. As indicate by the CEA slide above – “low cost scaling” and by a paper to be presented by Global Foundries showing monolithic 3D provides Power-Performance-Area (PPA) equivalent to dimension scaling at fraction of the cost. The Game-Changing 2.0, mean that without need for major process R&D efforts or new equipment the path for 3D scaling is now open with enormous advantages for IoT. And accordingly my answer to the above question is encompassed in the title of the invited talk prior to the panel “Monolithic 3D is Already Here – the 3D NAND – and Now it would be Easy to Adapt it for Logic”
In addition the other division – SOI and SubVt provide good complementing technology updates for the power performance objectives that are so important for these emerging markets. So do come to the S3S and enjoy unique key technologies update with the great wine and country pleasures of Sonoma Valley.

The forthcoming IEEE S3S Conference 2015 ,Sonoma, CA, on October 5th thru 8th, will focus on key technologies for the IoT era. It is now accepted that the needs for the emerging IoT market are different from those which drive the high volume PC and Smart-Phone market. The following Gartner slide illustrates this industry bifurcation where traditional mass products follow the – ever more expensive – scaling curve, while IoT devices, with their focus on cost, power, flexibility and accessibility, will seek place near its minimum.

The current high volume is focus on handful of foundries and SoC vendors driving a handful of designs at extremely high development cost each, processed at the most advanced nodes, with minimal processing options. In contrast, the emerging IoT market is looking for older nodes with lower development costs, broad range of process options, with many more players both at the foundry side and the design side.

For the IoT market the key enabling technologies are extreme low power, as enabled by SOI and sub-threshold design, integrating with multiple sensor technologies and communication technologies that ca be enabled by 3D integrations. All of these combined in forming the IEEE S3S unified conference.

This year conference includes many exciting papers and invited talks. It starts with three plenary talks: 

• Gary Patton – CTO of Global Foundries: New Game Changing Product Applications Enabled by SOI
  
• Geoffrey Yeap – VP at Qualcomm.: The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology
  
• Tsu-Jae King Liu – Chair of EE Division, Berkeley University: Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration
  

The following forecast from BI Intelligence suggest that the semiconductor technologies that are in good fit for the future market of IoT should be prime interest for the semiconductors professionals

Quoting Jim Walker, Research VP at Gartner presented on the “Foundry vs. SATS: The Battle for 3D Wafer Level Supremacy”. He argued 3D ICs are the key enabler of performance and small form factor of products required for IoT.


Hence the coming IEEE S3S conference provides important opportunity to catch up and learn about these technologies.

Let me share with you some nuggets from the monolithic 3D integration part of the conference:

Prof. Joachin Burghartz of the Institute for Microelectronics Stuttgart will deliver an invited talk on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” that will present a process technology to fabricate flexible devices 6-20 micron thin. This process flow is currently in manufacturing in their Stuttgart fab, as described below;

Another interesting discussion will be presented by NASA scientist Dr. Jin-Woo Han who will describe “Vacuum as New Element of Transistor”. These transistors are made of “nothing” and could be constructed within the metal stack, forming monolithic 3D integration with silicon-based fabric underneath.

In his invited talk titled “Emerging 3DVLSI: Opportunities and Challenges” Dr. Yang Du will share with us Qualcomm views on monolithic 3D IC which they term 3DVLSI and could be illustrated by the following figure which seems very fitting for IoT applications 

Globalfoundries will present joint work with Georgia Tec. titled “ Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs”. This work again shows that monolithic 3D can provide a compelling alternative to dimension scaling as illustrated by the following chart.

We will present “Modified ELTRAN® - A Game Changer for Monolithic 3D” that shows a practical flow for exiting fab to process monolithic 3D devices using their exiting transistor process and equipment. This flow leverages the work done by Canon about 20 years back called ELTRAN, for Epitaxial Layer Transfer. The following slide illustrates the original ELTRAN flow.

By deploying the elements of this proven process, a multilayer device could be built first by processing a multilayer transistors fabric at the front end of line, and then process the metal stacks from both top and bottom sides.

The conference includes many more interesting invited talks and papers covering the full spectrum of IoT enabling technologies. In addition, the conference offers short course on SOI application and monolithic 3D integration, and a fundamental class on low voltage logic.

New technologies are an important part of the future of semiconductor industry, and a conference like the S3S would be a golden opportunity to step away for a moment from the silicon valley, and learn about non-silicon and silicon options that promise to shape the future. 

The forthcoming IEEE S3S Conference 2015 ,Sonoma, CA, on October 5th thru 8th, will focus on key technologies for the IoT era. It is now accepted that the needs for the emerging IoT market are different from those which drive the high volume PC and Smart-Phone market. The following CEA Leti slide illustrates this industry bifurcation where traditional mass products follow the – ever more expensive – scaling curve, while IoT devices, with their focus on cost, power, flexibility and accessibility, will seek place near its minimum.

The current high volume is focus on handful of foundries and SoC vendors driving a handful of designs at extremely high development cost each, processed at the most advanced nodes, with minimal processing options. In contrast, the emerging IoT market is looking for older nodes with lower development costs, broad range of process options, with many more players both at the foundry side and the design side.

For the IoT market the key enabling technologies are extreme low power, as enabled by SOI and sub-threshold design, integrating with multiple sensor technologies and communication technologies that ca be enabled by 3D integrations. All of these combined in forming the IEEE S3S unified conference.

This year conference includes many exciting papers and invited talks. It starts with three plenary talks:

• Gary Patton – CTO of Global Foundries: New Game Changing Product Applications Enabled by SOI
  
• Geoffrey Yeap – VP at Qualcomm.: The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology
  
• Tsu-Jae King Liu – Chair of EE Division, Berkeley University: Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration
  

Prof. Tsu-Jae King will present in her talk an extremely low power nano-mechanical switch that could be fabricated within the metal stack. The slide below describes some of its characteristics.

Prof. Joachin Burghartz of the Institute for Microelectronics Stuttgart will deliver an invited talk  on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” that will present a process technology to fabricate flexible devices 6-20 micron thin. This process flow is currently in manufacturing in their Stuttgart fab, as described below;

Another interesting discussion will be presented by NASA scientist Dr. Jin-Woo Han who will describe “Vacuum as New Element of Transistor” As shown below

These transistors are made of “nothing” and could be constructed within the metal stack, forming monolithic 3D integration with silicon-based fabric underneath.

The conference includes many more interesting invited talks and papers covering the full spectrum of IoT enabling technologies. In addition, the conference offers short course on SOI application and monolithic 3D integration, and a fundamental class on low voltage logic.

Among the papers we will present “Modified ELTRAN® - A Game Changer for Monolithic 3D” that shows a practical flow for exiting fab to process monolithic 3D devices using their exiting transistor process and equipment. This flow leverages the work done by Canon about 20 years back called ELTRAN, for Epitaxial Layer Transfer. By deploying the elements of this proven process, a multilayer device could be built first by processing a multilayer transistors fabric at the front end of line, and then process the metal stacks from both top and bottom sides. The following slide illustrates the resulting monolithic 3D structure.

New technologies are an important part of the future of semiconductor industry, and a conference like the S3S would be a golden opportunity to step away for a moment from the silicon valley, and learn about non-silicon and silicon options that promise to shape the future.

This year Semicon West had a clear undertone – the roadmap forward is 3D IC. Yes, we can and we will keep pushing dimensions down, which for a few applications would be attractive, but for most designs the path forward would be “More than Moore.” As Globalfoundries' CEO Jha recently voiced: “it's clear that More-than-Moore is now mainstream rather than niche. …Really it is leading-edge pure digital that is the niche. Instead the high-cost leading edge processes are really niche processes optimized for applications in data centers or for high computational loads, albeit niches with volumes of hundred of millions of units per year.” Similarly, EE Times editor Rick Merritt subtitled his Semicon West summary Roadmap being drawn for chip stacks. All this is nicely illustrated by the following slide presented by An Steegen of IMEC for their pre-Semicon Technology Forum:

Leti, the other major semiconductor R&D organization, has gone even further by dedicating its Semicon West day entirely to 3D technologies, as can be seen in the following invitation:
2015-LetiDay-SanFrancisco

GOING VERTICAL WITH LETI: Solutions to new applications using 3D technologies

•         Welcome - Leti's 3D integration for tomorrow's devices > M.N Semeria

•         CoolCubeTM: 3D sequential integration to maintain Moore's Law > O. Faynot

•         Photonics: why 3D integration is mandatory > H. Metras

•         Computing: 3D technology for better performance > S. Cheramy

•         Lighting: 3D integration for cost effectiveness > I. C Robin

•         Nanocharacterization for 3D > P. Bleuet

•         Conclusion - Silicon Impulse > M.N Semeria
  

For more information: didier.louis@cea.fr
Come and visit Leti on European Pavilion

A similar view was also presented by Intel. Quoting Jeff Groff from his summary of Intel’s Q2 call: “In summary, it seems that Intel is executing fairly well on the process technology side of the business considering the ever increasing difficulty of pushing forward with Moore's Law. We can expect exciting new structures and materials (just maybe not at 10nm) and an increasing importance of 3-D structures in both logic and memory fabrication.” This echoes our blog Intel Calls for 3D IC, and was recently voiced by Intel’s process guru Mark Bohr: “Bohr predicted that Moore's Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.” It is also illustrated by his slide from ISSCC earlier this year.

The two concerns regarding 3D IC stacking using TSV are (a) Cost, noted in the slide above “Poor for Low Cost”, and (b) Vertical connectivity, as voiced by Mark Bohr: “Intel’s Bohr agrees that 3D structures will become more important. He said the kind of through-silicon vias used for today’s chip stacks need to improve in their density by orders of magnitude.”

These limitations are the driver behind the efforts to develop monolithic 3D technology. Monolithic 3D would provide a very cost effective alternative to dimensional scaling with 10,000x higher than TSV vertical connectivity, as illustrated by the following two slides of CEA Leti.

Prof. Subhasish Mitra of Stanford assesses a 1,000x improvement in energy efficiency using monolithic 3D. His summary at a Semicon West keynote panel: “We have an opportunity for a thousand-fold increase in energy efficiency…from collaboration between dense computing and memory elements and dense 3-D integration of them.”

While stacking using TSV does not require any change to the transistor (‘front-line’) process flow, all monolithic 3D process flows until recently required a significantly new transistor formation flow. Since the transistor process is where the majority of the R&D budget and talent is being allocated, and carries with it fresh reliability concerns, the industry has been most hesitant with respect to monolithic 3D adoption. Yet in this recent industry gathering there is a sense that industry wide interest is building up for 3D technologies. The success of 3D NAND as the first monolithic 3D industry wide adoption could help this new interest build even faster.

There is room for even more excitement. A recent technology breakthrough, first presented in IEEE S3S 2014 conference (Precision Bonders - A Game Changer for Monolithic 3D) introduced a game changer in the ease of monolithic 3D adoption. Enhancement of this breakthrough will be presented in this year’s IEEE S3S 2015. This new monolithic 3D flow allows the use of the existing fab transistor process for the fabrication of monolithic 3D devices, offering a most attractive path for the industry future scaling technology.


P.S.

A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program, three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies, and many other authors will be talking about their work on monolithic 3DIC and its ecosystem.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. 
Vivek Singh, an Intel fellow, in his DAC 2015 keynote Moore's Law at 50: No End in Sight presented again the Intel chart below suggesting straight (log) line transistor cost reduction with dimensional scaling. In fact, his cost/transistor drop even seems to accelerate beyond the linear at 14 and 10 nanometers.

Vivek Singh, an Intel fellow, in his DAC 2015 keynote Moore's Law at 50: No End in Sight presented again the Intel chart below suggesting straight (log) line transistor cost reduction with dimensional scaling. In fact, his cost/transistor drop even seems to accelerate beyond the linear at 14 and 10 nanometers.

Less than a week later, Handel Jones (IBS) in his blog 10nm Chips Promise Lower Costs published an update down to 10nm of his well-known chart, presented below, of transistor cost with scaling.

Yes, 10 nm transistor cost is a bit less than that of the 16/14nm node, but still higher than that of the 28nm node and clearly showing that the historical cost reduction of 30% per node stopped at 28nm node. From that point on Handel Jones’ cost projections have been either flat or even a bit higher. Clearly, those charts are in a striking contradiction!

The IBS chart had been supported by the other foundries and their customers, as illustrated by quotes such as the following: “Samsung spent several years developing its 14nm technology and debating which process node it would invest in after 28nm. Low expects that 28nm will still be a popular process node for years to come because of its price…The cost per transistor has increased in 14nm FinFETs and will continue to do so, …”(http://www.eetimes.com/document.asp?doc_id=1326369), “Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase. .. Now, although we are still scaling down it’s not cost-economic anymore” Karim Arabi, Qualcomm VP of engineering, DAC 2014 Keynote

While the Intel chart Y axis has nominal values, we can plot Intel’s straight line cost reduction on the IBS chart as illustrated below on a half log scale:

Before jumping to our assessment of the cost difference between the green bars and Intel’s blue line, I’d like to direct you to a very detailed comment made by the “IJD” reader to Handle Jones’ blog. IJD suggests that Intel cost reduction could be explained by Intel’s very high starting point “since they effectively have a monopoly in one of the highest-margin highest volume chip markets which is x86 CPUs.”
Intel has repeatedly used their chart in effort to promote their foundry business in competition with TSMC and in the process won the Altera business. Consequently, it seems important that we should compare Intel’s  costs as illustrated by the blue line vs. the green bars as reported by the rest of the industry.

We should consider the following points:

1.     The Intel chart, while illustrating a simple formula, does seem logically faulty. The exponentially escalating cost of wafers needs to be neutralized by exponentially escalating scaling beyond the historical 0.7x scaling. Yet the major driver of wafer cost is lithography and it seems illogical to further reduce wafer cost by doing even more of it. Specifically, the escalating wafer cost below 28nm is driven by the need of double patterning and processing of few critical layers.  Intel approach means that more layers would become critical and would need double patterning, driving the cost even higher.

2.     A $0.42 per transistor vs. $1.31 per transistor should have won Intel far more foundry business, yet their major win was a very high margin vendor – Altera, and the rumor was that Altera was planning to go back to TSMC for the 10nm node. Foundry business is extremely competitive, as the customer owns the product IP and can choose the lowest cost foundry in order to win the extremely competitive end-market such as the smart phone market.

3.     Intel’s $0.42 per transistor vs. the industry’s $1.31, combined with Intel’s command of the 86x CPU architecture, should have won Intel far more success in the Tablet market.

4.     Looking at the last 6 months of Intel stock chart (below) in comparison to TSMC, Qualcomm and Nvidia does not show any market forecast for Intel future business resulting from its ability to beat its competitors by more than 3x the manufacturing cost.

While Intel had consistently been the process technology leader, there is no special know-how or other unique advantage that could allow Intel to have 3x better costs than its competitors.

All we can do now is watch the market evolve and eventually tell us how the gap between these widely different cost estimates will be bridged.

In any event, it is clear that Intel’s solution to the escalating cost of lithography is not sustainable. Over-scaling interconnect on its own, as Intel has sometimes hinted at, is extremely problematic because interconnect RC delays are increasing exponentially with scaling. This is nicely illustrated in the Applied Materials chart below.

Source: B. Wu, A. Kumar, Applied Materials

The only visible solution for the coming decade is monolithic 3D. Quoting Geoffrey Yeap, VP of Technology at Qualcomm, at his invited paper at IEDM 2013: “Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.” And even Intel’s process guru Mark Bohr seems to have come around: “Bohr predicted that Moore's Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.” (http://www.v3.co.uk/v3-uk/news/2403113/intel-predicts-moores-law-to-last-another-10-years)

P.S.

A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program, three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies, and many other authors will be talking about their work on monolithic 3DIC and its ecosystem.

In his famous 1965 paper Cramming more components onto integrated circuits, Moore wrote: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year”. Dimensional scaling below 28nm will only increase the ‘component cost’ as described in 28nm – The Last Node of Moore's Law. While there is still a strong effort behind dimensional scaling to 14, 10 and 7nm – and possibly even beyond, a new scaling effort is emerging attempting to reduce the ‘component costs’ and increase integration by the other factors presented by Moore in his 1975 famous IEDM paper “Progress in digital integrated electronics.”. In the 1975 paper Moore updated the time scaling rate to every two years and suggested the following factors–see the following figure taken from his paper—helping to drive scaling forward:


1.     “Die size”—“larger chip area” 
2.     “Dimension”—“higher density” and “finer geometries” 
3.     “Device and circuit cleverness”

A fourth factor should have been added to the list above – improvement in manufacturing efficiency, which ensued from the increase in wafer sizes from 4” to 5” and all the way to the 12” of today.

In the past, all of these factors were aggregated into dimensional scaling as old fabs got obsolete and improvements predominantly were implemented in the new emerging node. Nowadays, as dimensional scaling has reached its diminishing returns phase, we can see a very diverse adaption of technology improvments.

In his keynote presentation at the 2014 Synopsys user group meeting, Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys’ newer tools to improve older node design effectiveness. The following is one of them

The following slide was taken from AMD’s President & CEO Dr. Lisa Su presentation in 2015 Semicon China, illustrating AMD’s improvements within the same 28nm technology node:

Even more significant would be the adoption of a breakthrough technology. A good example is the SRAM technology developed by Zeno Semiconductor, which has recently been validated on 28nm process. This new SRAM technology replaces the 6T SRAM bit cell with 1T SRAM (true SRAM - no refresh is needed) providing significant reduction of ‘component costs’ as is illustrated in the following two slides.

This new industry trend was nicely articulated by Kelvin Low of Samsung covered in “Samsung Describes Road to 14nm, FinFETs a challenge, FD-SOI an alternative.” Quoting: “Samsung spent several years developing its 14nm technology and debating which process node it would invest in after 28nm. Low expects that 28nm will still be a popular process node for years to come because of its price …The cost per transistor has increased in 14nm FinFETs and will continue to do so, Low said, so an alternative technology such as 28nm SOI is necessary.” Earlier, in the SOI Forum in its presentation “28FD-SOI: Cost effective low power solution for long lived 28nm” Samsung presented the following slide: 

“Device and circuit cleverness” as a factor would never stop but it is made of a series of individual improvements that will not be enough to sustain a long-term scaling path for the industry. An alternative long-term path will be “Die size” – “larger chip area,” which is effectively monolithic 3D, and manufacturing efficiency, which will have an important role in monolithic 3D. And who is better to call it than Mark Bohr of Intel? In a recent blog piece “Intel predicts Moore's Law to last another 10 years” Bohr is quoted predicting “that Moore's Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”   This new dimension for Moore’s Law is also illustrated in the following AMD’s Dr. Su slide:

And this is also visible in the marketplace by the industry-wide adoption of 3D NAND devices that Samsung started to mass-produce in 2014, and followed with a second generation 32 layer-stack device this year, as illustrated in their slide:

In the recent webcast “Monolithic 3D: The Most Effective Path for Future IC Scaling,” Dr. Maud Vinet of CEA Leti presented their “CoolCube” monolithic 3D technology, which was followed by our own, i.e., MonolithIC 3D, presentation. An important breakthrough presented by us was a monolithic 3D process flow that does not require changes in transistor-formation process and could be easily integrated by any fab at any process node.

Finally, I’d like to quote Mark Bohr again as we reported in our blog “Intel Calls for 3D IC”: “heterogeneous integration enabled by 3D IC is an increasingly important part of scaling". This is illustrated nicely by the following figure presented by Qualcomm in their ISPD ‘15 paper titled “3D VLSI: A Scalable Integration Beyond 2D”

In summary, the general promise of Moore’s Law is not going to end any time soon. Yet it is not going to be the simple brute-force x0.7 dimensional scaling that dominated the industry for the last 5 decades. Quoting Mark Bohr again, it “will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”

P.S.

A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies.