"Dark Silicon" is that portion of the device that needs to be shut down to avoid overheating. In a recent IEDM 2014 short course by ARM's principal engineer Greg Yeric the dark silicon was projected to be "about one-third of total area in the 20nm technology node (including 16/14nm finFETs), increasing to as much as 80% by the 5nm node," as reported by a recent Darker Silicon blog. Unlike the time that dimensional scaling could follow Dennard’s Law, it is now getting harder to thin the gate dielectric without causing extreme rise in device leakage and "as a result, while feature sizes have continued to shrink, threshold voltage has not". The following chart is from a DAC ‘13 paper titled The EDA Challenges in the Dark Silicon Era:

This dark outlook seems even darker once the cost of this silicon is taken into account. At the last SEMI Industry Strategy Symposium (ISS), as reported  in a blog titled Exponentially Rising Costs Will Bring Changes Scott McGregor, President and CEO of Broadcom presented the following charts:

This paints a very dark future for the industry: we would need to invest exponentially more, to develop designs which use more expensive transistors, of which we would need to keep dark an increasing proportion. It seems that Broadcom's CEO conclusion is unavoidable - "major changes for the semiconductor industry moving forward".

Looking for the light at the end of the tunnel, we can quote ARM's CTO, Mike Muller in Cadence's blog titled ARM Keynote: Will ‘Dark Silicon’ Derail The Mobile Internet? : "So how to light things up? Muller started with three suggestions:

• Push forward on new silicon technologies such as silicon-on-insulator (SOI),
• Use energy-efficient, high-density memories to fill some of the "dark" space.
• Combine the best process technologies to fulfill various functions with 3D ICs, which will "become a critical part of how we deliver power-efficient solutions."

Indeed just this week it was reported in EE Times that Sony Joins FDSOI Club writing: "Sony was able to cut power consumption in its GNSS chip from 10mW to 1mW".

And at IEDM 2014 we could see multiple papers on monolithic 3D technologies and memories such as R-RAM being formed as part of the Back End Of Line on top of the logic, forming effectively monolithic 3D circuits. It should be pointed out that in the general case of monolithic 3D the upper transistor layers are naturally SOI so achieving even better power efficiency by combining the SOI reduction of transistor threshold while reducing the average interconnect length, further reduces interconnect power and delay. CEA Leti had a workshop presenting their momentum on monolithic 3D through collaboration with ST Micro and IBM and supported by Qualcomm titled CoolCube™, a powerful approach for further 3D VLSI scaling. The following chart from Leti presentation illustrates the monolithic 3D build up of world wide ecosystem:

And the monolithic 3D light gets even brighter. Until recently, the path to monolithic 3D required change to the front end-of-line process. An FEOL  process change is always part of dimensional scaling, but is expensive and in most cases done only by the leading edge companies. Now, as was presented in the recent IEEE S3S ‘14 conference,  the emerging precise bonders, such as from EVG or Nikon, enable a Game Changer for Monolithic 3D  - "true monolithic 3D IC without the need for a new recipe for transistor formation. The process could be adapted by any current fab providing very competitive costs for a range of product enhancements and offer a long term road map for better offerings by scaling up."
So while traditional dimensional scaling looks darker, the emerging monolithic 3D technology is poised to bring back the light.

PS 
A good conference to learn about these emerging technologies - SOI-3D-Subthreshold - is the IEEE S3S ‘15, inSonoma, on October 5th thru 8th, 2015. 

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr Or Bach presents the article published at the IEEE S3S 2014 Conference. Authors of article: Zvi Or-Bach, Brian Cronquist, Zeev Wurman, Israel Beinglass, and Albert Henning, MonolithIC 3D Inc., San Jose, CA 95124, USA.

For many years monolithic 3D was considered untenable due to the strict 400 ºC temperature limit imposed by the aluminum or copper interconnect. This led to the focus on TSV technology as the only viable path for 3D ICs. Unfortunately, it is now clear that the TSV flow in intrinsically expensive and accordingly being perpetually pushed to the future. In the recent years pioneering efforts were published providing practical paths for monolithic 3D logic devices [1-7]. But each and every one of those presented new transistor formation flows and comes along with some other non trivial process development challenges.

Recently a new wafer bonder has been introduced to the market by EVG [8]. While prior wafer bonders had about 1 micron alignment accuracy, the newly introduced Fusion Bonder has an alignment precision of 200nm (3σ). This paper proposes a process flow that leverages such precise bonder to provide a true monolithic 3D IC without the need for a new recipe for transistor formation. The process could be adapted by any current fab providing very competitive costs for a range of product enhancements and offer a long term road map for better offerings by scaling up.


Ion-Cut - A Layer Transfer Technology


The proposed flow utilizes a well-known process for single crystal thin layer transfer known as ion-cut technology. It involves hydrogen implantation, wafer bonding, and cleaving (Fig. 1). Ion-cut is a volume production qualified process that has been used for two decades in SOI wafer manufacturing. The technology was owned exclusively by Soitec for many years, which named it smart-cutÒ, but in late 2012 Soitec's fundamental patent expired and the technology is now widely available. Our estimates suggest that with re-use of substrates, ion-cut would cost less than $60 per transferred layer. 

Monolithic 3D IC


The following flow (Fig. 2) is built on what we call 'gate replacement' [9] and leverages the precision bonder alignment accuracy. Step 1 - a 'donor' wafer will be used to process a transistor layer labeled Stratum 3. The existing front end process could be used. Alternatively for a gate-last flow, the process will hold before the gate replacement phase. Then H+ would be implanted at the desired depth (~100nm) in preparation for the layer transfer step. Step 2 - the donor wafer is bonded (oxide to oxide) to a 'carrier wafer' and ion-cut off. This bonding step does not require precise alignment. Step 3 - the carrier wafer could be now annealed to repair the potential H+ implant damage. Step 4 - the donor wafer is now processed to form Stratum 2. The existing front line process could be used including FinFET or any other available front line process. The choice of the transistor and the architecture for Strata 2 and 3 should consider the need for vertical isolation in-between them. Note that between the transferred layer and the carrier wafer there is an oxide layer which would be an excellent etch stop allowing the transfer onto the target layer without the need for ion-cut. A preferred strategy is to use Stratum 2 for the high performance circuits while Stratum 3 would be used for support of less sensitive circuits. All high temperature should be completed at this point, as in the following step interconnects are added. Step 5 - add contacts and at least one metal layer. Step 6 - bond (oxide to oxide or metal to metal) to the target wafer using the precise bonder alignment with less than 200nm misalignment.  Now grind and etch off the carrier wafer. (Not presented here are options to remove the carrier wafer for reuse.) Step 7 - the dummy gate and the gate oxide of Stratum 3 can be now replaced, and connections could be made between Stratum 2, Stratum 3 and the underneath target wafer. Alignment and via processing are just as if between conventional BEOL metal layers, as the transferred layer is very thin (~100nm).

Smart Alignment


Having a thin transferred layer allows the through layer via to be as small as a conventional BEOL interconnection via (~50 nm). Yet the 200 nm bonding alignment window would appear to require a landing pad of 200 nm by 200nm for each vertical connection. With Smart Alignment the connection is made by two perpendicular 200 nm long strips as seen in Fig 3. The vertical strip is part of the top layer of the target (bottom) wafer. After bonding, the through layer via would be aligned to the target wafer in the X direction and to the transferred layer in the Y direction as seen in Fig 4. The top connection strip could be then processed aligned to the transferred (top) layer. This alignment scheme reduces the vertical connection overhead to minimum and allows for multiple vertical connections per unit area of 200 nm x 200 nm.

Strata 2, 3 - Examples


Fig. 5 illustrates one example for circuit allocation for Stratum 2 and Stratum 3 with an intrinsic vertical isolation. For Stratum 2, most advanced devices could be used such as FinFET transistors and forming high speed logic. The SRAM for the high speed logic circuit could be placed onto the close by Stratum 3. A compelling option for the SRAM would be the use of Zeno technology [10] where a two stable states one transistor SRAM are enabled by a deep implanted back-bias. The vertical isolation is achieved by the back-bias. The FinFET transistor by design is also isolated from the substrate. This use of Stratum 2 and Stratum 3 is compelling as there is no obstruction to the memory blockages and creates a very short path for memory access. Such dual functional layer (Stratum 2 + Stratum 3) could be a product by itself offered as an add-on to many designs and 1-chip systems.         Such flows with a dual functional layer could enable many new innovative devices such as:

* An image sensor on Stratum 3 with pixel electronics on Stratum 2 could provide an unparalleled dynamic range to cameras. 

* A full redundancy layer [11] as Stratum 3 provides redundancy to Stratum 2, allowing almost unlimited logic integration on huge dies, essentially a server farm on a device.

* A configurable logic fabric as an add-on...

Monolithic 3D Cost Estimates


It is well known that high cost is the number one issue which slows down the adoption of 3D ICs based on TSV. The proposed monolithic 3D flow has the potential to overcome these barriers as it avoids use of a thick layer with lengthy etch and deposition processes. In fact, it can provide circuit fabrics for two strata for a cost that is less than one wafer substrate. The donor wafer is reusable and the cost of the first ion-cut is estimated to be less than $60 [12]. The carrier wafer could be reusable or utilize an inexpensive test wafer costing about $30. The estimated per wafer cost of precision bonding is less than $20. Other steps involved in layer transfer, cleaning, etch, etc., are estimated at about $30 total. The costs for transistor formation for Strata 2 and 3 and their associated interconnects are no different than any other circuit fabrication costs. Accordingly we estimate that the cost structure is comparable with the fabrication cost of 2D devices. Yet having the overall design built in a 3 strata fabric provides huge power, performance, and cost benefits.


Heat Removal


A point of concern is always the heat removal aspect for 3D IC. The first question relates to having more transistors in a smaller space. While more complex circuits present an ever increasing power challenge, having it built in monolithic 3D is an important part of the solution as it is well documented [13] that 80% of the power consumption is due to on-chip connectivity. The more interesting question relates to the fact that Strata 2 and 3 transistors are thermally isolated (surrounded by oxide) and without direct access to the silicon bulk for heat removal. Fig. 6 illustrates the solution of using the power delivery network for heat removal. This work was reported in IEDM 2012 [14]. Having Stratum 2 only about 1 micron away from the bulk allows a very effective heat removal path through the power delivery network. Additional supporting techniques such as heat spreaders and thermally conducting but electrically isolated contacts could also be implemented [15].

Summary


Precision Bonders combined with innovative layer transfer and alignment techniques enable a simple path to 3D IC providing the best of all worlds:

•         Vertical connectivity density comparable with the horizontal one
•         Use of existing transistor and interconnect flows
•         Compatible with advanced and older fabs
•         Low cost competitive with 2D IC cost structure 
•         Heterogonous integration - Fab lines, process nodes, device materials, processes
•         Parallel and Sequential process (short TAT)
•         Enables many new classes of device and systems untenable with 2D IC
•          Multiple paths for cost reduction that were untenable with 2D IC
  

        It seems that the new form of 3D IC combines the best of TSV with monolithic 3D IC to offer the most attractive path to keep Moore's Law, while opening an unparalleled path for all fabs to keep enhancing their product range using their existing equipment and flows.

                And yes, this opens a new horizon for the semiconductor industry.

References

[1] Z. Or-Bach, IEEE 3DIC Conference, 2013. 
[2] P. Batude et al., Proceedings of the Electro-Chemical Society (ECS) spring meeting, Vol. 16, pp.47 (2008) 
[3] D. C. Sekar, IEEE 3DIC Conference, 2012. 
[4] B. Rajendran, IEEE 3DIC Conference, 2013. 
[5] Chih-Chao Yang 29.6 IEDM 2013 
[6] Chang-Hong Shen pp. 262 IEDM 2013 
[7] Sang-Yun Lee, US Patent 7,470,142 
[8] Thomas Uhrmann et al., Solid State Technology, pp.14, July 2014 
[9] http://www.monolithic3d.com /hkmg.html 
[10] Yuniarto Widjaja US Patent 8,514,623 
[11] http://www.monolithic3d.com/ultra-large-integration---redundancy-and-repair.html 
[12] http://www.monolithic3d.com/blog/how-much-does-ion-cut-cost1 
[13] L. Chang, IBM Short Course, IEDM 2012 
[14] Hai Wei, et al., IEDM 2012 
[15] D. C. Sekar US Patent 8,686,428.

Presentation:
Precision Bonders - A Game Changer for Monolithic 3D, IEEE S3S 2014, October 2014. 

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the emergence of monolithic 3D technology in the near future.

The coming 2014 IEEE S3S conference (October 6-9) is first one to focus on the emergence of monolithic 3D technology. It is fitting that it would be the forum at which a key decisive breakthrough for monolithic 3D IC ("M3DI") technology will be presented. This game changing breakthrough is the first ever monolithic 3D flow that allows a fab to build a monolithic 3D integrated device while using the fab’s existing transistor process flow, without the need to develop and qualify new transistors and a new transistor formation flow.

Recent blogs such as Established Nodes Getting New Attention and Moore's Lag Shifts Paradigm of Semi Industry have articulated the building up of interest in SOI, Sub-threshold and 3D IC technologies. The IEEE S3S is the conference to learn and get updated on these technologies and M3DI is that newest part integrated into the conference. The 3D part of S3S 2014 will have a full day of tutorial presentations by leading researchers in the space, a full session of invited papers, and will conclude with a session dedicated to discussing the most recent breakthroughs in the field.

The M3DI short course will cover alternative process flows that enable M3DI, discuss the challenges and solutions to removal of the operating heat of monolithic 3D stacks, and describe the range of powerful advantages provided by M3DI. Subsequently, Prof. Sung Kyu Lim of Georgia Tech will cover EDA for M3DI. This will be followed by broad coverage of M3DI for memory applications by two leading experts in the field, Akihiro Nitayama of Toshiba/Tokohu University and Deepak Sekar of Rambus. M3DI provides unparalleled heterogeneous integration options which will be covered by Prof. Eugene Fitzgerald of MIT and SMART Lee Institute of Singapore describing the integration of silicon with other crystals for electro-optic device integration. The short course will conclude with Prof. Philip Wong of Stanford, who leads research efforts to integrate silicon with carbon nanotube and advanced 2D transistors layered with memory such as STT-MRAM and RRAM.

In the special invited 3D Hot Topics session we expect to get a full spectrum of the latest progress in the field. Particularly worth noting is the recent progress on the work done by CEA Leti with involvement of ST Micro, IBM and supported by Qualcomm. This work shows both a practical path to monolithic 3D IC and cost analysis of the monolithic 3D advantages. The following chart illustrates the reasons for the high interest in the technology.

And then there is a great dessert to this 3D feast. On Thursday afternoon, in the 3D New Developments session, a game changing breakthrough technology will be presented. Leveraging the breakthrough progress in wafer bonding technology, presenting for the first time ever a monolithic 3D flow using existing fab transistor process. Any fab could utilize this breakthrough to provide far better products at minimum capital and R&D investment. This game changing flow removes the historical differentiation between sequential and parallel 3D, and should significantly reduce the time for monolithic 3D adoption throughout the semiconductor industry.

For a postprandial enjoyment, CEA Leti will present in the Late News session a fully constructed M3DI SOI device, and IBM will present its Multi Stacked Memory Wafer technology.

More information is available on the conference site: S3S Conference 2014

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the paradigm shift in the semiconductor industry. 

In our blog 28nm – The Last Node of Moore's Law, we had pointed out that the change has happened, and it is no longer a matter of forecast or prediction. In this blog we will start by reviewing some of what has transpired since that blog, and then focus on the ensuing paradigm shift in the semiconductor industry.

The following chart was presented in the IEEE IITC workshop by Globalfoundries. It illustrates the cost impact of the double patterning required for scaling below 28/22 nm. 

Soon after Rick Merritt’s coverage of Semicon West - 13 Things I Heard at Semicon West -- Rick wrote: "Moore's Law has definitely slowed" quoting Gartner semiconductor analyst Bob Johnson."No matter what Intel says, Moore's Law is slowing down" and, Bob added, "Only a few high-volume, high-performance apps can justify 20 nm and beyond."

Soon thereafter Peter Singer, in a blog post about the ConFab 2014 –  Can we take cost out of technology scaling? -- quotes Dr. Gary Patton, VP of semiconductor research and development center at IBM: “The challenge we’re facing now is two fold. Number one, we’re struggling to get that 0.7X linear scaling. It might be about 0.8X. And we’re adding a lot more complexity, especially when you adding double and triple patterning."

And now, in early August we finaly got more information from Intel about their up coming 14nm. In our blog Intel vs. Intel we articulate that Intel’s numbers indicate that Moore’s Law had stopped at 28/22 nm both in terms of the bring-up time it takes and the cost of new technology nodes.

It is hard to accept that a trend that has held strong for 50 years, and which kept going many years after multiple predictions of its imminent demise, has really stopped. And it is even harder as we watch the huge effort of bringing up the 14 nm and 10 nm nodes. Yet it seems that everybody should agree that the semiconductor industry is now going through a paradigm shift and for most designs 28nm is, at least for some time, the last node of Moore's Law.

The following charts are well known and present the reason for that change.

It shows that the design cost increases by more than $100M from 32nm to 16nm. If we assume a die cost of $10 at 32 nm and we assume that the traditional cost reduction per node still holds, then we would need a volume of more than 20 million units just to break even. If one also considers the risk associated which such a design, it would actually require more than 100 million units, or at least $1B of market, for such device to justify the investment. Clearly, very few designs have the market for 100 million units or $1B market.
The following chart by IBS presents the past trend in design starts per node. Clearly, most new designs are still done in 130 nm while the node with the fastest ramp-up is 65 nm.

The forcast for 2016 at Semiconductor Technology Nodes – History, Trends and Forecast is illustrated in the following pie chart:

Yet again it indicates a very slow shift to more advanced nodes, and the expectationis that even in 2016 most new designs will still be done in 130nm.

This is clearly a paradigm shift in the industry, and the industry is responding accordingly.

Just prior to 2014 Semicon West, we have seen the conclusions of the SEMI’s World Fab Forecast -- Technology Node Transitions Slowing Below 32 nm. The Forecast uses a bottom-up methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. The chart below illustrates this new paradigm.

The report states: “The cost per wafer has become an increasing concern below the 32nm node.   The expected cost reduction benefit of production at smaller nodes is diminishing and is not keeping pace with the scaling benefits in many cases.  This has widespread and fundamental implications for an industry long following the cadences of Moore’s Law… These may be contributing factors as to why some volume fabs are exhibiting a lag in beginning production of a new technology node.  Now evident quantitatively for the first time, there is evidence of a clear slowdown in volume production scaling of leading technology node transitions.” (emphasis added)

This was followed by another EE Times article – Silicon Highway Narrows, Twists: “Most foundries have yet to start buying the capital equipment needed for the 14/16 nm node, which for many will be the first to support FinFETs, says Trafas of KLA-Tencor. Gear companies hope the orders start coming in the fall…Indeed, he says, one of the big questions many capital equipment execs will bring to this year's Semicon West event on July 7 is, "When will the 16/14 nm investments begin?"

In the same vein, Ed Sperling continued in Established Nodes Getting New Attention: "Work is under way to improve energy efficiency and boost performance without relying on multi-patterning or finFETs. As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors."

And a week later Samuel Wang, an analyst with Gartner, in Who’s Winning The FinFET Foundry Race? wrote: “Short-term, during the first two years of finFET production, there is no need for more than 50,000 wafers a month capacity from all foundries to satisfy the market demand for finFETs, …In the long run and before 2018, there is no need to have more than 250K wafers a month capacity to support the market demand for finFETs."    The EDA industry also is recognizing this paradigm shift. Dr. Aart de Geus in his keynote to the 2014 Synopsys User Group titled Designing Change Into Semiconductor Techonomics, recognized this shift with a series of slides articulating how EDA tools that were developed to support the new technology nodes could also benefit design efforts of old nodes:  

The IP industry is recognizing this paradigm shift as well, visible in IP Reaches Back To Established Nodes: "As SoC developers shift backward to established nodes, steps can be taken to improve the IP’s functionality. Driven by the IoT and wearable market opportunity, SoC developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality."

There also a clear effort to add value and innovation to older nodes by incorporating technology such as SOI and low Vt, known as sub-threshold designs. Most notable was the recent Samsung announcement of licensing FD-SOI from ST Micro for the established node of 28 nm. Some quotes from the articles above illustrate this trend:

* Krishna Balachandran, product marketing director for low power at Cadence. “Threshold voltage manipulation like forward biasing has been selectively used to speed up critical portions of the IP at the expense of increased leakage that is restricted to those sections of the IP without significant overall impact.”

* ARM Fellow Rob Aitken said energy savings are significant using the same exact processors differently. Moreover, it’s most effective at established process geometries where there are no finFETs. But it isn’t a simple process. (For a deeper understanding of this subject, click here). “We can get 4X to 6X improvements in energy,” said Aitken. “That doesn’t come for free, because we have to make some design changes to allow the design to operate down at this low energy point. But if we do this wrong, the overhead we have to add to get these savings is more than you get in terms of a benefit.”

* Mary Ann White, director of product marketing for the galaxy design platform at Synopsys: "Body biasing is another technique that is being recycled. It entered the picture at 90nm, when design teams found they could reduce leakage by as much as 30%. Even at 45/40nm, savings were in the 20% to 25% range. But at 28nm, the benefit for bulk CMOS dropped to as low as 2%,...When you use biasing, you are using extra tracks and extra resources, which may include one or two extra rails,” said White. “But the benefit was falling off at 28nm using planar CMOS. Interest is picking up again with FD-SOI. What’s interesting about this is we used to insert biasing at the back end, where you require a bulk n-well or p-well pin. But recently we’ve had a request to add that capability into UPF. We rolled that out with skepticism on our part, but we’ve been getting a lot of interest. If you’re adding 5% area for better power, it’s worth it.” (See related discussion.)

This paradigm shift could be a real blessing to the industry. The escalating costs drove out VCs from investing in semiconductor start-ups, drastically narrowed the number of vendors and the number of advanced new designs. It left little room for innovation or anything other than rushing to the next technology node. Now it seems that a whole new industry dynamic is taking place, innovation is being embraced, new markets are being explored, and hopefully we will see the return of VCs with the increase of semiconductor vendors and technologies.

This is also the time to pay increased attention to semiconductor technologies that could offer better intrinsic devices without traditional dimensional scaling. Most notable among those would be, SOI, Monolithic 3D, and Sub-threshold design. The 2014 S3S Conference scheduled for October 6-9, 2014, at the Westin San Francisco Airport would be a great opportunity to learn more about those technologies as it provides the latest research results along with workshops, tutorials and range of invited papers. The conference advance program is now available at < http://s3sconference.org/program/ >. It looks now to be the one conference that active members of the semiconductor industry should not miss. 

Along with many in the industry, we were pleased to see the release of Intel's 14 nm technical information on Aug. 11 - Intel Outlines 14nm, Broadwell. It does look like after an extended delay the 14 nm is coming and with it some clarity about the Intel 14 nm technology. Clearly this recent 14 nm information release is being presented by Intel to continue the historical trend of cost reduction and dimensional scaling. Undoubtedly, Intel’s 14 nm technology is a significant technological achievement and deserves full respect and appreciation. Yet, if one takes a closer look at this information, and especially with respect to prior information provided by Intel, there is room for some clarification.  

The above EE Times article provides the following numbers released by Intel on August 11:
"Compared to Intel's 22nm process, it will have:

• 42nm fin pitch, down .70x
• 70nm gate pitch, down .78x
• 52nm interconnect pitch down .65x
• 42nm high fins, up from 34nm
• a 0.0588 micron2 SRAM cell, down .54x

~0.53 area scaling compared to 22nm"
Let’s review the SRAM cell size of 0.0588µm². Yes, it is the smallest published size for a SRAM bitcell we have seen so far. Yet in our blog Intel vs. TSMC: An Update we wrote:  "Accordingly, the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² =0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm, it should be about 0.03 sq. micron or even smaller."

From Intel’s 2012 information release:

In the following table we calculated the expected bitcell size for 14nm according to simple dimensional scaling rules based on each of the bitcell sizes for each of the technology nodes in the above 2012 chart:

The above table indicates that SRAM bitcell scaling has been a challenge for some time but at 14 nm it broke totally away!

The recent Intel presentation argues for the continuation of historical scaling cost reduction to the 14 nm node as illustrated in the following Intel slide:

The graph in the middle shows the exponential increase in wafer cost with scaling; however, the argument made is that the more than 2X increase in transistor density compensates for the increase in wafer cost, resulting with the rightmost chart showing a consistent reduction in cost per transistor.

But the following Intel chart does not show a better than 2X density increase from 22nm to 14nm:

Actually the basic transistor gate pitch indicates only a x1.64 increase in transistor density.

As well, this is before accounting for the increase in RC associated with the narrower metal lines. This would require insertion of many more buffers and repeaters, further reducing the effective density increase.

Furthermore, back to the SRAM bitcell. The announced size for the Intel 14nm bitcell as presented above is not going to help offset the increase in wafer cost.

So it seems this would be a subject matter for more comments and blogs. However, I see no reasons to change my prior statements published in the EE Time blog titled: 28nm – The Last Node of Moore's Law.

Hughes Metras, Leti’s VP of Strategic Partnerships North America, introduced the lead talk at their SemiconWest 2014 Leti Day about monolithic 3D technology as the “solution for scaling.” Hughes presented the Leti device technology roadmap which showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to well past 5nm. Here’s the important piece of that roadmap, which highlights the partnership with Qualcomm (ST and IBM helped with some of the work as well):

The lead talk was given by device scientist Olivier Faynot, Leti’s Device Department Director.  He titled his talk “M3D, a disruptive approach for further scaling,” and began with why the industry needs a solution for scaling.

Most in the industry are in agreement that scaling past the 22nm node, while still quite technically feasible, has priced itself out of most markets. Olivier discussed the what (transistor costs are no longer decreasing) and the why (litho cost escalation and connectivity inefficiencies of energy and delay). And then he made the statement: “if we just keep the current (2Xnm) technology, we can go farther in cost scaling.” [note: see the following blogs and comments for more info on this crucial topic:  Tech Design Forums summary "3D and EDA need to make up for Moore’s Law, says Qualcomm" and Zvi-Or-Bach’s EETimes blogs Qualcomm Calls for Monolithic 3D IC and  28nm - The Last Node of Moore's Law.]

Oliver showed a summary of a DAC2014 paper and a Qualcomm/GeorgiaTech DAC2014 paper Power/Performance/Area analysis of M3D for an FPGA:

The solution is to build the stack sequentially, in a monolithic fashion. Olivier described their monolithic 3D, or sequential 3D, process flow where the lower-level (first layer) of transistors and its interconnect are conventionally made, then inter-level metal is crafted to help the vertical interconnection, and then a second layer of monocrystalline silicon is layer transferred and oxide-oxide low temperature bonded to the top of the inter-level metal dielectric. This is a blanket layer so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin (10-200nm final), so that direct alignment thru that thin layer to the lower level alignment marks can be made with conventional equipment and achieve conventional alignment tolerances (single digit nanometers).

Now upper-level transistors are formed utilizing SPER (Solid Phase Epitaxial Regrow) for junction doping at 475-600°C and other lower (<400°C) temperature processing for gate stacks, etc. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. Note that the lower level transistor Ni salicides are stabilized with platinum co-deposition and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.

Oliver also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. He called the laser (pulsed and short wavelength) option of solving the thermal challenge of monolithic 3D as the “crème brûlée” of methods and they were ‘seeing good results.’ Hopefully we will see published data soon. For more information on SPER and laser processing please see my recent blog Monolithic 3DIC: Overcoming silicon defects.

Oliver was also asked in the Q&A if stress was a big issue. He replied that stress was not an issue, rather, the biggest challenges were integration ones (how to form a low temp top transistor, stability of the local interconnect level, and the bottom transistor salicide stability). Olivier was asked in the Q&A what the observed performance differences were between the upper-level and lower-level transistors. He replied” Currently we are achieving 95% (of the lower for the upper). We believe we can make 100%.”

Leti has a 14nmPDK ready to go for those who want to design a test circuit in their monolithic 3D flow. They have ELDO, HSPICE, Virtusoso, Calibre, StarRC, etc. files available.

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December 2013, Leti signed an agreement to work with Qualcomm – Qualcomm to Evaluate Leti’s Non-TSV 3D Process. ST and IBM have also been working with Leti in various aspects, for example, IBM & Leti used COMPOSE3 to simulate a monolithic InGaAs nFET monolithically over a SiGe pFET on SOI.

CEA-Leti has been busy working on processing flows to enable monolithic 3D devices since before 2009. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper entitled, “Advances in 3D CMOS Sequential Integration,” where she showed results for a sequentially processed P over N (no metal between transistors layers) testchip Batude’s 2011 IEDM paper showed a 50nm 3D sequential structure on 10nm channel silicon:

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications, both parallel and monolithic, with an inauguration event in January 2011. As well, back in December 2013, Soitec and CEA renewed their long-standing partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. I would like to invite you to the IEEE S3S Conference: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference will be held October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

See you there!

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the shift in semi equipment, a paradigm confirmed lately.

Our blog Paradigm shift: Semi equipment tells the future, was focused on the quote: “Now more money is spent on upgrading existing facilities, while new capacity additions are occurring at a lower pace.” And now, just prior to Semicon West, we have the conclusion of the recent SEMI’s World Fab Forecast — Technology Node Transitions Slowing Below 32 nm. The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. The following chart illustrates this new paradigm:

The report states: “The cost per wafer has become an increasing concern below the 32nm node.   The expected cost reduction benefit of production at smaller nodes is diminishing and is not keeping pace with the scaling benefits in many cases.  This has widespread and fundamental implications for an industry long following the cadences of Moore’s Law… These may be contributing factors as to why some volume fabs are exhibiting a lag in beginning production of new technology node.  Now evident quantitatively for the first time, there is evidence of a clear slowdown in volume production scaling of leading technology node transitions.” (emphasis added)

It is fitting to point to the comment made to EE Times coverage on Semicon West – 13 Things I Heard at Semicon West: “No matter what Intel says, Moore’s Law is slowing down,” said Bob Johnson, a semiconductor analyst for Gartner. “Only a few high-volume, high-performance apps can justify 20 nm and beyond.” He sees problems ahead for logic chips in general,” and to follow with quotes from another EE Times article – Silicon Highway Narrows, Twists: “Most foundries have yet to start buying the capital equipment needed for the 14/16 nm node, which for many will be the first to support FinFETs, says Trafas of KLA-Tencor. Gear companies hope the orders start coming in the fall…Indeed, he says, one of the big questions many capital equipment execs will bring to this year’s Semicon West event on July 7 is, “When will the 16/14 nm investments begin?”

Since the 65 nm node, escalating costs of fab and process technology development and design, as illustrated in the chart below, put a huge pressure on the industry.

These escalating costs drove consolidation in the industry, cutting down to a handful the vendors who are still pursuing the leading edge.

At the recent (2014) SST ConFab in Las Vegas Bill McClean shared his annual report on Major trends shaping the future IC Industry. Bill reports: “Over the last two decades, the percentage of capex being spent by the top 5 has steadily increased to its current 70% with the big three of Samsung, Intel and TSMC being responsible for over 50%.” This is illustrated by the following chart.

Clearly the escalating costs drove out most but the largest vendor, but now we are facing the ”second punch” – the diminishing returns.

In the recent ITC conference Harry J. Levinson of GlobalFoundries in his talk: Lithography Issues for High Volume Manufacturing” presented the following chart:

The dramatic increase of lithography cost eats away the historical transistor cost reduction resulting from reduced dimensions, as we reported in our blog Qualcomm: Scaling down is not cost-economic anymore – so we are looking at true monolithic 3D. Quoting Qualcomm “One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down it’s not cost-economic anymore. It’s creating a big problem for us.” Accordingly we detailed in our blog that Moore’s Law has stopped at 28nmand following nodes would not provide lower transistor cost, and for most application will result in higher SoC costs.

We should not be surprised that the production ramp up below 28 nm is extremely slow. There is too much money involved to put it into the wrong place.

Going back to the SEMI World Fab Forecast, the authors ask “What’s next?” and respond: “Many in our industry are grappling with what to do as they have perceived the coming slowdown in technology node transitions.  IC manufacturers are now increasingly looking outside of conventional lithography and wafer size scaling approaches to pick up the pace of cost reduction while increasing transistor density and performance. Using memory as an example, to cope with increasing challenges in continuing to scale 2D, memory companies are looking into 3D.”

So the memory vendors already started shifting their Capex budget to scaling up with 3D NAND, instead of scaling to smaller dimension. Recently Qualcomm announced their collaboration with SMIC – China’s SMIC-Qualcomm 28-nm Deal: Why Now? – indicating more capacity build-up for 28 nm with looking forward to scaling up with monolithic 3D for logic as well. Quoting: ”Going forward, SMIC will also extend its technology offerings on 3DIC and RF front-end wafer manufacturing in support of Qualcomm”.

It is clear now that we are seeing a paradigm shift in the semiconductor equipment industry. After many decades of relentless dimensional scaling every two years, there is a change coming and we see a lower rate of dimensional scaling and exploration of other paths, to keep industry’s march on. We do believe that the next few decades will be about scaling with 3D Integration and we are pleased to see many others thinking the same.

The 2014 S3S Conference is scheduled for October 6-9, 2014, at the Westin San Francisco Airport, and would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about monolithic 3d technology for future scaling.

At the CEA-Leti Day July 8 during Semicon West, Hughes Metras, Leti's vice president of strategic partnerships for North America, introduced the lead talk about monolithic 3D technology as the "solution for scaling." The Leti device technology roadmap that Hughes presented showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to past 5 nm.Olivier Faynot, Leti's device department director and a well-known device scientist (with more than 170 papers/publications), entitled his talk "M3D, a disruptive approach for further scaling" and started with why the industry needs such a solution.

The majority of people in the industry agree that scaling past the 22nm node, though still quite technically feasible, has priced itself out of most markets. Faynot discussed the "what" (transistor costs are no longer decreasing) and the "why" (litho cost escalation and connectivity inefficiencies of energy and delay). Then he said, "If we just keep the current [2Xnm] technology, we can go farther in cost scaling."

Tech Design Forum's summary of a Qualcomm executive's DAC 2014 keynote offers more information on this crucial topic. So do a pair of EE Times blogs by Zvi Or-Bach.

The solution is to build the stack sequentially in a monolithic fashion. (See Monolithic 3D IC Technologies.) Faynot described a process flow wherein the lower level (first layer) of transistors and its interconnect are made conventionally, some interlevel metal is crafted to help the vertical interconnection, and a second layer of monocrystalline silicon is layer transferred and oxide-oxide bonded at low temperature to the top of the interlevel metal dielectric. This is a blanket layer, so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin, so that direct alignment to the lower-level alignment marks can be made with conventional equipment, and conventional alignment tolerances (single-digit nanometers) can be achieved.

Upper-level transistors are formed utilizing solid-phase epitaxial regrow (SPER) for junction doping at 475-600°C and lower-temperature processing (less than 400°C) for things like gate stacks. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. (Note that the lower-level transistor salicides are stabilized with platinum and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.)

In the Q&A session, Faynot was asked what the observed performance differences were between the upper-level and lower-level transistors. "Currently, we are achieving 95%" of the lower for the upper, he said. "We believe we can make 100%."

He also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. The laser option of solving the thermal challenge of monolithic 3D is the "crème brûlée" of methods, and Leti is "seeing good results." Hopefully, we will see published data soon. My recent Solid State Technology blog offers more information on SPER and laser processing.

Faynot was also asked if stress is a big issue. He replied that stress is not an issue. Rather, the biggest challenges are integration ones.

Leti has a PDK ready to go for those who want to design a test circuit in their monolithic 3D flow. The company has ELDO, HSPICE, Calibre, StarRC, and other files available, and it has said that monolithic 3D offers savings of at least 55% on area, 23% on performance, and 25% on power over 2D.

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December, Leti signed an agreement to work with Qualcomm. ST and IBM have also been working with Leti in various areas.

Since before 2009, CEA-Leti has been busy working on processing flows to enable monolithic 3D devices. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper "Advances in 3D CMOS Sequential Integration" (subscription required). In that paper, she and her co-authors showed results for a sequentially processed P over N (no metal between transistor layers) test chip. In an IEDM 2011 paper, she and her colleagues showed a 50nm 3D sequential structure on 10nm channel silicon, illustrated below.

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications -- both parallel and monolithic -- with an inauguration event in January 2011. In December 2013, Soitec and CEA renewed their longstanding partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference is scheduled for Oct. 6-9 at the Westin San Francisco Airport. CEA-Leti will present its work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon. With five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories, this would be a great opportunity to learn more about monolithic 3D technology.

-- Brian Cronquist is vice president of technology and IP at MonolithIC 3D Inc. He has 35 years of semiconductor industry experience as senior director of technology development and foundry at the nonvolatile FPGA provider Actel (now Microsemi), starting and building Chartered Semiconductor-Singapore (now GlobalFoundries), running startup wafer fab engineering teams at Sierra Semiconductor (now PMC-Sierra), and developing process technology at AMI and Synertek/Honeywell. He has published more than 100 technical papers in the fields of semiconductor microelectronic radiation effects and hardening, as well as new 3D-IC, logic, antifuse, and flash processes, devices, and reliability. He holds more than 60 issued/pending patents.

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about overcoming silicon defects in monolithic 3d.

As dimensional scaling has reached the diminishing return era there is a buildup of interest in monolithic 3D as an alternative path forward. Both memory and logic vendors are moving to monolithic 3D. The memory vendors are in transition to 3D NAND and Samsung has already announced mass production of their V-NAND. BeSang has been working in monolithic 3D memory for many years and has recently signed a license agreement with SK Hynix. And now, in the logic arena, Qualcomm has voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling.” The reason is economic: … “although we are still scaling down, it’s not cost-economic anymore” (Karim Arabi, DAC 2014).

A key aspect of monolithic 3D is engineering the second layer to be especially thin, on the order of 100nm or less. This provides for tiny (10s of nm diameter) vertical connections which are dense, manufacturable, and stress-free.  They can be manufactured with well understood processing as these vertical connections would look very much like the metal to metal vias that the industry has been making for decades. This avoids the 10+ micron sized TSVs of parallel 3D and their associated reliability hazards, process cost, Keep Out Zones, and ‘newness risk’.

When performance is important, single crystal silicon based transistors are the way to go for stacked layers. So far, it seems that the best technique to form such thin mono-crystal layers with the required thickness control is to use the volume production and well proven ion-cut process. Many of the high performance monolithic 3D process flows utilize ion-cut techniques, sometimes called ‘Smart-Cut’.

However, use of ion-cut creates a small number of crystal defects in the very thin single crystal layer-transferred film. I’ll talk about some techniques that may be employed to solve this but, first, let’s explore why defects are created in the ion-cut process.

The high dosage of ions used in the process creates damage to the silicon lattice at, and near, the ion-stopping depth, such that the lattice becomes brittle there; hence, can be ‘cut’ or ‘exfoliated’ with a force (e.g., knife, water jet) or thermal anneal. After separation of the layer to be transferred from the donor substrate, this ‘donor layer’ will still have some of the silicon lattice damage from the embrittlement on one surface, and may also have some damage from the splitting process itself. Soitec, in the manufacture of SOI wafers, utilizes 1100-1200°C thermal anneals (both oxidizing and non-oxidizing) in combination with chemical-mechanical polishing (CMP) to repair the crystalline damage, as part of its SmartCut (ion-cut) process. However, these damage repair anneals are not compatible with the commonly used low melting point/hi-diffusivity interconnect metals like copper or aluminum of the lower device layer in a 3D stack. BeSang has a nice tutorial video explaining this on their website. Here’s a snapshot:

Further, the passage of the ions used in the ion-cut process creates a lower level of damage to the silicon lattice of the bulk of the to-be-transferred donor layer as the ions pass thru the lattice. This bulk lattice damage can cause junction leakage, and lower the performance of devices. Annealing this type of lattice damage requires temperatures of about 600°C or greater, which – again – is incompatible with the commonly used interconnect metals of the lower device layers in a 3D stack.

Now let’s look at two silicon device proven methods that are available to overcome the ion-cut induced defects and can be applied to the ion-cut layer transfer for monolithic 3D devices and  structures.

Radu et al. of Soitec, in U.S. Patent Application Publication 2013/0026663, describe a method for curing defects associated with ion-cut implantation by a CMP and then a laser anneal of the transferred singe crystal silicon layer.

Singe crystal silicon donor wafer 1 is ion-implanted with a heavy dose of hydrogen or helium ions to create a brittle region 11 as shown in Fig. 1A. Then the donor wafer is flipped over and bonded to the top of a receiver substrate 2 that may have transistors and interconnect metallization 20, shown in Fig. 1B. Layer 3 is a low thermal conductivity or thermal insulating layer that will help thermally protect the transistors and interconnect metallization 20 of substrate 2.

Fracturing along the brittle region 11 may be done with any number of techniques, such as mechanical knife, water or gas jet, etc., leaving behind transferred silicon layer 10. The transferred layer surface 12 may be CMP’d to remove the majority of the roughness and surface defects, resulting in Fig. 1C.

However, there are still bulk lattice damage centers in transferred silicon layer 10. Radu et al. takes care of them thermally by applying pulses of electromagnetic energy. Specifically mentioned are the pulsed lasers of Excico and JPSA.

The wavelength of the irradiation is chosen such that the majority of the pulsed energy is absorbed in transferred layer 10. The low thermal conductivity or thermal insulating layer 3 minimizes the thermal diffusion from the heated transferred layer 10 to the interconnect metallization and must be designed properly to handle the thermal pulse of the layer above. Temperatures high enough to cure the ion-cut induced defects and reactivate any ion-cut deactivated dopants in transferred layer 10 can be achieved. For example, as Figs. 5A and B show, the transferred thin (0.8um in this case) silicon layer (a) may achieve a temperature well above 1000°C from the laser pulse, and the interface (b) between substrate 2 and thermal insulating layer 3 will stay well below 400°C.

Fig. 5A shows the JPSA laser at 193nm and 20ns pulse FWHM (Full-Width Half-Max) and Fig. 5B shows the Excico laser at 308nm and 160ns pulse FWHM.

We have also published work on laser annealing at 2013 IEEE 3DIC and 2013 IEEE S3S Conferences showing how scaling trends can make monolithic 3D practical and the substantial design space of the laser wavelength/energy/pulse width, top layer thickness, and shielding/thermal protection layers which can make single crystal monolithic 3D possible.

Clearly, stacking of ultra-thin layers of defect free single crystal silicon can be readily accomplished and the tools to realize this are available from at least two vendors.

At ESSDERC (43rd Solid State Device Research Conference) in September of 2013, Radu et al. in collaboration with CEA-Leti, presented a different way of obtaining low defect single crystal silicon stacks. Low temperature Solid Phase Epitaxial Re-grow (SPER) is combined with ion-cut to demonstrate defect free diodes with processing temperatures less than 500°C.

SPER utilizes a small amount of crystalline silicon as a template to re-crystallize an amorphous silicon layer at temperatures just above 475°C and can be used to activate dopants above the solubility limit.

SPER can be combined with low temperature ion-cut (SmartCut) and bonding techniques to obtain defect free single crystal devices. Donor wafer doped silicon is amorphized before bonding and ion-cut implanted to create the brittle zone, flipped and bonded to the handle, SPER processed, and then thinned to remove the End Of Range defects.

No crystalline defects were seen utilizing the usual physical means:

However, the tougher test to satisfy is always the electrical one. Radu showed excellent diode characteristics, resistivity, concentration and mobility recovery. Here are some of their diode I(V) curves:

I would not be surprised if demonstration of transistors is published in the near future.

So, hopefully I have given you at taste of how ready an important piece of the monolithic 3D puzzle is to delivering on its promises. Back in December 2013, Soitec and CEA-Leti renewed their long-standing partnership for five additional years. I think it is safe to say that more will be coming soon.

Give me a call or email if you want to talk more…

Monolithic 3D moving forward for SoC and logic devices. The latest news in the semiconductor industry reveals an important strategic relationship between Qualcomm Technologies and Semiconductor Manufacturing International Corporation SMIC. The latest is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in mainland China. "SMIC is further strengthening its strategic relationship with Qualcomm Technologies. SMIC will work with Qualcomm Technologies in bringing new 28nm design-ins and products for the growing mobile communication industry. Going forward, SMIC will also extend its technology offerings on 3D IC and RF front-end wafer manufacturing in support of Qualcomm Technologies". As Zvi Or-Bach, Presindet and CEO of MonolithIC 3D Inc. recently reported in our blog: "Qualcomm Calls for Monolithic 3D IC", first developing EDA with help of Georgia Tech., than support the process development at CEA Leti, and now setting up volume production with SMIC. This is the first announcement of moving to monolithic 3D for SoC and logic devices after Samsung already reported mass production of for monolithic 3D in first 3D vertical NAND flash.

Source:

- SMIC and Qualcomm Collaborate on 28nm Wafer Production in China – Solid State Magazine [http://electroiq.com/blog/2014/07/smic-and-qualcomm-collaborate-on-28nm-wafer-production-in-china/];

- China's SMIC-Qualcomm 28-nm Deal: Why Now? - EE Times [http://www.eetimes.com/document.asp?doc_id=1322988&piddl_msgid=306046#msg_306046];