Algorithm to combine all the models and design a 2D or 3D-IC
The key challenge with combining all the models shown thus far is:
1. Input: The user inputs the parameters of the system being modeled. The wire length distribution is obtained from these parameters and logic gate sizing is done. An initial chip power estimate is set (as 100W, say) and the number of repeaters is set as 0.
2. Local interconnect modeling: Local wire pitch is set as 2F. The longest wire routed in local interconnect levels is determined using equations shown in the local interconnect modeling page.
3. Arrangement of wires without repeaters: The multilevel interconnect network is obtained without repeaters using equations (1) and (2) of the intermediate and semi-global interconnect design page.
4. Global interconnect modeling: A top-down process of global interconnect pitch selection and repeater insertion then begins. Global wire pitch is constrained to be the value found from the global interconnect design page. Repeaters are inserted into these global signal wires, and the shortest signal wire routed in global wire levels is found.
5. Assignment of wires with repeaters: Based on the length of shortest global signal wire, wires with repeaters are assigned to the pair of metal levels below the global wire levels, based on equations (1) and (3) of the intermediate and semi-global interconnects page. This keeps continuing for other metal levels till one runs out of die area for placing more repeaters or till the addition of repeaters does not improve wire delay.
6. Power computation and iteration: Once repeaters are assigned, the total chip power is calculated. If the total power calculated is different from the power estimate used for designing power distribution wiring, IntSim sets Estimated Power = 0.5*(Old estimated power + Calculated Power) and goes back to Step 2. For the next iteration, the number of repeaters is set as the value calculated in Step 5.
7. Data output: When the simulation converges, the total number of wire levels, pitches of each wire level and a power estimate are output.
- The design of power interconnects and their area allocation depends on the chip power. However, chip power is not known until repeaters are designed in the multilevel wiring network, especially in sub-90nm chips where repeaters consume a significant fraction of total power.
- Design of the interconnect stack needs some knowledge of via blockage caused by repeaters.
1. Input: The user inputs the parameters of the system being modeled. The wire length distribution is obtained from these parameters and logic gate sizing is done. An initial chip power estimate is set (as 100W, say) and the number of repeaters is set as 0.
2. Local interconnect modeling: Local wire pitch is set as 2F. The longest wire routed in local interconnect levels is determined using equations shown in the local interconnect modeling page.
3. Arrangement of wires without repeaters: The multilevel interconnect network is obtained without repeaters using equations (1) and (2) of the intermediate and semi-global interconnect design page.
4. Global interconnect modeling: A top-down process of global interconnect pitch selection and repeater insertion then begins. Global wire pitch is constrained to be the value found from the global interconnect design page. Repeaters are inserted into these global signal wires, and the shortest signal wire routed in global wire levels is found.
5. Assignment of wires with repeaters: Based on the length of shortest global signal wire, wires with repeaters are assigned to the pair of metal levels below the global wire levels, based on equations (1) and (3) of the intermediate and semi-global interconnects page. This keeps continuing for other metal levels till one runs out of die area for placing more repeaters or till the addition of repeaters does not improve wire delay.
6. Power computation and iteration: Once repeaters are assigned, the total chip power is calculated. If the total power calculated is different from the power estimate used for designing power distribution wiring, IntSim sets Estimated Power = 0.5*(Old estimated power + Calculated Power) and goes back to Step 2. For the next iteration, the number of repeaters is set as the value calculated in Step 5.
7. Data output: When the simulation converges, the total number of wire levels, pitches of each wire level and a power estimate are output.