Webcast Overview: 

It is well recognized that dimensional scaling has reached its diminishing return phase. The industry is now looking at monolithic 3D to be the future technology driver. Yet, until recently, the path to monolithic 3D has required the development of new transistor types and processes. This Webcast will present game-changing monolithic 3D process flows, which use the existing transistor of existing manufacturing line and existing process flows. Now the most effective path for future IC scaling is indeed monolithic 3D, which offers the lowest development and manufacturing cost for future ICs.  
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1) Currently, I am working in a large project where we develop ICs and hermetic wafer level packages. My question is what are the key requirements to land on a job as a process engineer? (I hope my question is not completely out of the context)

Asked by Dilek Isik - Ecole Polytechnique de Montreal

2)Which NEMS gas sensor Technology is used by LETI?

Asked by Roberto Dossi - zmdi 

3) The benefits of 3D active on active have been clear for a while. The main feature that is missing is "AVAILABILITY" through popular manufacturing channels. Any comments on when such technology is available, say from TSMC or other known fabs at a product quality?

Asked by Alireza Kaviani - Xilinx 

4) Large devices such as FPGAs have many metal layers. TSVs need to go through so many of those layers to get to other active die. Are there any studies (or comments) on area overhead of such process on metal layers?

Asked by Alireza Kaviani - Xilinx

5) What challenges other than technical remain to be resolved before such a technology would be adopted for high volume manufactured, high performance computing products?

Asked by Jon Candelaria - Semiconductor Research Corp. 

6) Can you provide additional details about molecular bonding? It appears to be a critical process step for M3D.

Asked by Ajit Paranjpe - Veeco 

7) How effective is molecular bonding for long term stability of he ICs? What if we need to use bonding processes with T higher than 300 C?

Asked by Dilek Isik - Ecole Polytechnique de Montreal 

8) Dear Dr. Vinet, how are you doing the gate oxide of the top CMOS?

Asked by Juergen Niess - HQ-Dielectrics GmbH


9) Yield is a function of process steps. monolithic 3D has twice the number of steps (for 2 layers). Yield will be lowered as defects in any layer will kill the die. So, defect density have to be twice as good before we have the same yield. Is it likely?

Asked by TM Mak - Global Foundries 

10) What's about cost of pure stacking on Memory?

Asked by Roberto Dossi - zmdi 

11) Concerning the ELTRAN process: bringing so close together devices in the stratrum 2 and stratrum 3 without a thick silicon heat sink in between, how do you handle the heat generated from each layer of transistors?

Asked by Fabio Carta - Columbia University Reply 

12) 1-How does the cost multiply with the number of layers being manufactured? Is there an approximation rule for this? 2-For precise bonders, what is the cost difference between die-to-die bonding vs wafer level bonding?

Asked by Dilek Isik - Ecole Polytechnique de Montreal 

13) Have you evaluated the yield impact of the 3D monolithic approach?

Asked by Jim Wieser - Texas Instruments 

14) how can you guarantee 100nm via pitch with actual bonder alignment tolerance?

Asked by Roberto Dossi - zmdi 

15) What is the yield of the presented ELTRAN process?

Asked by Dilek Isik - Ecole Polytechnique de Montreal