3D Industry News and Progress Reports

  • Experts At The Table: Yield Issues (April 22, 2011) — Semiconductor Manufacturing & Design has a very interesting discussion of the ways that die stacking will impact final product yields.
  • Wally Rhines 3D IC Keynote   (April 19, 2011) — The DAC blog does an outstanding job of reporting the details from Dr. Rhines' keynote at the GlobalPress Forum.
  • 3-D ICs stack up design challenges: Mentor's CEO lists some of the issues awaiting 3D IC designers  (April 14, 2011) — EDN's Editorial Director, Ron Wilson, covers Dr. Walden Rhines, CEO of Mentor Graphics' address to the GlobalPress Forum.  Dr. Rhines gives a good (albeit TSV focused) history of 3D, as well some of the challenges from a design tool perspective.
  • The 3-D IC and you:  All the talk seems to be about the 3-D IC, but does it amount to anything?  (April 7, 2011) — EDN's Editorial Director, Ron Wilson, poses a number of interesting questions about how "real" 3D IC's are.  The results of the work done at MonolithIC 3D show that true vertical integration of semiconductors is a much nearer term reality than Mr. Wilson might be suggesting.
  • Experts at the Table:  3D Stacking  (February 14, 2011) — "Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice president of marketing at Atrenta for a roundtable discussion on the topic.
  • TSV makes EETimes 2010 Hot Tech List (November 18, 2009) — EETimes reports that, "The desire, for marketing as well as technical reasons, to mount multiple die in single packages is also driving a need for more sophisticated interconnect and the arrival of the through-silicon-via passing completely through a silicon wafer or die is clearly important in creating 3-D packages."  While we may disagree with the focus on TSVs, we clearly agree with the overall premise!
  • IBM, GIT demo 3D die with microchannel cooling (June 5, 2008) — A great article from EETimes describing Deepak's work on a liquid cooling technique for 3D stacked dice.  His team passed liquid on the back-side of each die in the 3D stack and could cool even power-hungry 100W-type chips stacked in 3D. 
  • Through Silicon Vias (TSV):  Design and Reliability (PDF) — A very interesting slide deck from our friends at ALLVIA, the TSV foundry specialists.  The pictures alone more than justify a look!


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