References
[1]
http://public.itrs.net
[2] Oh-Hyun Kwon (Samsung), Keynote, Design Automation Conference, 2007.
[3] J. Davis, et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE , vol.89, no.3, pp.305-324, Mar 2001.
[4] Synopsys, Proc. 3D-ASIP Conference, December 2010.
[5] L. Zhou, et al., “Implementing a 2-Gbs 1024-bit ½-rate low-density parity-check code decoder in three-dimensional integrated circuits”, Proc. ICCD, 2007.
[6] D. C. Sekar, et al., “IntSim: A CAD tool for optimization of multilevel interconnect networks”, Proc. ICCAD 2007.
[7] W. G. En, et al., “The Genesis Process: A new SOI wafer fabrication method”, Proc. IEEE SOI conference, 1998.
[8] W. G. En, et al., “The Genesis Process: A new SOI wafer fabrication method”, Proc. IEEE SOI conference, 1998.
[9] M. Sadaka, et al., “Building blocks for wafer-level 3D integration”, Solid State Technology, October 2009.
[10] J. Y. Kim, et al., “The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor( RCAT) for 88 nm feature size and beyond”, VLSl Digest of Technical Papers, pp. 11-12,2003.
[11] Y. Choi, “Under the Hood: The race is on for 50-nm DRAM”, EETimes, 9th February 2009.
[12] S. Natarajan, et al., “A 32nm logic technology …”, Proc. IEDM 2008.
[13] Report from Morgan Stanley, available at http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf
[14] W. E. Donath, "Wire length distribution for placements of computer logic", IBM Journal of Research and Development, Volume 25 Issue 2-3, March 1981
[15] J. Davis, PhD dissertation, Georgia Institute of Technology, 1999
[16] Christie, P.; Stroobandt, D.; , "The interpretation and application of Rent's rule," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.8, no.6, pp.639-648, Dec 2000
[17] N. Magen, et al., "Interconnect power dissipation in a microprocessor", Proc. System Level Interconnect Prediction Workshop, 2004.
[18] R. Venkatesan, PhD dissertation, Georgia Institute of Technology, 2003.
[19] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C.; , "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001.
[20] A. Rahman, PhD dissertation, Massachusetts Institute of Technology, 2001.
[21] J. Joyner, PhD dissertation, Georgia Institute of Technology, 2003.
[22] D. C. Sekar, PhD dissertation, Georgia Institute of Technology, 2008.
[23] H. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
[24] R. Venkatesan, PhD dissertation, Georgia Institute of Technology, 2003.
[25] D. C. Sekar, E. Demaray, H. Zhang, P. Kohl, J. Meindl,”A New Global Interconnect Paradigm: MIM Power Ground Plane Decoupling Capacitors”, Proc.Intl. Interconnect Technology Conference, pp. 48-50, 2006.
[26] R. Sarvari, A. Naeemi, P. Zarkesh-Ha, J. Meindl, “Design and Optimization for Nanoscale Power Distribution Networks in Gigascale Systems”, Proc. Intl. Interconnect Technology Conference, pp. 190-192, 2007.
[27] Q. Chen, J. Davis, P. Zarkesh-Ha, J. Meindl, “A Compact Physical Via Blockage Model”, Transactions on VLSI Systems, Vol. 8, Issue 6, pp. 689-692, Dec. 2000.
[28] N. Sakran, M. Yuffe, M. Mehalel, J. Doweck, E. Knoll, A. Kovacs, “The Implementation of the 65nm Dual Core Merom Processor”, Proc. Intl. Solid State Circuits Conference, pp. 106-590, 2007.
[29] P. Bai, C. Auth, S. Balakrishnan, et al. “A 65nm Logic Technology featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu interconnect layers, Low k ILD and a 0.57 um2 SRAM cell”, Proc. Intl. Electron Devices Meeting, pp. 657-660, 2004.
[30] S. Naffziger, B. Stackhouse, T. Grutkowski, “The implementation of a 2 core multi-threaded Itanium family processor”, Proc. Intl. Solid State Circuits Conference, pp. 182-183, 2005.
[31] Models in BACPAC. Available online at www.eecs.umich.edu/~dennis/bacpac
[2] Oh-Hyun Kwon (Samsung), Keynote, Design Automation Conference, 2007.
[3] J. Davis, et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE , vol.89, no.3, pp.305-324, Mar 2001.
[4] Synopsys, Proc. 3D-ASIP Conference, December 2010.
[5] L. Zhou, et al., “Implementing a 2-Gbs 1024-bit ½-rate low-density parity-check code decoder in three-dimensional integrated circuits”, Proc. ICCD, 2007.
[6] D. C. Sekar, et al., “IntSim: A CAD tool for optimization of multilevel interconnect networks”, Proc. ICCAD 2007.
[7] W. G. En, et al., “The Genesis Process: A new SOI wafer fabrication method”, Proc. IEEE SOI conference, 1998.
[8] W. G. En, et al., “The Genesis Process: A new SOI wafer fabrication method”, Proc. IEEE SOI conference, 1998.
[9] M. Sadaka, et al., “Building blocks for wafer-level 3D integration”, Solid State Technology, October 2009.
[10] J. Y. Kim, et al., “The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor( RCAT) for 88 nm feature size and beyond”, VLSl Digest of Technical Papers, pp. 11-12,2003.
[11] Y. Choi, “Under the Hood: The race is on for 50-nm DRAM”, EETimes, 9th February 2009.
[12] S. Natarajan, et al., “A 32nm logic technology …”, Proc. IEDM 2008.
[13] Report from Morgan Stanley, available at http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf
[14] W. E. Donath, "Wire length distribution for placements of computer logic", IBM Journal of Research and Development, Volume 25 Issue 2-3, March 1981
[15] J. Davis, PhD dissertation, Georgia Institute of Technology, 1999
[16] Christie, P.; Stroobandt, D.; , "The interpretation and application of Rent's rule," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.8, no.6, pp.639-648, Dec 2000
[17] N. Magen, et al., "Interconnect power dissipation in a microprocessor", Proc. System Level Interconnect Prediction Workshop, 2004.
[18] R. Venkatesan, PhD dissertation, Georgia Institute of Technology, 2003.
[19] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C.; , "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001.
[20] A. Rahman, PhD dissertation, Massachusetts Institute of Technology, 2001.
[21] J. Joyner, PhD dissertation, Georgia Institute of Technology, 2003.
[22] D. C. Sekar, PhD dissertation, Georgia Institute of Technology, 2008.
[23] H. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
[24] R. Venkatesan, PhD dissertation, Georgia Institute of Technology, 2003.
[25] D. C. Sekar, E. Demaray, H. Zhang, P. Kohl, J. Meindl,”A New Global Interconnect Paradigm: MIM Power Ground Plane Decoupling Capacitors”, Proc.Intl. Interconnect Technology Conference, pp. 48-50, 2006.
[26] R. Sarvari, A. Naeemi, P. Zarkesh-Ha, J. Meindl, “Design and Optimization for Nanoscale Power Distribution Networks in Gigascale Systems”, Proc. Intl. Interconnect Technology Conference, pp. 190-192, 2007.
[27] Q. Chen, J. Davis, P. Zarkesh-Ha, J. Meindl, “A Compact Physical Via Blockage Model”, Transactions on VLSI Systems, Vol. 8, Issue 6, pp. 689-692, Dec. 2000.
[28] N. Sakran, M. Yuffe, M. Mehalel, J. Doweck, E. Knoll, A. Kovacs, “The Implementation of the 65nm Dual Core Merom Processor”, Proc. Intl. Solid State Circuits Conference, pp. 106-590, 2007.
[29] P. Bai, C. Auth, S. Balakrishnan, et al. “A 65nm Logic Technology featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu interconnect layers, Low k ILD and a 0.57 um2 SRAM cell”, Proc. Intl. Electron Devices Meeting, pp. 657-660, 2004.
[30] S. Naffziger, B. Stackhouse, T. Grutkowski, “The implementation of a 2 core multi-threaded Itanium family processor”, Proc. Intl. Solid State Circuits Conference, pp. 182-183, 2005.
[31] Models in BACPAC. Available online at www.eecs.umich.edu/~dennis/bacpac
