Scaling Up: The MonolithIC 3D Record of Invention, 2010–2026
“Dimensional scaling is ending. Scaling up is the way forward. Here is the practical, cost-effective way to do it.” A documented sixteen-year public record, and the industry that followed it.
The Case in One Paragraph
Beginning in 2010, MonolithIC 3D Inc. told the semiconductor industry, in keynotes, peer-reviewed papers, book chapters, free e-books, open simulators, and more than a decade of continuous public blogging, that dimensional (2D) scaling was approaching its economic end, and that the industry’s future lay in scaling up: building integrated circuits vertically, using layer transfer, precision wafer bonding, and ultimately hybrid bonding, on existing fab equipment at existing nodes. The company did not merely predict the destination; it published the practical process flows, the cost models proving economic viability, the thermal solutions answering the standard objections, and the system architectures (memory-on-logic, two-wafer NAND, 3D DRAM) that define today’s memory industry. In parallel, it filed and prosecuted the patent estate covering that path: more than 400 issued, with many more applications pending, the earliest grants issuing in 2011 from applications filed in 2009–2010. Every major element of the thesis has since been adopted by the industry: YMTC’s Xtacking (2018), AMD’s 3D V-Cache (2022), Kioxia/SanDisk’s CMOS-directly-Bonded-to-Array NAND (2023–2026), hybrid bonding on every HBM roadmap, 4F²/vertical 3D DRAM as the industry’s declared next architecture, and, in mid-2026, memory-on-logic near-memory computing announced as the datacenter roadmap of Qualcomm (High Bandwidth Compute) and reported as a TSMC/Winbond wafer-bonding program, while Huawei codified equivalent scaling through 3D architecture as its “Tau Scaling Law.” The publications came first. The patents came first. The industry followed.
Beginning in 2010, MonolithIC 3D Inc. told the semiconductor industry, in keynotes, peer-reviewed papers, book chapters, free e-books, open simulators, and more than a decade of continuous public blogging, that dimensional (2D) scaling was approaching its economic end, and that the industry’s future lay in scaling up: building integrated circuits vertically, using layer transfer, precision wafer bonding, and ultimately hybrid bonding, on existing fab equipment at existing nodes. The company did not merely predict the destination; it published the practical process flows, the cost models proving economic viability, the thermal solutions answering the standard objections, and the system architectures (memory-on-logic, two-wafer NAND, 3D DRAM) that define today’s memory industry. In parallel, it filed and prosecuted the patent estate covering that path: more than 400 issued, with many more applications pending, the earliest grants issuing in 2011 from applications filed in 2009–2010. Every major element of the thesis has since been adopted by the industry: YMTC’s Xtacking (2018), AMD’s 3D V-Cache (2022), Kioxia/SanDisk’s CMOS-directly-Bonded-to-Array NAND (2023–2026), hybrid bonding on every HBM roadmap, 4F²/vertical 3D DRAM as the industry’s declared next architecture, and, in mid-2026, memory-on-logic near-memory computing announced as the datacenter roadmap of Qualcomm (High Bandwidth Compute) and reported as a TSMC/Winbond wafer-bonding program, while Huawei codified equivalent scaling through 3D architecture as its “Tau Scaling Law.” The publications came first. The patents came first. The industry followed.
The Thesis Stated Early (2010–2011)
The founding claim was made publicly, by name, in the industry’s own venues, before any of today’s commercial 3D memory products existed:
The patents were already issuing. US Patents 7,960,242 and 7,964,916 issued in June 2011, and 7,986,042 in July 2011, from applications with 2009–2010 priority, beginning an unbroken sixteen-year grant cadence that now totals more than 400 issued US patents.
The founding claim was made publicly, by name, in the industry’s own venues, before any of today’s commercial 3D memory products existed:
- January 2010: Invited presentation at the Applied Materials 3D Interconnect Symposium: “3D-FPGA: The Path to ASIC-like Density, Power and Performance.”
- December 2010: Invited presentation at the 3D-ASIP Conference: “Monolithic 3D Technology: A Semiconductor Industry Game Changer.”
- March 2011: The MonolithIC 3D technical blog launches; it has published continuously since, creating a dated, public, searchable record of the company’s teachings for fifteen years. A parallel channel of dated technical articles has run on the founder’s LinkedIn profile, and further teaching appeared as EE Times and Semiconductor Digest columns throughout.
- April 2011: “Monolithic 3D Integrated Circuits,” Future-Fab International, Issue #37.
- May–July 2011: Invited talks at the International Memory Workshop (“Monolithic 3D FPGAs”), the Technical University of Munich, the American Vacuum Society Workshop on 3D Packaging (“Monolithic 3D DRAM Technology”, the 3D DRAM teaching fifteen years before the industry’s current 3D DRAM race), the CMOS Emerging Technologies Workshop, and Intel Research (Photonics Technology Lab).
- September 2011: Invited talk at UC Berkeley: “Resistive RAM: Technology and Market Applications.”
- October 7, 2011: Invited keynote, International Electronics Forum, Seville: “Monolithic 3D-ICs: The Effective Alternative to Dimensional Scaling.” The thesis, stated in the title, on a keynote stage, in 2011.
- November 2011: Invited lecture at the Technion: “Monolithic 3D - The Effective Alternative to Dimensional Scaling”; invited talk at the 9th International SoC Conference.
- 2011–2012: Industry recognition of the breakthrough: finalist, “Best of Semicon West 2011”; finalist, EE Times Innovator of the Year, 2011 and 2012; named Top Embedded Innovator (Silicon) by Embedded Computing Design.
The patents were already issuing. US Patents 7,960,242 and 7,964,916 issued in June 2011, and 7,986,042 in July 2011, from applications with 2009–2010 priority, beginning an unbroken sixteen-year grant cadence that now totals more than 400 issued US patents.
The Economic Call: “Moore’s Law Stopped at 28nm” (2014 → validated 2023)
In 2014, while Intel was publishing roadmaps promising continued cost-per-transistor reduction for the foreseeable future, Zvi Or-Bach published the contrarian, falsifiable claim that transistor cost scaling had stopped at the 28 nm node (EE Times, “Intel vs. Intel,” 2014, with a deeper technical analysis in 2016 covering lithography cost escalation and transistor complexity). The claim was widely covered (Design & Reuse, EE Times Asia, SmartBrief, and others) and widely doubted.
Nine years later it was confirmed from the industry’s own podium. At IEDM 2023, Short Course SC1.6, Milind Shah of Google stated: “Transistor cost scaling (0.7X) stalled at 28 nm and remains flat gen over gen.”
This matters beyond vindication: the end of cost scaling is the economic premise of the entire scaling-up thesis. If cost-per-transistor no longer falls with node shrinks, the only remaining path to more capability per dollar is vertical integration on mature nodes, exactly what the memory industry then did.
In 2014, while Intel was publishing roadmaps promising continued cost-per-transistor reduction for the foreseeable future, Zvi Or-Bach published the contrarian, falsifiable claim that transistor cost scaling had stopped at the 28 nm node (EE Times, “Intel vs. Intel,” 2014, with a deeper technical analysis in 2016 covering lithography cost escalation and transistor complexity). The claim was widely covered (Design & Reuse, EE Times Asia, SmartBrief, and others) and widely doubted.
Nine years later it was confirmed from the industry’s own podium. At IEDM 2023, Short Course SC1.6, Milind Shah of Google stated: “Transistor cost scaling (0.7X) stalled at 28 nm and remains flat gen over gen.”
This matters beyond vindication: the end of cost scaling is the economic premise of the entire scaling-up thesis. If cost-per-transistor no longer falls with node shrinks, the only remaining path to more capability per dollar is vertical integration on mature nodes, exactly what the memory industry then did.
The Validation Cascade: The Industry Executes the Thesis (2018–2026)
Each item below is a third party independently adopting, demonstrating, or announcing an element MonolithIC 3D had already published and patented:
Each item below is a third party independently adopting, demonstrating, or announcing an element MonolithIC 3D had already published and patented:
Year |
Adopter / Event |
The element validated |
Taught by MonolithIC 3D |
Sept 2017 |
DARPA ERI / 3DSoC program ($500–800M initiative): calls for monolithic 3D enabling >50× SoC performance-at-power vs 7nm 2D CMOS; Intel’s Al Fazio plenary at IEEE S3S 2017 presents 3D NAND / 3D XPoint as trailblazing monolithic 3D in volume production |
US Government funding of the scaling-up direction; Intel confirming memory as the early adopter |
Thesis publications 2010–2017; documented in real time, Sept 19, 2017 |
Aug 2018 |
YMTC Xtacking launches at Flash Memory Summit (“Best of Show”): periphery CMOS wafer hybrid-bonded onto 3D NAND array wafer |
Two-wafer NAND: logic wafer + memory wafer, bonded |
Two-wafer / layer-transfer memory architectures published 2011–2015; patents from 2009–2010 priorities |
Sept 2020 |
IC League HITOC paper: “Breaking the Memory Wall for AI Chip with a New Dimension”: logic wafer + DRAM wafer, hybrid bonded |
Memory-on-logic via hybrid bonding |
2017 S3S paper; 2020 NANO-CHIPS 2030 Ch. 15 |
Feb 2022 |
Alibaba, ISSCC 2022: 3D logic-to-DRAM hybrid bonding, 602 mm² die, >1,000× improvement in AI computing (9.78× speedup, 317× energy efficiency, 660× area efficiency) on 55 nm logic vs 14 nm Xeon |
The 1,000× number itself, achieved by the published method, on mature nodes |
2017 S3S: “A 1,000× Improvement…”; flagged same month in “China May Win in AI Computing,” EE Times, Mar 2022 |
2022–2023 |
AMD 3D V-Cache ships; Dr. Lisa Su, ISSCC 2023: “Tighter Integration of Compute and Memory” |
Hybrid-bonded memory-on-logic in volume production |
Memory-on-logic teachings 2011–2020 |
2022 |
imec publishes the BSPDN flow (ECTC 2022, Jourdain et al.): a 50nm epitaxial SiGe25% layer as the etch stop; grind plus selective soft-landing wet etch on the SiGe; sub-40nm total thickness variation at final silicon thickness below 500nm, enabling nano-TSVs to buried power rails |
The SiGe cut / etch-stop layer as the enabler of backside power delivery |
SiGe cut layer: WO 2017/053329 (published Mar 30, 2017; US 10,515,981, Fig. 44). Power from below: US 8,395,191, Figs. 83L–83L4 (2009 priority). Republished: NANO-CHIPS 2030 Ch. 8 §8.3 (2020) |
2023 |
Chinese ecosystem documented: Xinmeng 3D 4F² DRAM (HITOC); Jasminer X4, the industry’s first DBI hybrid bonding with DRAM (TechInsights); Seehi SH9000 tiled DRAM-on-logic |
4F² 3D DRAM; hybrid-bonded DRAM systems on mature nodes |
“Update: China May Win in AI Computing,” Semiconductor Digest, May 2023, plus underlying 3D DRAM publications from 2011 |
Dec 2023 |
MonolithIC 3D forecast in print: 2024 = hybrid-bonding inflection across logic, DRAM, NAND; Kioxia/WD BiCS8 218L CBA to volume production; HBM4 with hybrid bonding; Samsung 4F² + hybrid-bonding DRAM at IEDM; Intel PowerVia extreme-thinning |
Named, dated predictions across all three segments |
“2024 Forecast: Hybrid Bonding Steps Up,” Dec 2023 |
Dec 2023 |
Google, IEDM 2023 SC1.6: transistor cost scaling stalled at 28 nm |
The 2014 economic call |
EE Times 2014; technical analysis 2016 |
2023–2026 |
Kioxia/SanDisk CBA generation ships and scales: BiCS8 (218L) to volume; BiCS10 (332L) sample-shipping July 2026, built as separate logic and NAND-cell wafers, bonded; SK hynix 321L; Samsung Cell-on-Periphery |
CMOS-directly-Bonded-to-Array = the two-wafer NAND architecture, now the industry’s mainstream direction |
Two-wafer NAND teachings and patents, 2009–2015; predicted by name Dec 2023 |
2023–2026 |
Backside power delivery goes mainstream: Intel commercializes PowerVia (announced 2023, first products on 18A-class nodes); TSMC announces A16 with Super Power Rail; Samsung announces SF2Z with BSPDN. SiGe layers are native to gate-all-around nanosheet nodes, making the cut-layer approach the industry’s natural path |
Extreme-thinning backside architecture as the leading-edge logic standard |
The power-from-below (2009) and SiGe cut-layer (2016/2017) teachings; named in the December 2023 forecast |
2024–2026 |
Hybrid bonding on every HBM roadmap (HBM4/HBM4E era); all DRAM vendors pursuing 3D DRAM via hybrid bonding and 4F²/vertical architectures |
Vertical DRAM and bonded stacking as DRAM’s future |
3D DRAM talks from June 2011; 3D DRAM patent families throughout |
Nov 2025 |
IEEE TENCON 2025 Best Paper Award: “Design of Highly Stackable Charge Trap-Based 3D DRAM” (1T poly-Si channel, Schottky-barrier metal-silicide S/D, CXL-class applications) |
Ongoing, award-recognized invention in exactly the industry’s next battleground |
MonolithIC 3D’s own current R&D |
Mid-2025 |
The world’s largest memory maker takes a patent license to the portfolio |
Commercial validation by the industry leader |
The portfolio itself |
May 2026 |
Huawei proposes the “Tau Scaling Law”: equivalent transistor-density gains through 3D architectural innovation, framed as a named engineering principle for the post-Moore era |
Scaling up as codified doctrine at China’s national champion |
“The Effective Alternative to Dimensional Scaling” (keynote, 2011); the 2022–2023 “China May Win” series |
June 2026 |
Qualcomm announces High Bandwidth Compute (HBC) at its Investor Day: LPDDR stacked in 3D directly on a custom compute base die with near-memory processing, anchoring its multi-generation datacenter roadmap (AI250 sampling mid-2027) as an alternative to the “HBM tax” |
Memory-on-logic near-memory computing as a flagship compute-vendor roadmap |
2017 S3S: “A 1,000× Improvement…”; memory-on-logic teachings 2011–2020 |
July 2026 |
Dongfang Suanxin exits stealth (led by Wei Shaojun, vice-president of the China Semiconductor Industry Association): 3D stacked near-memory computing on a fully domestic supply chain (SCMP, July 5, 2026) |
The processor-memory-gap architecture as Chinese national-champion strategy |
2017 S3S paper; “China May Win in AI Computing,” 2022; “Update,” 2023 |
July 2026 |
TSMC / Winbond wafer-on-wafer DRAM stacking (industry reports, unconfirmed): DRAM wafers hybrid-bonded directly with logic wafers to attack the AI memory bottleneck |
Two-wafer logic-plus-memory bonding entering the foundry layer |
Two-wafer teachings and patents, 2009–2015; 2017 S3S paper |
Aug 2026 |
Samsung introduces V10 BV-NAND [archived copy], for Bonding V-NAND: an industry-first NAND architecture enabled by a new wafer bonding technology, with more than 400 layers and about 58% higher density than the previous generation. |
Bonded two-wafer construction as the NAND architecture itself, now named in the product |
“Monolithic 3D Memory: NAND Flash, DRAM and R-RAM,” 2013; layer transfer and bonded memory teachings, 2010 to 2020 |
Aug 2026 |
Samsung previews zHBM [archived copy], stacking HBM directly above the AI accelerator rather than beside it, with wafer bonding named as the density enabler and customer IP contemplated in the interlayer between memory and accelerator. |
Compute and memory in a single vertical stack as the destination architecture, with logic in the bonding interlayer |
“A 1,000x Improvement in Computer Systems by Bridging the Processor-Memory Gap,” IEEE S3S 2017 |
Aug 2026 |
www.servethehome.com/d-matrix-raptor-3d-dram-accelerator-for-generative-inference-at-hot-chips-2026/Hot Chips 2026 (Stanford, Aug 23-25). Micron reports AI accelerator compute rising about 3× every two years against less than 2× for HBM bandwidth, notes that memory silicon is about 90% of a four-stack 16-high GPU package (roughly 8× the GPU silicon) and that HBM faults caused 17% of the unplanned interruptions in Meta’s Llama 3 training, and calls the memory wall a problem that is getting worse, naming hybrid bonding and fusion bonding among the required remedies; SK hynix presents an HBM packaging roadmap running from hybrid bonding to full 3D integration, citing a 775 μm stack-height ceiling that only thinner, hybrid-bonded dies can relieve; d-Matrix shows working silicon of Raptor, a TSMC 4 nm compute die bonded face to face onto a custom DRAM die, delivering 32 GB at more than 100 TB/s per card at 0.37 pJ/bit versus about 2.4 pJ/bit for HBM4. |
The processor-memory gap named as AI’s binding constraint by the memory makers themselves, with hybrid-bonded memory-on-logic as the declared remedy; the Fig. 14 architecture of the 2017 paper demonstrated in working silicon |
“A 1,000x Improvement in Computer Systems by Bridging the Processor-Memory Gap,” IEEE S3S 2017 (Figs. 1, 10, 14); memory-on-logic teachings 2011-2020 |
Aug 2026 |
Cerebras, Hot Chips 2026: CS-6 roadmap announced: for the first time, DRAM 3D-stacked at wafer scale on top of its wafer-scale logic-and-SRAM engine, with a yield-resilient architecture, vertical power delivery, and fully integrated cooling, to reach the same memory capacity in an order-of-magnitude smaller footprint |
Wafer-scale memory-on-logic 3D integration, together with the three enablers it requires: yield resilience through redundancy and repair, power from below, and integrated cooling |
Wafer-scale 3D integration made yieldable by stacked redundancy and repair layers: “Redundancy & Repair” presentation, Feb 4, 2011; blog post “Monolithic 3D IC Could Increase Circuit Integration by 1,000x,” Dec 15, 2011 (off-chip data movement >>100x the energy; yield removed as a constraint; “we could even integrate 1,000 such devices”); “The Monolithic 3D Advantage” (3D-IC Edge, c. 2013-14), Sec. 6: “3D WSI,” about 1,000x at board, rack and server-farm level, memory 1 micron above logic; WSI with repair layers and a continuous array spanning the wafer in the foundational patent specifications (as issued, e.g., US 12,125,737); repairable memory strata, IEEE S3S 2017 (Figs. 11, 13, 14); NANO-CHIPS 2030 Ch. 15 (2020); power from below, US 8,395,191 (2009 priority); cooling, IEDM 2012 |
Aug 2026 |
Xiaomi unveils the XRING O100 AI chip (Aug 24, 2026): a 6 nm logic layer, an NPU layer, and two layers of vertical DRAM in one hybrid-bonded 3D stack at 1.4 µm pitch, forming 28,672 vertical data connections at 1.22 TB/s; slated for devices by 2027 (Xiaomi AI Cube shown) |
Hybrid-bonded memory-on-logic near-memory compute reaching consumer and edge silicon, designed by a phone maker |
“A 1,000x Improvement in Computer Systems by Bridging the Processor-Memory Gap,” IEEE S3S 2017; memory-on-logic teachings 2011–2020 |
Aug 2026 |
Fujitsu Monaka, Hot Chips 2026 (Aug 24, 2026): 144-core Arm server CPU with 2 nm compute dies hybrid-bonded face-to-face onto 5 nm dies holding the entire last-level cache and the per-core voltage regulators; 2 nm silicon held under 30% of die area to cut cost; volume production 2027; NEDO-subsidized |
Memory-on-logic with mixed nodes as the answer to stalled cost scaling, and power regulation delivered from the die beneath the transistors |
“Intel vs. Intel,” EE Times, 2014 (cost scaling); memory-on-logic teachings 2011–2020; power from below, US 8,395,191 (2009 priority) |
Aug 2026 |
The equipment layer commits: Applied Materials, Seoul media briefing (Aug 31, 2026), states that data-movement efficiency, not compute speed, is the AI bottleneck and that the industry’s solution is 3D scaling; that HBM stacking must move from microbumps to hybrid bonding to keep scaling at acceptable power, reaching about 1,000,000 I/Os per mm²; and that its advanced-packaging revenue will grow more than 70% in 2026, with hybrid-bonding programs running at its $5B EPIC center. Besi, the leading hybrid-bonder supplier, reports that its Q2 2026 orders roughly doubled year on year on AI-driven hybrid bonding demand |
The capital-equipment industry now organized around scaling up, with hybrid bonding as the volume tool set |
“Monolithic 3D-ICs: The Effective Alternative to Dimensional Scaling” (keynote, 2011); “Scaling Makes Monolithic 3D IC Practical,” 2013; “Precision Bonders - A Game Changer for Monolithic 3D,” IEEE S3S 2014 |
Sept 2026 |
Samsung codifies scaling up as memory doctrine: at SEMICON Taiwan (Sept 1, 2026) the head of memory product planning presents “CUBE” (Capacity, Utilization, Bandwidth, Efficiency) as the governing strategy of the world’s largest memory maker: build memory upward rather than outward, and place logic and memory within the stack to cut latency (“3D is not simply about stacking”; “we will no longer be constrained by the printed circuit board area”), with zHBM targeted at 8× HBM4E performance and 3× performance per watt, and zNAND-O sampling in 2028 |
Vertical integration of memory and logic declared the organizing principle of the memory industry’s leader, at the scale of its entire production base |
“Monolithic 3D-ICs: The Effective Alternative to Dimensional Scaling” (keynote, 2011); “Monolithic 3D DRAM Technology,” June 2011; “Monolithic 3D Memory: NAND Flash, DRAM and R-RAM,” 2013; “A 1,000× Improvement...,” IEEE S3S 2017 |
The pattern is uniform: publication → skepticism → third-party demonstration → industry adoption → commercial mainstream. Sixteen years, one thesis, no reversals. And in the second quarter of 2026 alone, the convergence extended beyond the memory makers to the compute layer (Qualcomm), the foundry layer (TSMC, reported), Chinese national doctrine (Huawei, Dongfang Suanxin), consumer silicon (Xiaomi), and the equipment suppliers (Applied Materials, Besi): every layer of the industry is now converging on memory-on-logic 3D integration. On September 1, Samsung presented vertical integration as the governing strategy of its memory business.
At Hot Chips 2026 the memory makers themselves named the processor-memory gap as AI’s binding constraint and hybrid-bonded 3D integration as the way through it, and Cerebras announced DRAM stacked at wafer scale on its wafer-scale engine. Independent analysis of the conference reached the same conclusion under the title “The Memory Wall Is Making Hybrid Bonding a Necessity.
At Hot Chips 2026 the memory makers themselves named the processor-memory gap as AI’s binding constraint and hybrid-bonded 3D integration as the way through it, and Cerebras announced DRAM stacked at wafer scale on its wafer-scale engine. Independent analysis of the conference reached the same conclusion under the title “The Memory Wall Is Making Hybrid Bonding a Necessity.
The complete document, including the patent estate analysis and full source register, is available in the PDF above.
The inventions described in this record are available for license.
See MonolithIC 3D Technology Licensing
See MonolithIC 3D Technology Licensing
Rev. 9, published September 2026. This page is updated as the record grows; prior revisions are preserved.