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Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC



Two Major Semiconductor Trends Help Make Monolithic 3D Practical

As we have pushed dimensional scaling: 
  • The volume of the transistor has scaled
                               - Bulk um-sized transistors -> FDSOI & FinFet nm transistors
  • Processing temperatures have trended lower
                               - Shallower & sharper junctions, tighter pitches, etc.
Much less mass to heat, and for much shorter time -> reduction in total thermal energy
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Source: LETI
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Annealing Trend with Scaling Source: Ultratech
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Major Thermal Process Steps in a Modern IC Process

Laser Spike Annealing

  • Goals
             - Activate implanted dopants
             - Do not disrupt already-fabricated devices lying beneath the fresh Si layerIssues
             - Thermal stress
             - Heat transfer dynamics to underlying layers
  • Approach
             - Short wavelength laser is optimum – mostly absorbs energy in the top few nm
             - Use combination of thermal/electrical insulators, and high heat capacity metallic shield layers
             - All materials compatible with existing IC technology

Dopant Activation by Laser: IEDM 2013 Example

  • Taiwan National Nano Device Laboratory: IEDM13-Paper #9.3            
              - ‘green’ laser: HIPPO 532QW Nd/YAG, 532 nm wavelength, 13 ns pulse width, 25 cm/s scanning speed, and 2.7 mm X 60 µm beam size
              - “Researchers from Taiwan’s National Nano Device Laboratories avoided the use of TSVs by fabricating a monolithic sub-50-nm 3D chip, which integrates high-speed logic and nonvolatile and SRAM memories... The monolithic 3D architecture demonstrated high performance – 3 ps logic circuits, 1T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints…”
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Dopant Activation by Laser: IEDM 2013 Example

Laser Spike Annealing of Top Monocrystalline Silicon Layer

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Types






                           Dwell time ~ 275µs
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LSA 100A – Short Pulse, Small Spot

Laser Spike Annealing of Top Monocrystalline Silicon Layer

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Ion-Cut Applied to Monolithic 3D 

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Pulsed Laser Anneal May Be Used to Repair Ion-Cut Lattice Damage of Top Monocrystalline Silicon Layer

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Conclusions

  • Monolithic 3D IC technology is a leading approach to extend IC scaling beyond the 7-10 nm nodes
                               - Key obstacle:  thermal processing the top c-Si layer without disturbing the already-processed devices & BEOL beneath 
  • Use of laser spike annealing on a thin layer of c-Si, combined with metal and insulator thermal shield layers, allows:
                               - Thermal process profiles needed to activate dopants
                               - No disruption to underlying structures
                               - Annealing of ion-cut damage
                               - Densification and other anneals
  • Pulsed laser annealing works because:
                               - Thin Si layers require only a small amount of thermal energy to anneal
                               - The thermal energy required is shielded from the underlying structures by the thermal heat capacity of the shield

References

  1. "Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC", Paper presented at the 2013 IEEE 3DIC Conference, October 2013.
  2. "Thermal Considerations for Monolithic Integration of Three-Dimensional Integrated Circuits", Poster presented at the 2013 S3S Conference, October 2013.
  3. "Monolithic 3D Advantage", Free E-book, February 2013.
  4. "Monolithic 3D - In General", Free E-book, March 2013.
  5. Obtaining Monocrystalline Semiconductor Layers for Monolithic 3D, Blog post by Israel Beinglass, the CTO of MonolithIC 3D Inc.
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