At the Future of Memory and Storage Summit in Santa Clara this week, Samsung delivered a keynote [archived copy] titled “Driving the Wave of AI Revolution: 3D Innovations in Memory & Storage Architecture.” The title is worth pausing on. The organizing idea of the largest memory roadmap in the industry is now three-dimensional integration.
The headline announcement was V10 BV-NAND [archived copy], where BV stands for Bonding V-NAND. Samsung describes it as an industry first: a NAND architecture enabled by a new wafer bonding technology, with more than 400 layers and roughly 58 percent higher density than the previous generation. Thirteen years after Samsung introduced V-NAND at the 2013 Flash Memory Summit, the company has named its next NAND generation after the bonding step that makes it possible. Bonded two-wafer construction in NAND is no longer one vendor’s approach. It is the architecture, and it is now in the product name.
Samsung also previewed zHBM, which stacks HBM directly above the AI accelerator rather than beside it, in order to minimize the distance data travels between processor and memory. Samsung projects roughly eight times the performance of HBM5, and states that with next-generation wafer bonding it can reach more than ten times the memory density, three times the energy efficiency, and less than half the thermal resistance. Two details deserve attention. The density gain is attributed to wafer bonding rather than to more through-silicon vias. And zHBM contemplates customer-specific IP placed in the interlayer between the memory and the accelerator, which makes the bonding interface itself a place where logic lives.
Readers of this blog will recognize the destination. Our 2017 IEEE S3S paper, “A 1,000x Improvement in Computer Systems by Bridging the Processor-Memory Gap,” taught that the largest remaining gains in computing were not in the transistor but in the distance between compute and memory, and that placing memory directly on logic was how to collect them. Alibaba demonstrated the numbers at ISSCC 2022 with hybrid-bonded logic-to-DRAM. Qualcomm’s June 2026 High Bandwidth Compute announcement moved the idea onto a compute vendor’s datacenter roadmap. Samsung has now placed it on the roadmap of the world’s largest memory maker, with wafer bonding named as the enabler.
The pattern documented across our Record of Invention holds: publication, skepticism, third-party demonstration, industry adoption. What is different this time is the vocabulary. Wafer bonding and vertical integration are no longer described as alternatives to scaling. They are the roadmap, and one of them is now a product name.
The headline announcement was V10 BV-NAND [archived copy], where BV stands for Bonding V-NAND. Samsung describes it as an industry first: a NAND architecture enabled by a new wafer bonding technology, with more than 400 layers and roughly 58 percent higher density than the previous generation. Thirteen years after Samsung introduced V-NAND at the 2013 Flash Memory Summit, the company has named its next NAND generation after the bonding step that makes it possible. Bonded two-wafer construction in NAND is no longer one vendor’s approach. It is the architecture, and it is now in the product name.
Samsung also previewed zHBM, which stacks HBM directly above the AI accelerator rather than beside it, in order to minimize the distance data travels between processor and memory. Samsung projects roughly eight times the performance of HBM5, and states that with next-generation wafer bonding it can reach more than ten times the memory density, three times the energy efficiency, and less than half the thermal resistance. Two details deserve attention. The density gain is attributed to wafer bonding rather than to more through-silicon vias. And zHBM contemplates customer-specific IP placed in the interlayer between the memory and the accelerator, which makes the bonding interface itself a place where logic lives.
Readers of this blog will recognize the destination. Our 2017 IEEE S3S paper, “A 1,000x Improvement in Computer Systems by Bridging the Processor-Memory Gap,” taught that the largest remaining gains in computing were not in the transistor but in the distance between compute and memory, and that placing memory directly on logic was how to collect them. Alibaba demonstrated the numbers at ISSCC 2022 with hybrid-bonded logic-to-DRAM. Qualcomm’s June 2026 High Bandwidth Compute announcement moved the idea onto a compute vendor’s datacenter roadmap. Samsung has now placed it on the roadmap of the world’s largest memory maker, with wafer bonding named as the enabler.
The pattern documented across our Record of Invention holds: publication, skepticism, third-party demonstration, industry adoption. What is different this time is the vocabulary. Wafer bonding and vertical integration are no longer described as alternatives to scaling. They are the roadmap, and one of them is now a product name.
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