We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses the starts of mass production for the industry's first 3D vertical NAND flash by Samsung.
Samsung announced today (Aug. 6, 2013) the mass production of the industry's first three-dimensional (3D) Vertical NAND (V-NAND) flash memory, which breaks through the current scaling limit for existing NAND flash technology. Achieving gains in performance and area ratio, the new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid state drives (SSDs).
Samsung's new V-NAND offers a 128 gigabit (Gb) density in a single chip, utilizing the company's proprietary vertical cell structure based on 3D Charge Trap Flash (CTF) technology and vertical interconnect process technology to link the 3D cell array. By applying both of these technologies, Samsung's 3D V-NAND is able to provide over twice the scaling of 20nm-class planar NAND flash.
"For the past 40 years, conventional flash memory has been based on planar structures that make use of floating gates. As manufacturing process technology has proceeded to the 10nm-class and beyond, concern for a scaling limit arose, due to the cell-to-cell interference that causes a trade-off in the reliability of NAND flash products. This also led to added development time and costs.
Samsung's new V-NAND solves such technical challenges by achieving new levels of innovation in circuits, structure and the manufacturing process through which a vertical stacking of planar cell layers for a new 3D structure has been successfully develop...
Also, one of the most important technological achievements of the new Samsung V-NAND is that the company's proprietary vertical interconnect process technology can stack as many as 24 cell layers vertically, using special etching technology that connects the layers electronically by punching holes from the highest layer to the bottom. With the new vertical structure, Samsung can enable higher density NAND flash memory products by increasing the 3D cell layers without having to continue planar scaling, which has become incredibly difficult to achieve”
It’s worth mentioning to the point that while the volume production of TSV based 3D IC is keep being pushed out as discussed in a recent blog: EUV vs TSV: Which one will become production ready first?, this announcement indicates that monolithic 3D NAND is biting the forecast by few years as being illustrated by the following 2012 ITRS chart:
"For the past 40 years, conventional flash memory has been based on planar structures that make use of floating gates. As manufacturing process technology has proceeded to the 10nm-class and beyond, concern for a scaling limit arose, due to the cell-to-cell interference that causes a trade-off in the reliability of NAND flash products. This also led to added development time and costs.
Samsung's new V-NAND solves such technical challenges by achieving new levels of innovation in circuits, structure and the manufacturing process through which a vertical stacking of planar cell layers for a new 3D structure has been successfully develop...
Also, one of the most important technological achievements of the new Samsung V-NAND is that the company's proprietary vertical interconnect process technology can stack as many as 24 cell layers vertically, using special etching technology that connects the layers electronically by punching holes from the highest layer to the bottom. With the new vertical structure, Samsung can enable higher density NAND flash memory products by increasing the 3D cell layers without having to continue planar scaling, which has become incredibly difficult to achieve”
It’s worth mentioning to the point that while the volume production of TSV based 3D IC is keep being pushed out as discussed in a recent blog: EUV vs TSV: Which one will become production ready first?, this announcement indicates that monolithic 3D NAND is biting the forecast by few years as being illustrated by the following 2012 ITRS chart:
Figure 2
Clearly monolithic 3D is a promising alternative to dimension scaling, as one can read in this Samsung press release. It also abides very well to the low cost objective for mass production products.
Monolithic 3D technology provides multiple unique and powerful advantages as we present on our site under the tab: 3D-IC Edge. Under item 5 we present the unique advantage that was first introduced in 2007, when Toshiba unveiled its Bit Cost Scalable (BiCS) technology. The unique advantage of 3D NAND is the ability to pattern and process multiple layers simultaneously.
This advantage comes very natural for regular layout fabrics such as memory, but it is also available for logic circuits. The driver for this advantage is the escalating costs of lithography in state of the art IC. The following charts illustrate the impact of dimensional scaling on lithography costs.
Monolithic 3D technology provides multiple unique and powerful advantages as we present on our site under the tab: 3D-IC Edge. Under item 5 we present the unique advantage that was first introduced in 2007, when Toshiba unveiled its Bit Cost Scalable (BiCS) technology. The unique advantage of 3D NAND is the ability to pattern and process multiple layers simultaneously.
This advantage comes very natural for regular layout fabrics such as memory, but it is also available for logic circuits. The driver for this advantage is the escalating costs of lithography in state of the art IC. The following charts illustrate the impact of dimensional scaling on lithography costs.
Figure 3
Figure 4
Currently critical lithography steps dominate the end device production costs as been illustrated in the following chart:
Figure 5
Accordingly, if the critical lithography step could be used once for multiple layers rather than multiple times for each single layer, then the end device cost would roughly be reduced in proportion to the number of layers processed simultaneously. Multiple memory architectures that support such drastic cost reduction has been presented in various conferences and other forums. Few of those had been presented in our blog: The Flash Industry's Direction, and MonolithIC 3D Inc.'s Solution... This dramatic announcement by Samsung comes in less than a week since we posted the blog: Monolithic 3D is now on the roadmap for 2019. It represents the beginning of a new trend for Moore’s Law – scaling up. As the memory segment of the industry shift its R&D budget and its capital equipment budget for scaling up, the shrinking camp supporting dimension scaling would need to pony up this shortage while facing escalating costs of dimension scaling. It is clear to us that the time to investigate various alternatives for scaling up has come, which also abides to the new industry roadmap recently presented.
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