Guest Contribution: Embedded Memory and Monolithic 3D

We have a guest contribution today from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. In this post, Zvi discusses the implications of monolithic 3D for embedded memories.

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Introduction

SoCs represent a significant part of the semiconductor industry ~40%. The logic market, which has SoCs and microprocessors, forms 60% of the industry.

The logic market is highly diversified and comprises hundreds of designs, yet within these devices the embedded memory portion is becoming the dominating element – see chart below:

In most cases, the embedded memory within the SoC is predominantly SRAM. In many designs, the internal memory (or as many refer to it, the eMemory) comprises hundreds of different structures, including a few large chunks of single port memories and hundreds of smaller chunks of memories, many of which are multiple port memories.

As SoC devices represent a great variety of products and market segments, there are requirements for various types of memory, including high speed, high density and non volatile. Yet due to the need for a simple manufacturing flow, the dominating memory type in most SoCs is the conventional 6 transistor SRAM.

For better illustration of the embedded memory in SoCs, lets look at embedded memory offered by Altera in their programmable devices:

The Monolithic 3D Advantage

The expected and well studied effect of monolithic 3D is the reduction of average wire length. At MonolithIC 3D™ Inc., we have develop a simulation tool –IntSim v2.0 which provides top level simulations for 2D and 3D implementation options. In most cases, for every device folding the average wire length and total silicon area will be reduced by about 50%.

An additional advantage of monolithic 3D could be achieved by placing the embedded memory in dedicated strata. Memory-only strata could be processed in a flow optimized for memory such as a DRAM flow, to allow the much better density offered by DRAM.

SoCs built with monolithic 3D could be constructed with trench capacitor eDRAM as the first stratum or stack capacitor eDRAM on the upper most stratum. Additional variation that could leverage monolithic 3D would be dual-port eDRAM. This could be done using two strata of transistors so each port may use its own transistors providing two transistors for each capacitor. This could enable user accessibility that is not impacted by refresh accessibility.

Alternatively a more advanced form of eDRAM – Floating Body DRAM (FB-DRAM) could be used. FB-DRAMs use the transistor own body as the charge holder instead of the dedicated capacitor. This form of DRAM had been suggested to save area and simplify the fabrication process. It is very appealing for monolithic 3D as multiple layers of DRAM could be stacked vertically without the bulky capacitors. Yet the FB-DRAM has yet to become an acceptable option, due to the small charge stored and the requirement for rapid refresh. The concept of dual-port could be applied to support rapid refresh with no interference with the user's use of the memory.

Additional advantage of a multi-stratum monolithic 3D SoC is the ability to have a mix of technologies while being efficient in device processing. So for applications that require a decent amount of non volatile memory, a device stratum could be dedicated to Flash memory which utilizes a fabrication flow quite different from a logic flow.

The Monolithic 3D options

MonolithIC 3D Inc. offers two flows for monolithic 3D. 

• Path 1 to Monolithic 3D: Construct recessed channel transistors in single crystal silicon, common in DRAM manufacturing, above copper interconnects at <400C.
• Path 2 to Monolithic 3D: Employ any state-of-the-art replacement gate transistor, along with repeating layouts and a novel alignment scheme, to obtain a high density of vertical connections. The advantage of this technique is its use of state-of-the-art transistor technologies.
  

Memories being a repetitive structure would work well with Path 2, while DRAMs being the proponent of RCAT transistors would also work well with Path 1.

In short the embedded memory of a 3D SoC could effectively utilize both flows for monolithic 3D fabrication.

The Continuous Array

An additional advantage of monolithic 3D SoCs, and quite a non-obvious one, is the concept we call ‘Continuous Array’. The following drawing illustrates the idea:

The drawing illustrates a stratum dedicated to a specific continuous memory array of bit cells. The idea is to process a reticle size continuous terrain of bit cells from which specific memories will be constructed. The memory peripherals could be constructed on the upper or lower strata. The continuous terrain would be customized to the specific SoC need by etching ‘borders’ around the desired memory structure as required and than connecting to the peripheral logic as required.

This concept provides significant reduction of the NRE and mask cost with benefits for low to medium production volumes.