We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the emergence of monolithic 3D technology in the near future.

The coming 2014 IEEE S3S conference (October 6-9) is first one to focus on the emergence of monolithic 3D technology. It is fitting that it would be the forum at which a key decisive breakthrough for monolithic 3D IC ("M3DI") technology will be presented. This game changing breakthrough is the first ever monolithic 3D flow that allows a fab to build a monolithic 3D integrated device while using the fab’s existing transistor process flow, without the need to develop and qualify new transistors and a new transistor formation flow.

Recent blogs such as Established Nodes Getting New Attention and Moore's Lag Shifts Paradigm of Semi Industry have articulated the building up of interest in SOI, Sub-threshold and 3D IC technologies. The IEEE S3S is the conference to learn and get updated on these technologies and M3DI is that newest part integrated into the conference. The 3D part of S3S 2014 will have a full day of tutorial presentations by leading researchers in the space, a full session of invited papers, and will conclude with a session dedicated to discussing the most recent breakthroughs in the field.

The M3DI short course will cover alternative process flows that enable M3DI, discuss the challenges and solutions to removal of the operating heat of monolithic 3D stacks, and describe the range of powerful advantages provided by M3DI. Subsequently, Prof. Sung Kyu Lim of Georgia Tech will cover EDA for M3DI. This will be followed by broad coverage of M3DI for memory applications by two leading experts in the field, Akihiro Nitayama of Toshiba/Tokohu University and Deepak Sekar of Rambus. M3DI provides unparalleled heterogeneous integration options which will be covered by Prof. Eugene Fitzgerald of MIT and SMART Lee Institute of Singapore describing the integration of silicon with other crystals for electro-optic device integration. The short course will conclude with Prof. Philip Wong of Stanford, who leads research efforts to integrate silicon with carbon nanotube and advanced 2D transistors layered with memory such as STT-MRAM and RRAM.

In the special invited 3D Hot Topics session we expect to get a full spectrum of the latest progress in the field. Particularly worth noting is the recent progress on the work done by CEA Leti with involvement of ST Micro, IBM and supported by Qualcomm. This work shows both a practical path to monolithic 3D IC and cost analysis of the monolithic 3D advantages. The following chart illustrates the reasons for the high interest in the technology.

And then there is a great dessert to this 3D feast. On Thursday afternoon, in the 3D New Developments session, a game changing breakthrough technology will be presented. Leveraging the breakthrough progress in wafer bonding technology, presenting for the first time ever a monolithic 3D flow using existing fab transistor process. Any fab could utilize this breakthrough to provide far better products at minimum capital and R&D investment. This game changing flow removes the historical differentiation between sequential and parallel 3D, and should significantly reduce the time for monolithic 3D adoption throughout the semiconductor industry.

For a postprandial enjoyment, CEA Leti will present in the Late News session a fully constructed M3DI SOI device, and IBM will present its Multi Stacked Memory Wafer technology.

More information is available on the conference site: S3S Conference 2014

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the paradigm shift in the semiconductor industry. 

In our blog 28nm – The Last Node of Moore's Law, we had pointed out that the change has happened, and it is no longer a matter of forecast or prediction. In this blog we will start by reviewing some of what has transpired since that blog, and then focus on the ensuing paradigm shift in the semiconductor industry.

The following chart was presented in the IEEE IITC workshop by Globalfoundries. It illustrates the cost impact of the double patterning required for scaling below 28/22 nm. 

Soon after Rick Merritt’s coverage of Semicon West - 13 Things I Heard at Semicon West -- Rick wrote: "Moore's Law has definitely slowed" quoting Gartner semiconductor analyst Bob Johnson."No matter what Intel says, Moore's Law is slowing down" and, Bob added, "Only a few high-volume, high-performance apps can justify 20 nm and beyond."

Soon thereafter Peter Singer, in a blog post about the ConFab 2014 –  Can we take cost out of technology scaling? -- quotes Dr. Gary Patton, VP of semiconductor research and development center at IBM: “The challenge we’re facing now is two fold. Number one, we’re struggling to get that 0.7X linear scaling. It might be about 0.8X. And we’re adding a lot more complexity, especially when you adding double and triple patterning."

And now, in early August we finaly got more information from Intel about their up coming 14nm. In our blog Intel vs. Intel we articulate that Intel’s numbers indicate that Moore’s Law had stopped at 28/22 nm both in terms of the bring-up time it takes and the cost of new technology nodes.

It is hard to accept that a trend that has held strong for 50 years, and which kept going many years after multiple predictions of its imminent demise, has really stopped. And it is even harder as we watch the huge effort of bringing up the 14 nm and 10 nm nodes. Yet it seems that everybody should agree that the semiconductor industry is now going through a paradigm shift and for most designs 28nm is, at least for some time, the last node of Moore's Law.

The following charts are well known and present the reason for that change.

It shows that the design cost increases by more than $100M from 32nm to 16nm. If we assume a die cost of $10 at 32 nm and we assume that the traditional cost reduction per node still holds, then we would need a volume of more than 20 million units just to break even. If one also considers the risk associated which such a design, it would actually require more than 100 million units, or at least $1B of market, for such device to justify the investment. Clearly, very few designs have the market for 100 million units or $1B market.
The following chart by IBS presents the past trend in design starts per node. Clearly, most new designs are still done in 130 nm while the node with the fastest ramp-up is 65 nm.

The forcast for 2016 at Semiconductor Technology Nodes – History, Trends and Forecast is illustrated in the following pie chart:

Yet again it indicates a very slow shift to more advanced nodes, and the expectationis that even in 2016 most new designs will still be done in 130nm.

This is clearly a paradigm shift in the industry, and the industry is responding accordingly.

Just prior to 2014 Semicon West, we have seen the conclusions of the SEMI’s World Fab Forecast -- Technology Node Transitions Slowing Below 32 nm. The Forecast uses a bottom-up methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. The chart below illustrates this new paradigm.

The report states: “The cost per wafer has become an increasing concern below the 32nm node.   The expected cost reduction benefit of production at smaller nodes is diminishing and is not keeping pace with the scaling benefits in many cases.  This has widespread and fundamental implications for an industry long following the cadences of Moore’s Law… These may be contributing factors as to why some volume fabs are exhibiting a lag in beginning production of a new technology node.  Now evident quantitatively for the first time, there is evidence of a clear slowdown in volume production scaling of leading technology node transitions.” (emphasis added)

This was followed by another EE Times article – Silicon Highway Narrows, Twists: “Most foundries have yet to start buying the capital equipment needed for the 14/16 nm node, which for many will be the first to support FinFETs, says Trafas of KLA-Tencor. Gear companies hope the orders start coming in the fall…Indeed, he says, one of the big questions many capital equipment execs will bring to this year's Semicon West event on July 7 is, "When will the 16/14 nm investments begin?"

In the same vein, Ed Sperling continued in Established Nodes Getting New Attention: "Work is under way to improve energy efficiency and boost performance without relying on multi-patterning or finFETs. As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors."

And a week later Samuel Wang, an analyst with Gartner, in Who’s Winning The FinFET Foundry Race? wrote: “Short-term, during the first two years of finFET production, there is no need for more than 50,000 wafers a month capacity from all foundries to satisfy the market demand for finFETs, …In the long run and before 2018, there is no need to have more than 250K wafers a month capacity to support the market demand for finFETs."    The EDA industry also is recognizing this paradigm shift. Dr. Aart de Geus in his keynote to the 2014 Synopsys User Group titled Designing Change Into Semiconductor Techonomics, recognized this shift with a series of slides articulating how EDA tools that were developed to support the new technology nodes could also benefit design efforts of old nodes:  

The IP industry is recognizing this paradigm shift as well, visible in IP Reaches Back To Established Nodes: "As SoC developers shift backward to established nodes, steps can be taken to improve the IP’s functionality. Driven by the IoT and wearable market opportunity, SoC developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality."

There also a clear effort to add value and innovation to older nodes by incorporating technology such as SOI and low Vt, known as sub-threshold designs. Most notable was the recent Samsung announcement of licensing FD-SOI from ST Micro for the established node of 28 nm. Some quotes from the articles above illustrate this trend:

* Krishna Balachandran, product marketing director for low power at Cadence. “Threshold voltage manipulation like forward biasing has been selectively used to speed up critical portions of the IP at the expense of increased leakage that is restricted to those sections of the IP without significant overall impact.”

* ARM Fellow Rob Aitken said energy savings are significant using the same exact processors differently. Moreover, it’s most effective at established process geometries where there are no finFETs. But it isn’t a simple process. (For a deeper understanding of this subject, click here). “We can get 4X to 6X improvements in energy,” said Aitken. “That doesn’t come for free, because we have to make some design changes to allow the design to operate down at this low energy point. But if we do this wrong, the overhead we have to add to get these savings is more than you get in terms of a benefit.”

* Mary Ann White, director of product marketing for the galaxy design platform at Synopsys: "Body biasing is another technique that is being recycled. It entered the picture at 90nm, when design teams found they could reduce leakage by as much as 30%. Even at 45/40nm, savings were in the 20% to 25% range. But at 28nm, the benefit for bulk CMOS dropped to as low as 2%,...When you use biasing, you are using extra tracks and extra resources, which may include one or two extra rails,” said White. “But the benefit was falling off at 28nm using planar CMOS. Interest is picking up again with FD-SOI. What’s interesting about this is we used to insert biasing at the back end, where you require a bulk n-well or p-well pin. But recently we’ve had a request to add that capability into UPF. We rolled that out with skepticism on our part, but we’ve been getting a lot of interest. If you’re adding 5% area for better power, it’s worth it.” (See related discussion.)

This paradigm shift could be a real blessing to the industry. The escalating costs drove out VCs from investing in semiconductor start-ups, drastically narrowed the number of vendors and the number of advanced new designs. It left little room for innovation or anything other than rushing to the next technology node. Now it seems that a whole new industry dynamic is taking place, innovation is being embraced, new markets are being explored, and hopefully we will see the return of VCs with the increase of semiconductor vendors and technologies.

This is also the time to pay increased attention to semiconductor technologies that could offer better intrinsic devices without traditional dimensional scaling. Most notable among those would be, SOI, Monolithic 3D, and Sub-threshold design. The 2014 S3S Conference scheduled for October 6-9, 2014, at the Westin San Francisco Airport would be a great opportunity to learn more about those technologies as it provides the latest research results along with workshops, tutorials and range of invited papers. The conference advance program is now available at < http://s3sconference.org/program/ >. It looks now to be the one conference that active members of the semiconductor industry should not miss. 

Along with many in the industry, we were pleased to see the release of Intel's 14 nm technical information on Aug. 11 - Intel Outlines 14nm, Broadwell. It does look like after an extended delay the 14 nm is coming and with it some clarity about the Intel 14 nm technology. Clearly this recent 14 nm information release is being presented by Intel to continue the historical trend of cost reduction and dimensional scaling. Undoubtedly, Intel’s 14 nm technology is a significant technological achievement and deserves full respect and appreciation. Yet, if one takes a closer look at this information, and especially with respect to prior information provided by Intel, there is room for some clarification.  

The above EE Times article provides the following numbers released by Intel on August 11:
"Compared to Intel's 22nm process, it will have:

• 42nm fin pitch, down .70x
• 70nm gate pitch, down .78x
• 52nm interconnect pitch down .65x
• 42nm high fins, up from 34nm
• a 0.0588 micron2 SRAM cell, down .54x

~0.53 area scaling compared to 22nm"
Let’s review the SRAM cell size of 0.0588µm². Yes, it is the smallest published size for a SRAM bitcell we have seen so far. Yet in our blog Intel vs. TSMC: An Update we wrote:  "Accordingly, the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² =0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm, it should be about 0.03 sq. micron or even smaller."

From Intel’s 2012 information release:

In the following table we calculated the expected bitcell size for 14nm according to simple dimensional scaling rules based on each of the bitcell sizes for each of the technology nodes in the above 2012 chart:

The above table indicates that SRAM bitcell scaling has been a challenge for some time but at 14 nm it broke totally away!

The recent Intel presentation argues for the continuation of historical scaling cost reduction to the 14 nm node as illustrated in the following Intel slide:

The graph in the middle shows the exponential increase in wafer cost with scaling; however, the argument made is that the more than 2X increase in transistor density compensates for the increase in wafer cost, resulting with the rightmost chart showing a consistent reduction in cost per transistor.

But the following Intel chart does not show a better than 2X density increase from 22nm to 14nm:

Actually the basic transistor gate pitch indicates only a x1.64 increase in transistor density.

As well, this is before accounting for the increase in RC associated with the narrower metal lines. This would require insertion of many more buffers and repeaters, further reducing the effective density increase.

Furthermore, back to the SRAM bitcell. The announced size for the Intel 14nm bitcell as presented above is not going to help offset the increase in wafer cost.

So it seems this would be a subject matter for more comments and blogs. However, I see no reasons to change my prior statements published in the EE Time blog titled: 28nm – The Last Node of Moore's Law.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the shift in semi equipment, a paradigm confirmed lately.

Our blog Paradigm shift: Semi equipment tells the future, was focused on the quote: “Now more money is spent on upgrading existing facilities, while new capacity additions are occurring at a lower pace.” And now, just prior to Semicon West, we have the conclusion of the recent SEMI’s World Fab Forecast — Technology Node Transitions Slowing Below 32 nm. The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. The following chart illustrates this new paradigm:

The report states: “The cost per wafer has become an increasing concern below the 32nm node.   The expected cost reduction benefit of production at smaller nodes is diminishing and is not keeping pace with the scaling benefits in many cases.  This has widespread and fundamental implications for an industry long following the cadences of Moore’s Law… These may be contributing factors as to why some volume fabs are exhibiting a lag in beginning production of new technology node.  Now evident quantitatively for the first time, there is evidence of a clear slowdown in volume production scaling of leading technology node transitions.” (emphasis added)

It is fitting to point to the comment made to EE Times coverage on Semicon West – 13 Things I Heard at Semicon West: “No matter what Intel says, Moore’s Law is slowing down,” said Bob Johnson, a semiconductor analyst for Gartner. “Only a few high-volume, high-performance apps can justify 20 nm and beyond.” He sees problems ahead for logic chips in general,” and to follow with quotes from another EE Times article – Silicon Highway Narrows, Twists: “Most foundries have yet to start buying the capital equipment needed for the 14/16 nm node, which for many will be the first to support FinFETs, says Trafas of KLA-Tencor. Gear companies hope the orders start coming in the fall…Indeed, he says, one of the big questions many capital equipment execs will bring to this year’s Semicon West event on July 7 is, “When will the 16/14 nm investments begin?”

Since the 65 nm node, escalating costs of fab and process technology development and design, as illustrated in the chart below, put a huge pressure on the industry.

These escalating costs drove consolidation in the industry, cutting down to a handful the vendors who are still pursuing the leading edge.

At the recent (2014) SST ConFab in Las Vegas Bill McClean shared his annual report on Major trends shaping the future IC Industry. Bill reports: “Over the last two decades, the percentage of capex being spent by the top 5 has steadily increased to its current 70% with the big three of Samsung, Intel and TSMC being responsible for over 50%.” This is illustrated by the following chart.

Clearly the escalating costs drove out most but the largest vendor, but now we are facing the ”second punch” – the diminishing returns.

In the recent ITC conference Harry J. Levinson of GlobalFoundries in his talk: Lithography Issues for High Volume Manufacturing” presented the following chart:

The dramatic increase of lithography cost eats away the historical transistor cost reduction resulting from reduced dimensions, as we reported in our blog Qualcomm: Scaling down is not cost-economic anymore – so we are looking at true monolithic 3D. Quoting Qualcomm “One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down it’s not cost-economic anymore. It’s creating a big problem for us.” Accordingly we detailed in our blog that Moore’s Law has stopped at 28nmand following nodes would not provide lower transistor cost, and for most application will result in higher SoC costs.

We should not be surprised that the production ramp up below 28 nm is extremely slow. There is too much money involved to put it into the wrong place.

Going back to the SEMI World Fab Forecast, the authors ask “What’s next?” and respond: “Many in our industry are grappling with what to do as they have perceived the coming slowdown in technology node transitions.  IC manufacturers are now increasingly looking outside of conventional lithography and wafer size scaling approaches to pick up the pace of cost reduction while increasing transistor density and performance. Using memory as an example, to cope with increasing challenges in continuing to scale 2D, memory companies are looking into 3D.”

So the memory vendors already started shifting their Capex budget to scaling up with 3D NAND, instead of scaling to smaller dimension. Recently Qualcomm announced their collaboration with SMIC – China’s SMIC-Qualcomm 28-nm Deal: Why Now? – indicating more capacity build-up for 28 nm with looking forward to scaling up with monolithic 3D for logic as well. Quoting: ”Going forward, SMIC will also extend its technology offerings on 3DIC and RF front-end wafer manufacturing in support of Qualcomm”.

It is clear now that we are seeing a paradigm shift in the semiconductor equipment industry. After many decades of relentless dimensional scaling every two years, there is a change coming and we see a lower rate of dimensional scaling and exploration of other paths, to keep industry’s march on. We do believe that the next few decades will be about scaling with 3D Integration and we are pleased to see many others thinking the same.

The 2014 S3S Conference is scheduled for October 6-9, 2014, at the Westin San Francisco Airport, and would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the latest news shared by Qualcomm.

"Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase." Speaking in a keynote at DAC 2014 in San Francisco, vice president of engineering Karim Arabi, is reported to argue that 3D and EDA need to make up for Moore’s Law.This was the third time in the past year that Qualcomm executives have made such a call at major industry conferences. At IEDM 2013 Geoffrey Yeap, Qualcomm VP of Technology, stated in his invited talk: "As performance mismatch between transistors and interconnects continue to increase, designs have become interconnect-limited. Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law." Yeap provided the following chart for the growing gap between transistor delay and interconnect delay

Earlier that year, Robert Gilmore, Qualcomm VP Engineering, in his invited talk at VLSI 2013 (Kyoto, Japan), used almost the same words and provided the following illustration (note the wafer is face-down):

Clearly there seems to be a concentrated effort by Qualcomm to promote the development and adoption of monolithic 3D.

Qualcomm has done more than just talking. It has been investing in monolithic 3D development tools with institutions such as Georgia Tech (see their GTCAD LAB website reporting technology transfer in 2012 and 2014). Qualcomm has been filing patents in this area and recently announced an agreement to work with CEA-Leti - Qualcomm to Evaluate Leti’s Non-TSV 3D Process

It would seem that the number one motivation behind these efforts is Qualcomm’s concern about future cost reductions. Early in 2012 Jim Clifford, Qualcomm's VP and GM (at that time), in his plenary talk at the SPIE conference titled - A Mobile Wireless Phenomenon: A Continued Need for Advanced Lithography, made it very clear with his second slide. At that time there were already some concerns with EUV’s rollout schedule. Jim called on the conference attendees to make sure to solve the escalation of advanced lithography cost, which was already dominating more than 50 % of the overall advanced device cost. Jim presented the following curve, showing the historical 29% cost reduction per year, and the looming problem with the production cost beyond 28 nm.

 Jim than said: "If the next node doesn't cost less than the last node we got a problem because I don't think the demand will be there." Well it is now clear that EUV is not ready and that dimensional scaling below 28nm will require double and triple lithography with its associated extra costs.

Back to the DAC 2014 keynote: Arabi explained: “Mobile is becoming a centre of gravity for the user. It is providing a unique opportunity ... but it becomes a challenge to develop because you have to integrate them at lower power and low cost as well ... One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down, it’s not cost-economic anymore. It’s creating a big problem for us.” As we reported in our recent blog, 28nm – The Last Node of Moore's Law, dimensional scaling below 28 nm will result in increasing device cost. This was echoed multiple times at this DAC by other keynote speakers such as Hossein Yassaie, CEO of Imagination Technologies, who said: “Moore’s Law is really over from my point of view. It’s not that it can’t scale, it’s that the cost is not going down anymore".

 And cost is not the only problem with dimensional scaling. The following IBM slide illustrates that interconnect now dominates device power.   

Interconnect’s effect on power is just getting worse with dimensional scaling. Arabi also stated in his DAC keynote: “Interconnect RC is inching up as we go to deeper technology. That is a major problem because designs are becoming interconnect-dominated. Something has to be done about interconnect. What needs to be done is monolithic three-dimensional ICs ... So we are looking at true monolithic 3D. You have normal vias between different stacks. Then interconnect lengths will be smaller than with 2D. If we can connect between layers the delay becomes smaller. This is a technology for the end of the decade, but it can give us an advantage of one process node, with a 30 per cent power saving and a 40 per cent gain in performance.”

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology with 5 invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories, CEA Leti will present their work on CMOS monolithic 3D IC, and researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the latest news in support of monolithic 3d.

Over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D "to extend the semiconductor roadmap way beyond the 2D scaling" as part of their keynote presentations.  
Karim Arabi, Qualcomm VP of Engineering, voiced the strongest support and provided many details of monolithic 3D’s role, in his keynote at this year’s DAC. A good summary was posted at the Tech Design Forums site under the title "3D and EDA need to make up for Moore’s Law, says Qualcomm". In this blog I’ll highlight some of the very interesting quotes from Arabi’s keynote: "Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase...One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down, it’s not cost-economic anymore"

Karim Arabi, Qualcomm VP of Engineering, voiced the strongest support and provided many details of monolithic 3D’s role, in his keynote at this year’s DAC. A good summary was posted at the Tech Design Forums site under the title "3D and EDA need to make up for Moore’s Law, says Qualcomm". In this blog I’ll highlight some of the very interesting quotes from Arabi’s keynote: "Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase...One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down, it’s not cost-economic anymore"

Qualcomm is not the only fabless company voicing its concern with cost. Early in 2013 Nvidia said it is "deeply unhappy" and executives of Broadcom followed suite. The following chart, presented by ARM, illustrates it nicely.

But it seems that the problem is even more severe than that. In our blog Moore’s Law has stopped at 28nm we examined the expected increase of SoC cost due to poor scaling of embedded SRAM (eSRAM). We should note that the chart above, like many others, is about the cost per transistor associated with dimensional scaling. Escalating lithography cost causes escalating wafer cost, which neutralizes the 2X transistor density increases.

Yet eSRAM scales far less than 2X and, accordingly, for most SOCs, scaling would be even more costly. This issue has been confirmed again with the recent VLSI 2014 paper "10-nm Platform Technology Featuring FinFET on Bulk and SOI" by Samsung, IBM, STMicroelectronics, GLOBALFOUNDRIES and UMC. They presented that the size of their 10 nm bitcell is 0.053 µm², which is only 25% smaller than the 0.07 µm² reported for 14 nm bitcell size. One should expect that an additional area penalty would occur for effective use in large memory blocks, as reported even for 14nm, which could bring the effective SRAM scaling to only about 15%, a long way from the 50% required to neutralize the escalating wafer costs. 

However, cost is not the only issue that forced Qualcomm to consider monolithic 3D. Quoting Arabi:
“Interconnect RC is inching up as we go to deeper technology. That is a major problem because designs are becoming interconnect-dominated. Something has to be done about interconnect. What needs to be done is monolithic three-dimensional ICs. Through-silicon vias and micro bumps are useful where you need I/Os ... But they are not really solving the interconnect issue I’m talking about ... So we are looking at true monolithic 3D. You have normal vias between different stacks. Then interconnect lengths will be smaller than with 2D. If we can connect between layers the delay becomes smaller." 

The interconnect issue was also addressed at IEDM 2013 by Geoffrey Yeap, Qualcomm VP of Technology, in his invited talk:
"As performance mismatch between transistors and interconnects continue to increase, designs have become interconnect-limited. Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law."
Yeap provided the following chart for the growing gap between transistor delay and interconnect delay:

Arabi DAC 2014 keynote was also reported on Cadence’s website, which provides our final Arabi quote for this blog: Qualcomm is looking at "monolithic" 3D-ICs that use normal vias between stacked dies. This can provide a one-process-node advantage along with a 30% power savings, 40% performance gain, and 5-10% cost savings.

Clearly, monolithic 3D integration has a very important role in the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with 5 invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC, and researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the FPGA as ASIC Alternative. 

In our recent blog 28nm – The Last Node of Moore's Law we outlined the recent dramatic change that has happened after many years of cost reduction associated with dimensional scaling. It is clear now that 28 nm will provide the lowest cost per gate for years to come. In this blog we will assess the potential implications for the ASIC and the FPGA markets. Over the last two decades we have seen escalating mask set costs associated with dimensional scaling and accordingly escalating NRE costs. At the recent 2014 SEMI Industry Strategy Symposium (ISS) Ivo Bolsens, Xilinx CTO, presented the following chart of ASIC design cost escalation: 

The dramatic increases of ASIC design cost have had a real effect on the ASIC market, reducing the number of new designs and dramatically reducing the number of vendors serving the ASIC market.

One would expect that such a trend would have a very positive effect on the FPGA market, as there is no mask-set cost associated with an FPGA design and, accordingly, far lower NRE costs per design. The following fictitious chart presented in the EE Times article: What’s the number of ASIC versus FPGA design starts?, illustrates these expectations.

Surprisingly, this did not really happen. The following chart presents the overall FPGA market during the last decade according to the financial results of Xilinx, Altera and Actel.

The FPGA market growth could be compared to the overall semiconductor market growth as presented in the chart below (the market in 2013 was $305B). Clearly the FPGA market growth during the last decade is similar to the overall semiconductor market growth, and there is no indication of any benefits from the escalating ASIC mask-set cost and its associated NRE.

The FPGA technology started in the mid-1980s as an alternative to the popular ASIC technology then – the Gate Array. The acronym FPGA stands for Field Programmable Gate Array. During the 1990s the Gate Array technology lost its appeal and the ~$20B Gate Array market shrunk dramatically and effectively ceased to exist. Analyst expected that this will have a dramatic positive impact on the FPGA market, which did grow some but far from the expectations. The trend of escalating NRE driven by dimensional scaling and escalating lithography costs kept on going in the 2000s and drove down the number of ASIC designs. And, again, analysts expected a huge surge in the FPGA market. Clearly, this did not happen. 

In the following we will present our theory why it did not happen and some potential implications for the future.

We believe that the stagnation of FPGA growth is mostly due to the inefficiency of the FPGA technology. Most FPGAs use SRAM as the programming or ‘switch’ technology. Interconnects are the dominating resource in modern designs. Within an SRAM based FPGA the programming of interconnects is implemented by an SRAM cell control of a pass transistor, driver, or bidirectional driver. The following chart illustrates the diffusion area associated for such Programmable Interconnect Cell (PIC) assessed in 45nm technology and compared to the size of mask-defined equivalent – the via. The results indicate that the cell area overhead for the SRAM PIC is over 30X when compared to a via, which does not include the additional circuit overhead area needed to program and control the SRAM PIC.

This number had been reported in the industry for many years. A 2007 research paper by Ian Kuon and Prof Jonathan Rose (IEEE Transaction on Computer-Aided Design of IC and System) says this clearly: “In this paper, we have presented empirical measurements quantifying the gap between FPGAs and ASICs for core logic. We found that for circuits implemented purely using the LUT based logic elements, an FPGA is approximately 35 times larger and between 3.4 to 4.6 times slower on average than a standard-cell implementation.”

This high programmability overhead suggests that many of the current ASIC designs cannot be replaced by an FPGA design. Consequently, when advanced technology NRE is too high, the alternative is to use older node ASIC technologies. Since the number one driver for cost of mask-sets and NRE is the associated capital, the cost of older technologies goes down dramatically over time. The 30X area penalty means that one could use a node that is five generations older and have a competitive solution when compared to current node FPGA. Taking into account the 60% gross margin of the FPGA companies and the overhead of using a fixed-sized device of an FPGA family rather than a custom tailored Standard Cell device, these could compensate for an additional two nodes. Looking again at the design costs as illustrated in the Xilinx chart above, we can see that at 180 nm the design costs are pretty low and the mask set costs are too small even to register on the chart.

What has really happened is that many designs chose to use older node standard cells instead of an FPGA. In his last keynote presentation at the Synopsys user group (SNUG 2014) Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys newer tools to improve older node design effectiveness. The following chart is one of them and it also includes in its left side the current distribution of design starts. One can easily see that the most popular current design node is at 180nm. Clearly even such old node provides a better product than the state of the art FPGA.  

Now we understand why the escalating mask set and NRE costs have not resulted in a surge of FPGA designs but rather pushed designers to user older technology nodes that had depreciated enough to make their NRE cost less of an issue. The following chart of Design Starts per Node by IBS was recently presented in a Synopsys article "The new landscape of advanced design". It shows the design starts trend over time and, not surprisingly, indicates that designers migrate to more advanced nodes over a longer time and that the up and coming node these days is just 65 nm.

Recently EE Times published our blog, 28nm – The Last Node of Moore's Law. In it we presented that the 28nm node will be the end of cost reduction for dimensional scaling. Most analysts accept by now that 28 nm is going to be the lowest cost per gate for many years to come. 

There are potentially many implications of this change in Moore’s Law. One of those implications could affect the future of FPGAs.
Traditionally FPGAs have been, and still are, a technology driver of new logic technology nodes. This early adoption gave the FPGA customer a constantly better programmable platform for their designs. Now that dimensional scaling does not provide better cost, it will result in a build-up of pressure for FPGA customers to use a depreciated technology node as an alternative. Over time designers would see the NRE of 65nm going down to about what the 180nm NRE is today. Comparing a 65nm Standard Cell design to an FPGA of 28nm suggests that far more designs could be better off with Standard Cell. As 20 nm and 14 nm FPGAs would not provide a better cost than the 28 nm one, it means that the FPGA market could see a growing challenge in the coming years. 
 
Designers chose older nodes not just for its lower mask-set and NRE costs but also for availability of broader embedded options such as flash memories and analog cells. But those are becoming available on newer nodes over time as well. The 65 nm node is now ramping up and would become the preferred choice for new designs in a few years, as its mask-set cost and NRE keep going down thanks to deprecation and broader availability. As volume production of older designs winds down, vendors are reducing their costs to bring new designs in, and will soon make the 65 nm as easy to access as 180 nm is now. FPGA vendors will release newer products on 20nm and 14nm but those would not offer lower production costs than the 28 nm FPGA products and will be less and less competitive versus a ‘not too old’ technology node such as 65 nm. It only seems logical that these new semiconductor industry dynamics will have a negative effect on the FPGA market and a positive effect on ASIC and Structured ASIC technologies. 

Thus it behooves us to consider what can the FPGA vendors do to keep their business growth.
Interestingly, the same trend that now works against FPGA technologies could be used to improve their competitiveness. In the early days two major FPGA technologies were competing in the market. The SRAM technology and the anti-fuse technology. The SRAM technology had higher switch overhead, but ended up winning because it benefitted from two major advantages. First, it did not need any major process changes and could be adapted to newer nodes as soon as those could be fabricated. Second was their ability to reprogram the device over and over again. Now that new process nodes do not provide lower costs, FPGA vendors could look to other than SRAM technology as a new path to improve their programmable platforms. As for anti-fuse, the significant effort in recent years to develop RRAM technology opens the possibility of adopting antifuse technology that could offer re-programmability. Even more important is the fact that re-programmability these days is far less important as all FPGA designs utilize simulation technology and other EDA tools, as the trial and error methodology no longer can be effectively used for modern designs. 

A special type of antifuse programmable technology could be most effective – Antifuse-based 3D High Density FPGA. This type of programmable fabric leverages anti-fuse metal to metal technology, which use 3D transistors for programming the anti-fuses. The 3D transistors could handle the higher voltage required for the programming and provide the interconnect programming with minimal device density impact. The 3D anti-fuse programmable fabric density is very similar to a via programmable fabric. Via programmable fabrics has been used with structured ASICs such as those offered by eASIC and Triad Semiconductors (ViASIC). They provide a programmable fabric with about a 2X area penalty vs. mask-defined standard cell technologies. These antifuses could be made as one time or reprogrammable devices and be fully replaced by mask-defined vias for even lower cost volume production, as illustrated by the following chart

Going forward, the semiconductor industry needs to go through fundamental change. No longer is it sufficient to scale using the next node of dimensional scaling to provide better overall device value. From the 28 nm node going forward, the industry needs to open up for a broad range of innovation so to continue offering better products. We can only hope that this will drive the industry back to fast growth and support the future market of Internet-of-Things and Internet-of-Everything.

We have been hearing about the imminent demise of Moore’s Law quite often recently. Most of those predictions have been targeting the 7nm node and 2020 as the end point. But we need to recognize that 28nm is actually the last node of Moore's Law, beyond which we can make smaller transistors and pack more of them into the same die size but we can not reduce the cost, and in most cases, the same SoC will have a higher cost!

The famous Moore's Law was presented as an observation by Moore in his 1965 Electronics paper "The future of integrated electronics". Quoting: "The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years." Clearly Moore's Law is about "The complexity for minimum component costs", and the minimum component cost will be at the 28nm node for many years, as we will detail in the remainder of this blog.

The following chart was presented by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during Semi’s recent ISS 2014 Europe Symposium:

Hartmann is making the case that the "Moore's Law discontinuation due to cost stagnation or increase" applies to bulk technologies, which is the technology base of the majority of the industry.

ST information is backed by Globalfoundries as we can see from the following chart presented at the 2013 SOI Consortium workshop in Kyoto, Japan.

The above Globalfoundries chart shows that the lowest cost transistor is at the polySiON 28nm node.

Beyond 28nm, scaling becomes extremely expensive due to double litho, HKMG, FinFET, etc. The increase in wafer cost is illustrated by the recent NVidia chart from Semicon Japan (Dec. 2013) below:

The increase in wafer cost eats away the 2X transistor density gain per node as is illustrated by this ASML slide from Semicon West (2013):

However, the SoC end product silicon area is dependent on the SRAM bit cell size far more than on the general transistor density. This is the fundamental challenge now facing dimensional scaling - SRAM Bit scaling has been dramatically slowed beyond 28nm.
At 28nm the bitcell size is about 0.12µm². The following chart by imec reported in Status update on logic and memory roadmaps (Oct 2013):

Beyond 28nm, the SRAM bit scaling rate is about 20% per node instead of the historical 50%. And the situation is actually far worse as is illustrated by the following chart, presented in an invited paper by Dinesh Maheshwari, CTO of Memory Products Division at Cypress Semiconductors, at ISSCC 2014. It was also at the center of our recent blog "Embedded SRAM Scaling is Broken and with it Moore's Law."

Accordingly, the SRAM Mb/mm² scales far less than the bitcell due to factors such as:

• Smaller transistors have less drive, thus requiring breaking the SRAM into smaller blocks, creating more overhead area costs
  
• Smaller transistors have a higher level of variation, also requiring breaking the SRAM into smaller blocks
  
• The need for more overhead such as read assist circuits and write assist circuits
  
• Tighter metal pitches begat higher RC, thus again requiring breaking the SRAM into smaller blocks
  

Moreover, SoCs need I/O pads and their circuits, and other analog circuitry, all of which scale at a rate far less than 2x per node.

Furthermore, the exponential increase in BEOL RC as is illustrated by the following chart, presented by Geoffrey Yeap, VP of Technology at Qualcomm in his invited IEDM 2013 paper, results in an exponential increase of number of drivers and repeaters. This suppresses the effective gate density increase to only a factor of x1.6, or less.

Summarizing all of these factors, it is clear that for most SoCs, the 28nm will be for the coming years the node for "minimum component costs".

As an industry, we are facing a paradigm shift because dimensional scaling is no longer the path for cost scaling. New paths need to be explored such as SOI and monolithic 3D integration. It is therefore fitting that the traditional IEEE conference on SOI has expanded its scope and renamed itself to IEEE S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This new unified conference will help us to improve efficiency and establish this conference as a world class international venue to present and learn about the most up-to-date trends in CMOS and post-CMOS Scaling. The conference will provide both educational and cutting edge research in SOI and monolithic 3D and other supporting domains. These technologies were not part of the mainstream semiconductor past; accordingly, it is a golden opportunity to catch-up with these technologies now. Please mark your calendar for this opportunity to contribute and learn about SOI and monolithic 3D technology, as these technologies are well positioned to keep the semiconductor industry's future momentum.

The chart below was presented at ISSCC 2014 by Dinesh Maheshwari, CTO of Memory Products Division at Cypress Semiconductors. The slide clearly illustrates that embedded SRAM ("eSRAM") scaling is broken. 

Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let’s discuss it further.Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let’s discuss it further.
The following slide was presented by Intel at their recent analyst day. It illustrates the impact of dimensional scaling on advanced wafer cost ($/mm²) mostly due to the escalating cost of lithography. Intel believes it can compensate for this exponential wafer cost increase by increasing their transistor density (mm²/transistor) to maintain historical cost reduction of transistor cost ($/transistor).

Perhaps it can, but at this time we keep hearing about delays in ramping up the 14nm line. (See "Broadwell Coming, but Not Until the End of the Year.") This reminds us of the famous joke, "Will make it on the volume," since increasing transistor density is directly related to the aggressive dimensional scaling that was driving the escalating wafer cost in the first place.

Most industry players confirm that cost-reduction for transistors has stopped beyond the 28nm process node, as is illustrated by the ASML chart below. This chart was presented at SEMICON West 2013.

It also clear that EUV is not going to be ready for the 16/14nm node. In fact, most observers are in agreement that EUV will also miss the 10nm node.

For some applications, keeping the cost-per-transistor about the same while reducing power or increasing speed might still justify going to 20nm or 14nm. The IMEC/Cypress chart above indicates that this will not be true for most designs. The fraction of the die area used for eSRAM is consistently growing with scaling, and it already regularly exceeds 50%. The following two charts from Semico, which were recently updated, illustrate this for advanced SoC and average SoC implementations.

Taking into account that 16/14 nm silicon is almost twice as expensive per unit area as that of 28 nm, this implies that beyond 28nm, SoC costs for the same functionality will escalate for most designs, and this will dampen even further the transition to advanced nodes such as 20nm or 16/14nm!

This clearly seems to indicate a paradigm shift after 50 years of consistent cost-reduction with dimensional scaling. Indications of this were already presented in our blog, Paradigm Shift: Semi Equipment Tells the Future, and in recent news articles such asAnalysis: ASML Stops 450mm Dead and Intel Cancels Fab 42.

Some people will attempt to brush aside Maheshwari's chart shown above, yet multiple sources indicate this is a true new reality that should not be ignored. We first reported it in our blog on ASML at Semicon West 2013, SRAM Scaling Has Stopped, which was backed up by the following IMEC chart as reported in Status Update on Logic and Memory Roadmaps.

This IMEC chart shows that the reduction of eSRAM bitcell area below 28nm is much less than the 50% expected size-reduction per technology node.

Furthermore, TSMC reported at IEDM 2013 that their bitcell for 16nm is 0.07µm2, and at ISSCC2014 Samsung presented similar results for 14nm finFETs as shown in the following slide.

It appears that the TSMC and Samsung bit cell sizes are in line with the IMEC table presented above. It also appears that these trends become even worse when comparing the size of high performance block RAM between technology nodes as presented by Maheshwari.

In the case of block RAM, additional aspects need to be taken into consideration, such as the die size impacts required for implementing a new technology such as finFET. In its ISSCC 2014 paper, Samsung identified complications involved with the transition from planar to finFET, such as quantized width, strong PMOS, and a lack of the body-bias effect. Samsung disclosed a die size impact of 0.87% in order to add a Disturbance Noise Reduction (DNR) scheme to deal with its larger, more stable High Performance (HP) bit-cell. Samsung did not disclose the area impact of its proposed Negative Bitline write assist scheme used with their high density HD bit-cell, but we can assume it is likely significantly larger than the proposed scheme for the HP bit-cell.

Some of the issues that are holding back scaling eSRAM were presented in our recent blog: The Most Expensive SRAM in the World -- 2.0. Bitcell scaling is getting harder, much harder, and even more so is the ability to scale large blocks of embedded SRAM. When we add the fact that the amount of embedded memory is growing faster than the amount of logic cells, one can predict dark clouds for SoC scaling beyond 28nm. It seems that brute-force scaling is simply not practical anymore, but two technology innovations could solve the SRAM memory scaling problem and provide a scalable high density memory if adopted soon by the industry.

The first innovation is the One-Transistor SRAM (1T SRAM) developed by Zeno Semiconductor. This 1T SRAM utilizes an existing fab process, provides a 90% bitcell size reduction versus conventional 6T SRAM, and it will keep scaling beyond 28nm. The second innovation is that of monolithic 3D, which enables a very effective heterogeneous integration scheme, thereby allowing for the SRAM layer to be optimized for memory while the logic layer can be optimized for logic. (See Monolithic 3D eDRAM on Logic.)

So, what do you think? Do you still believe that traditional scaling is the way to go? Or do you think that we will need to rely on new technologies like 1T-SRAM and monolithic 3D in order to maintain the pace of SoC development?

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the latest news in semiconductor industry, the headlines that dominated last week's news papers about TSMC and Intel. 

 On January 14, 2014 we read on the Investors.com headlines page - Intel Seen Gaining Huge Pricing Advantage Over TSMC. Just three days later comes the responding headline: TSMC: We're "Far Superior" to Intel and Samsung as a Partner Fab.
These kinds of headlines are not seen too often in the semiconductor business domain and it is not clear what the objectives are for such. It will be hard to believe that this is an attempt to manipulate the investor community, yet there are only a handful of super high volume design wins that are driving the leading edge devices, and for those wins the fight should be taking place in the 'board' room. So let’s dive a bit into the details behind these headlines.
 The first headline relates to Jefferies analyst Mark Lipaci releasing an analysis report stating: "Intel will have a die size and transistor cost advantage over Taiwan Semiconductor (TSM) for the first time by fourth-quarter 2014, which could lead to a 50% pricing advantage in processors in 12 months, and a 66% pricing advantage in 36 months". We can find more information in the blog titled: Intel: Primed for Major Phone, Tablet Share on Cheaper Transistors, Says Jefferies. Quoting Lipaci: "At the same time that Intel has started focusing on computing devices in mobile form factors, it appears that TSMC is hitting a wall on the transistor cost curve. The chart below was presented by TSMC’s CTO. We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC for the first time ever in 4Q14. We believe Intel extends that cost lead 24 months after than in 2016."
Lipaci then used the following chart to illustrate the build up of Intel advantage vs. TSMC.

The Jefferies report goes further and provides the following charts for 14nm and 10nm.

 Clearly the primary advantage that the report is pointing out is the lack of the double margin associated with the foundry model vs. the IDM model. It seems that this argument has clearly been disproven by now. In the early days of the foundry industry most IDMs would argue that the foundry model would not work because of the double margin aspect - the foundry would need about 50% gross margin and then the fables company would need an additional 50% gross margin - which would make it completely uncompetitive vs. the IDM. 20 years later it was proven, again, that there is no "free lunch". The chip fabrication business needs a margin to be sustainable and the design business needs a margin to be sustainable. And the better business model is to have those managed by different companies as each could build excellence in its own value proposition. Intel did enjoy for many years effective exclusivity in the Windows based processors. Intel has not been able so far to show much success in mobile or any other non-Windows market. Since Intel is now trying to position themselves as a better foundry than TSMC, then clearly for their potential foundry customers this double margin argument is moot.  
 The charts above also compare Intel’s cost advantage vs. TSMC older nodes (Intel's 14nm vs. TSMC's 20 nm and Intel's 10nm vs. TSMC's 16nm). It is not clear that Intel is so far ahead. Intel 14nm had been delayed to the first quarter of 2014 and TSMC has committed to be in volume production in the later part of 2014. But the real competition is on the ability to bring fabless companies to volume using one's advanced process node. Key to this is the availability of libraries, EDA full tool set support, and major IP such as ARM processors. It is far from being clear that Intel is really far ahead of TSMC in this critical area. And then, these days it is not so clear that using a more advanced process node buys one an end-device cost advantage. In fact, the foundries have already made it clear that beyond the 28nm node they do not see cost reduction, due to the extra cost associated with advanced node lithography and other issues. Even Intel admitted at their latest analyst day that advanced nodes are associated with escalating depreciation and other costs, as illustrated by the following Intel chart - see the left most graph.

We should note that the Y axes of these graphs are logarithmic which indicate a significant increase of deprecation costs. However, Intel claims it will more than neutralize this increase of costs by accelerating the dimensional scaling when going to 14nm and 10nm, as is presented with the middle graph above. This would lead to an overall sustaining of the historical cost per transistor reduction as is illustrated by the rightmost graph above. Note: the asterisk (*) on those graphs indicates that numbers relating to 14nm and 10nm are forecasts only. Since Intel is committed to be in volume production at the 14nm node any day now, the number associated with 14nm should not be a forecast anymore and we hope to see them released soon.

The simple indication of technology node effective transistor density these days would be the bit cell size. As we have presented many times before, modern SoC device area is dominated by the embedded 6T SRAM. At IEDM 2013, TSMC made public their 6T SRAM bit cell area for 16nm: 0.07 sq. micron. We could not find any Intel public release for their 14nm 6T SRAM bit cell size. We did find an Intel chart for older nodes. This 6T bit cell size chart was presented at IDF2012:

Accordingly the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² = 0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm should be about 0.03 sq. micron or even smaller. As we don't have any official number we could wait until their early production devices of the 14nm node get analyzed or to the eventual release of their number. But short of an official number, we did find a 2013 presentation from the TRAMS project, of which Intel is a partner, as illustrated in the following charts:

It is now clear that EUV will not be available for the 14nm node, and accordingly the bit cell size from the chart above is 0.062 sq. micron. This is a bit better than that of TSMC but a far cry from 0.03 sq. micron.

If Intel does have a really good number, it would be reasonable to expect that they will make it public soon, to entice the high volume fabless companies such as Qualcomm and Apple to explore Intel’s foundry option.


As for the Jefferies analyst assertion "We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC", it is not clear if Intel’s R&D budget is truly larger. TSMC’s R&D budget is dedicated to the foundry side of the business while Qualcomm, Apple, ARM and many other fabless vendors R&D budgets support the design part of any new product release. The total ecosystem behind TSMC and ARM is clearly not smaller than that of Intel. In this month’s SEMI ISS Conference, IC Insights provided very interesting numbers regarding the record of 2013 as was reported in a blog titled:Is Intel the Concorde of Semiconductor Companies?


Top 10 CAPEX Spenders in 2013:

1. Samsung $12B
   
2. TSMC $11.2B
   
3. Intel $10.5B
   
4. GF $5.5B
   
5. SK Hynix $3.7B
   
6. Micron $3B
   
7. Toshiba $2.9B
   
8. UMC $1.5B
   
9. Infineon $880M
   
10. ASE (OSAT) $770M
    

Yes, Samsung and TSMC both outspent Intel. Just wait until you see the capacity numbers and you will know why.

Top 10 IC Wafer Capacity Leaders in 2013:

1. Samsung 12.6%
   
2. TSMC 10%
   
3. Micron 9.3%
   
4. Toshiba 8%
   
5. SK Hynix 7%
   
6. Intel 6.5%
   
7. ST 3.5%
   
8. UMC 3.5%
   
9. GF 3.3%
   
10. TI 3.0%
    

Clearly Intel is not larger than TSMC as a foundry and it is not clear why would it have a sustainable per transistor cost advantage.

Cost is important but it is far from being the only parameter when choosing a foundry partner. Selecting a foundry partner is truly selecting a partner. The design of leading edge devices is a very costly and lengthy effort, and has a pivotal effect on the business success for the fabless customer. TSMC had built trustful relationships for many years with its fabless customers. It is not clear how easy it is going to be for Intel to become a trustful foundry partner. So far it seems that Intel is still a proud IDM that insists that its customer will support its branding like the "Intel Inside" campaign or the recent announcement of Branding the cloud: Intel puts its stamp on cloud services across the globe. Intel’s repeating emphasis of their transistor cost advantage vs. that of TSMC suggests that Intel considers TSMC as their main competition for the mobile and tablet business. But then their consistent offering of SoC products for the space, as illustrated by the recent Intel chart below, and the Jefferies' cost analysis above, suggests that Intel is actually an IDM competing with the likes of Qualcomm in this space. It may create concerns in the minds of potential fables customers.

And as a final note, we don't know how much better the Intel process at 14nm and 10nm is vs. that of TSMC. We do know that when we ask someone for directions, if he says ‘make a right turn’ but with his hand he is pointing left, we should go ahead and turn left. So along with all of these confusing statements we learned just this week that Intel Cancels Fab 42, which was supposed to be the most advanced large capacity fab effort of Intel. I wonder if it should be considered as the hand pointing....