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3D-IC: Two for one

9/26/2013

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi details MonolithIC 3D Inc's participation at the upcoming events in 3D IC field and the key role of the company in each event.

This coming October there are two IEEE Conferences discussing 3D IC, both are within an easy drive from Silicon Valley.

The first one is the IEEE International Conference on 3D System Integration (3D IC), October 2-4, 2013 in San Francisco, and just following in the second week of October is the S3S Conference on October 7-10 in Monterey. The IEEE S3S Conference was enhanced this year to include the 3D IC track and accordingly got the new name S3S (SOI-3D-Subthreshold). It does indicate the growing importance and interest in 3D IC technology.

This year is special in that both of these conferences will contain presentations on the two aspects of 3D IC technologies. The first one is 3D IC by the use of Through -Silicon-Via which some call -”parallel” 3D and the second one is the monolithic 3D-IC which some call “sequential.”

This is very important progress for the second type of 3D IC technology. I clearly remember back in early 2010 attending another local IEEE 3D IC Conference: 3D Interconnect: Shaping Future Technology. An IBM technologist started his presentation titled “Through Silicon Via (TSV) for 3D integration” with an apology for the redundancy in his presentation title, stating that if it 3D integration it must be TSV!

Yes, we have made quite a lot of progress since then. This year one of the major semiconductor research organization – CEA Leti – has placed monolithic 3D on its near term road-map, and was followed shortly after by a Samsung announcement of mass production of monolithic 3D non volatile memories – 3D NAND.

We are now learning to accept that 3D IC has two sides, which in fact complement each other. In hoping not to over-simplify- I would say that main function of the TSV type of 3D ICs is to overcome the limitation of PCB interconnect as well being manifest by the well known Hybrid Memory Cube consortium, bridging the gap between DRAM memories being built by the memory vendors and the processors being build by the processor vendors. At the recent VLSI Conference Dr. Jack Sun, CTO of TSMC present the 1000x gap which is been open between on chip interconnect and the off chip interconnect. This clearly explain why TSMC is putting so much effort on TSV technology – see following figure:

Figure 1: System level interconnect gaps

On the other hand, monolithic 3D’s function is to enable the continuation of Moore’s Law and to overcome the escalating on-chip interconnect gap. Quoting Robert Gilmore, Qualcomm VP of Engineering, from his invited paper at the recent VLSI conference: “As performance mismatch between devices and interconnects increases, designs have become interconnect limited. Monolithic 3D (M3D) is an emerging integration technology that is poised to reduce the gap significantly between device and interconnect delays to extend the semiconductor roadmap beyond the 2D scaling trajectory predicted by Moore’s Law…” In IITC11 (IEEE Interconnect Conference 2011) Dr. Kim presented a detailed work on the effect of the TSV size for 3D IC of 4 layers vs. 2D. The result showed that for TSV of 0.1µm – which is the case in monolithic 3D – the 3D device wire length (power and performance) were equivalent of scaling by two process nodes! The work also showed that for TSV of 5.0µm – resulted with no improvement at all (today conventional TSV are striving to reach the 5.0µm size) – see the following chart:

Figure 2: Cross comparison of various 2D and 3D technologies. Dashed lines are wirelengths of 2D ICs. #dies: 4.

So as monolithic 3D is becoming an important part of the 3D IC space, we are most honored to have a role in these coming IEEE conferences. It will start on October 2nd in SF when we will present a Tutorial that is open for all conference attendees. In this Monolithic 3DIC Tutorial we plan to present more than 10 powerful advantages being opened up by the new dimension for integrated circuits. Some of those are well known and some probably were not presented before. These new capabilities that are about to open up would very important in various market and applications.

In the following S3S conference we are scheduled on October 8, to provide the 3D Plenary Talk for the 3D IC track of the S3S conference. The Plenary Talk will present three independent paths for monolithic 3D using the same materials, fab equipment and well established semiconductor processes for monolithic 3D IC. These three paths could be used independently or be mixed providing multiple options for tailoring differently by different entities.

Clearly 3D IC technologies are growing in importance and this coming October brings golden opportunities to get a ‘two for one’ and catch up and learn the latest and greatest in TSV and monolithic 3D technologies — looking forward to see you there.

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MonolithIC 3D Inc. at IEEE International Conference on 3D System Integration (3D IC)

9/10/2013

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Join MonolithIC 3D Inc. at IEEE International Conference on 3D System Integration (3D IC) on October 2nd -4th, 2013 in San Francisco, CA. Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. will present a guest tutorial on 3D IC edge. The company will also give the presentation: “Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC” in session VII of the event. You can access the Technical Program of the Conference here.

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. will be featured as guest speaker to present a tutorial on Monolithic 3D IC. The tutorial describes the advantages of monolithic 3d as an alternative to maintain the exponential increase in integration. Some of the advantages of this technology include reductions of cost, decreases in power consumption, and improvements in performance, and bring some new and compelling benefits like:

Continuing reductions in die size and power,
Significant advantages for reusing the same fab line and design tools,
Heterogeneous Integration
Processing multiple layers simultaneously, offering multiples of cost improvement
Logic redundancy, allowing 100x integration at good yields
Modular Platforms

“Monolithic 3D is a disruptive semiconductor technology. It builds on the existing infrastructure and know-how, and could bring to the high tech industry many more years of continuous progress. While it provides the advantages that dimensional scaling once provided, monolithic 3D offers many more options and benefits. And the best of all is that it could be done in conjunction with dimensional scaling. Now that monolithic 3D is practical, it is time to augment dimensional scaling with monolithic 3D-IC scaling.”

Even more, the company will also give a presentation in session VII on a new path for monolithic 3D IC: “Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC”. This work was done in collaboration with the Department of Electrical Engineering, IIT Bombay, India.

Abstract of presentation: Classical dimensional scaling faces challenges from growing on-chip interconnect time delays, and escalating lithography costs and layout limitations. In this paper, we present practical integration schemes for developing cost-efficient 3D ICs in a monolithic fashion, which employ fully depleted transistor channels and laser annealing to achieve sharper junction definition.

Join us at the most important event in the 3D IC industry held this year in San Francisco, CA on October 2nd - 4th, 2013. Here you can find the registration link and fee information to attend the conference.

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"Moore's Law Dead by 2022" - Then, Before or .... ?

9/3/2013

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We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses the EE Times blog piece: Moore's Law Dead by 2022, Expert Says.

“Moore’s Law Dead by 2022” announces EE Times headline reporting Bob Colwell’s keynote at Hot Chips this week. Actual quote: "Moore's Law -- the ability to pack twice as many transistors on the same sliver of silicon every two years -- will come to an end as soon as 2020 at the 7nm node". Collwell told the audience that DARPA “tracks a list of as many as 30 possible alternatives to the CMOS technology that has been the workhorse of Moore's Law …My personal take is there are two or three promising ones and they are not very promising,". Colwell is the Director of DARPA’s Microsystems Technology Office (MTO) and has both visibility and credibility in these matters. In fact, this is not his first time to publicly state the end of Moore's Law -- he did so at ACM SIGDA and DAC meetings earlier this year. His slide (below) clearly presents the gap between the end of dimensional (Dennard) scaling and the establishment and ramp-up of alternatives to the current silicon based technology.

Figure 1

The discussion at EE Times remind us that we have "been hearing this for 20 years or more", so why is it different now? Well, even in the crying wolf story the wolf eventually did come! This time the signs are very clear. In fact, one could argue that as far as cost reduction, Moore's Law is already dead. The following ASML chart clearly shows it.

Figure 2

Taking into account additional information released during the recent Semicon West, it seems that effective cost for most fabless companies might even go higher with future scaling. Even if we ignore the fact that most foundries chose to keep their metal rules at 20nm when going to 14nm node, with the associated end-device cost implications, advanced nodes come with many additional layout restrictions. Those create circuit design and interconnect overheads that eat away a large part of theoretical scaling benefits. Quoting Andrew Kahng: "Constant area-factors allowed prior node scaling to be 2x, however since 2009 the real scaling has been 2E(2/3)x or ~1.6x due to an “IC Design Gap". Add to it the fact that embedded memory SRAM bit cell is expected to barely scale, as shown in the following slide, and end-product costs might go up even for the same SoC complexity!

Figure 3

The following chart from Samsung clearly illustrates this dynamics for NAND, but from the above discussion it may be even more true for SoC.

Figure 4

The issue of cost has very significant implications. For the semiconductor industry Moore's Law is not just a matter of pride: it became one of its fundamental business drivers. In the food industry vendors keep on selling food as it get consumed, clothing and car industry products get worn out or go out of fashion. But in the semiconductor industry old products mostly get displaced by better new products – the upgrades. Imagine what would happen to the major industry players’ stock if they were to update their projections to expect 20% reduction in revenue!!!
And 20% might be a conservative number once the dynamics of the last 30 years would hit a hard stop.
The following Samsung chart is a good illustration of where we are and the choice that at least Samsung has made:

Figure 5

We can keep on hoping that the wolf will never come, just as it hasn't before. Or we can take action now before 'they comes'.

Samsung, Toshiba and the rest of the NAND industry are already taking action. On the SoC side the challenges are as severe, yet at this point the industry is consumed by the enormous efforts to bring up FinFETs. It may even bring up compound semiconductors (III-V) for the next node (10nm), but then what? At what cost? For what kind of return?

It seems to me that the right moves are:

First, logic design market needs to adopt an alternative to the embedded memory. IBM stated at the recent Common Platform Forum that adopting eDRAM gave it the equivalent benefit of one node scaling. This was seconded by Intel’s recent announcement of integrating eDRAM with their new Haswell processor - Intel eDRAM attacks graphics in pre-3-D IC days. An even better option would be the one transistor two state memory breakthrough solution recently developed by Zeno Semiconductors.

Second, logic design needs to follow the NAND industry by developing monolithic 3D technology for SoC and logic products. In a recent blog we reported that CEA Leti has placed Monolithic 3D is now on the roadmap for 2019. We are pleased to announce that we will provide a tutorial on monolithic 3D as a part of the upcoming IEEE 3D IC Conference in early October in San Francisco, and we will follow with a plenary talk the following week at the IEEE S3S Conference in Monterey. In these conferences we also plan to present a new practical process flow for monolithic 3D, leveraging industry’s shift to laser annealing. This technology supports 3D technologies we had presented in the past, and can be used independently for new monolithic 3D process flows. We are looking forward to meeting you all there.

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Monolithic 3D is Now in Production: Samsung Starts Mass Producing Industry’s First 3D Vertical NAND Flash

8/19/2013

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We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses the starts of mass production for the industry's first 3D vertical NAND flash by Samsung.

Samsung announced today (Aug. 6, 2013) the mass production of the industry's first three-dimensional (3D) Vertical NAND (V-NAND) flash memory, which breaks through the current scaling limit for existing NAND flash technology. Achieving gains in performance and area ratio, the new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid state drives (SSDs).

Samsung's new V-NAND offers a 128 gigabit (Gb) density in a single chip, utilizing the company's proprietary vertical cell structure based on 3D Charge Trap Flash (CTF) technology and vertical interconnect process technology to link the 3D cell array. By applying both of these technologies, Samsung's 3D V-NAND is able to provide over twice the scaling of 20nm-class planar NAND flash.
"For the past 40 years, conventional flash memory has been based on planar structures that make use of floating gates. As manufacturing process technology has proceeded to the 10nm-class and beyond, concern for a scaling limit arose, due to the cell-to-cell interference that causes a trade-off in the reliability of NAND flash products. This also led to added development time and costs.

Samsung's new V-NAND solves such technical challenges by achieving new levels of innovation in circuits, structure and the manufacturing process through which a vertical stacking of planar cell layers for a new 3D structure has been successfully develop...
Also, one of the most important technological achievements of the new Samsung V-NAND is that the company's proprietary vertical interconnect process technology can stack as many as 24 cell layers vertically, using special etching technology that connects the layers electronically by punching holes from the highest layer to the bottom. With the new vertical structure, Samsung can enable higher density NAND flash memory products by increasing the 3D cell layers without having to continue planar scaling, which has become incredibly difficult to achieve”

It’s worth mentioning to the point that while the volume production of TSV based 3D IC is keep being pushed out as discussed in a recent blog: EUV vs TSV: Which one will become production ready first?, this announcement indicates that monolithic 3D NAND is biting the forecast by few years as being illustrated by the following 2012 ITRS chart:

Figure 2

Clearly monolithic 3D is a promising alternative to dimension scaling, as one can read in this Samsung press release. It also abides very well to the low cost objective for mass production products.

Monolithic 3D technology provides multiple unique and powerful advantages as we present on our site under the tab: 3D-IC Edge. Under item 5 we present the unique advantage that was first introduced in 2007, when Toshiba unveiled its Bit Cost Scalable (BiCS) technology. The unique advantage of 3D NAND is the ability to pattern and process multiple layers simultaneously.

This advantage comes very natural for regular layout fabrics such as memory, but it is also available for logic circuits. The driver for this advantage is the escalating costs of lithography in state of the art IC. The following charts illustrate the impact of dimensional scaling on lithography costs.

Figure 3

Figure 4

Currently critical lithography steps dominate the end device production costs as been illustrated in the following chart:

Figure 5

Accordingly, if the critical lithography step could be used once for multiple layers rather than multiple times for each single layer, then the end device cost would roughly be reduced in proportion to the number of layers processed simultaneously. Multiple memory architectures that support such drastic cost reduction has been presented in various conferences and other forums. Few of those had been presented in our blog: The Flash Industry's Direction, and MonolithIC 3D Inc.'s Solution... This dramatic announcement by Samsung comes in less than a week since we posted the blog: Monolithic 3D is now on the roadmap for 2019. It represents the beginning of a new trend for Moore’s Law – scaling up. As the memory segment of the industry shift its R&D budget and its capital equipment budget for scaling up, the shrinking camp supporting dimension scaling would need to pony up this shortage while facing escalating costs of dimension scaling. It is clear to us that the time to investigate various alternatives for scaling up has come, which also abides to the new industry roadmap recently presented.

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Monolithic 3D is now on the Road-Map for 2019

8/12/2013

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"The Evolution of Scaling from the Homogenous Era to the Heterogeneous Era"

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi underlines the milestone for monolithic 3D in the semiconductor road map 2019.

In the recent CEA Leti day, that took place as part of Semicon West 2013, Laurent Malier, Leti CEO presented his "A look at the coming Decade".
Slide 15 of the presentation provides Leti vision for CMOS roadmaps as presented here:

Figure 1

Monolithic 3D is presented on the road-map as the technology to follow 7nm process node.

Early this year we blogged - IEDM 2012: The pivotal point for monolithic 3D ICs, it is quite reassuring to see monolithic 3D now as part of the industry road-map. As we discussed than the memory vendors are already gearing up for volume production of the 3D NAND as reported recently Toshiba to Build Fab for 3D NAND Flash, leveraging monolithic 3D cost reduction advantage. It only makes senses for the CMOS market to follow. Doubters would ask why the industry would introduce new dimension to a road map that has been extremely successful for over 40 years. And the answer is very simple - because it is successful any more. We are all aware that the escalating costs of lithography had diminished transistors cost reduction as illustrated in the following ASML chart

Figure 2

But even if we ignore these issues we should remember that "Atoms don't scale" (as was phrased by Bernie Meyerson of IBM), and we are quickly approaching these limit as is presented by the following Intel chart:

Figure 3

And accordingly Mike Mayberry, director of its component research at Intel, said at the very recent IMEC Technology Forum "...has looked down the highway of conventional silicon development and reckons things become foggy beyond about the 7-nm node".
In fact Mike in his March 2013 presentation titled "Pushing Past the frontiers of Technology" clearly also present the monolithic 3D on his road map as the following slides illustrates

Figure 4

Figure 5

As was very well stated by Mark Bohr - Senior Fellow of Technology and Manufacturing Group and a Director of Process Architecture and Integration of Intel:

"The Evolution of Scaling from the Homogenous Era to the Heterogeneous Era"

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EUV vs. TSV: Which one will become production ready first?

7/31/2013

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We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel debates on the answer to an important question that is on everybody's mind these days.

Like every Semicon West show in the past, where many experts are brought together for showing the latest and greatest semiconductor manufacturing equipment and bringing numerous seminar/panel discussions, this Semicon West of 2013 was no different. Two major issues were discussed, which on the face of it look unrelated, that caught my attention:

Progress in

3D - TSV technology, and
EUV

Obviously these two issues are very different, but they are quite similar in respect to the following:

1. As the advanced node progresses to smaller and smaller feature size we are getting closer to the "end of the road map" or the "end of Moore's law".

Going to EUV does alleviate some of the problems related to the current solution of double patterning (or quadruple in the future assuming, EUV doesn't come to fruition soon enough).

As well, utilizing 3D devices with TSV has, in the grand scheme, a similar outcome; namely, advancing the integration via 3D structures rather than continued scaling. Though in the future, 3D devices and advanced nodes could go hand in hand.

2. The big miss of the road map. When one looks at some old road maps from a few years ago, one can ask how did we, the industry, miss by so much?

This actually reminds me of another miss from a few years ago-the low k inter-metal dielectric. Fig. 1 shows the low k dielectric roadmap trend of various ITRS published roadmaps and the prediction in 1999 that by 2004 we would be using k<2 !! Obviously we know what happened and even today 14 years later it is hard to breakthrough a k value of 2.5.

Figure1: low k Dielectric Road Map

Figures 2 and 3 show the roadmap for EUV and TSV, respectively. Both are of 2009 vintage. In each case the prediction of the road map vs. actual is startling.

Figure 2: EUV road map

Figure 3: TSV road Map

It is not the purpose of this blog to go over the reasons why the roadmaps of EUV and TSV missed the time table by miles, nor to blame anybody for it. There are many articles and discussions published on the subjects. Rather, I will touch on some of the highlights as well as try to make some conclusions regarding the pathway of the industry regarding these two important technologies.

EUV: The EUV technology has so far gone through monumental achievements vis-Ã -vis the incredible tasks of developing the next generation stepper technology. The amount of engineering and resources poured into it is unprecedented in the short history of the semiconductor industry and maybe so for other industries.

It looks like as I write this blog that the only barrier for the technology from becoming a HVM tool is EUV source power that can provide a high enough throughput. Many experts doubt that it could ever be achieved; however, there are many other experts saying that it is within a reach.

TSV: In this case I could see two totally unrelated issues:

1. Technology driven obstacles

2. Logistics and supply chain issues.

In the case of the TSV it is one of the few cases where the "power point" presentation(s) of the TSV idea are so convincing that it is actually hard to oppose it. However, when it comes to the fine details of the technology development, there are many issues that still need to be addressed and resolved. I believe that it is just a matter of time before the technical obstacles will be resolved and a unified standardized solution emerges. However, on the other hand, I see a real problem from the point of view of logistics, cost and supply chain of the technology, and I have some doubts if it can ever be resolved. For further discussion on this issue, please refer to: 3D IC Supply Chain: Still Under Construction, and to a detailed comment in EE Time published blog and comments re. Semicon West 3D - IC TSV, provided here below.

In summary, I believe that the industry will come with a solution for EUV before TSV becomes a production technology.

Yet there is another alternative to TSV and to EUV - it is the Monolithic 3D methods. Moreover, it is very likely that monolithic 3D will reach volume production before EUV and TSV. As we already see the NAND Flash vendors ramping up for production of 3D NAND.

The detailed comment fromm EE Times re. Semicon West 3D - IC TSV:

USER RANK CEO

Re: Semicon Showed Support for 3D ICs
chipmonk0 7/18/2013 1:46:13 PM

" same old same old ... " !! With such pollyannaish coverage, I am afraid that TSVs will remain the next hot interconnect tech even 5 years from now !

To provide a counter-point to all this happy talk, SemiCon had invited me to lead a 1 hr discussion at the Show on "Roadmap for TSVs and Alternatives from a Technology perspective ". Since Herb was not there, here are the key points :

1. unlike previous Advanced Packaging technologies like Flip Chip which we developed at IDMs like Motorola & Intel with both deep / broad expertise and product commitments, the development of TSVs has been going on mostly at overseas Govt. funded Laboratories in fits and starts and has then jumped to Foundries / OSATs. Xilinx' use of 2.5-d to integrate poorly yielding FPGAs has led to much irrational exuberance and then disappointment.

2. In the Winter of 2010 - 11 Samsung reported the first Wide I/O DRAM stack using TSVs. Great bandwidth even at 200 MHz & terrific power eff. But what the blogosphere neglected to report was that the yields were down in the mud and since then not much has been heard about Wide I/O from Samsung. Instead they keep bringing out conventional LP DDR at ever higher Clock Rates. JEDEC has actually postponed Wide I/O to 2015.
3. The development of TSV technology has been going on in Fabs who do not have to be sensitive to stress issues common in "thick film" type laminates / composites as is the case for filled vias. It is only now that they are waking up to it. Stress effects depend on the sq. of via dia., hence the new interest in shrinking them below 5 um. But integration & reliability problems ( at high Aspect Ratios both get worse ) have not been thought through. Moreover, Bonding stacked chips using the current method ( a sort of pidgin version of the technology I had invented nearly 20 years ago at Motorola for GaAs Power Amps that went into Cell Phones ) also introduces residual stress, affects electron mobility and shifts timing.

4. While these slow-poke Govt. funded Euro Labs rediscover stress effects on device perf. and the perils of Cu metallurgy applied indiscriminately, there is at least one small Company outside Chicago that has already shifted to the non - obvious ( at least to these TSV-niks ) yet theoretically sound choice of using Tungsten ( a brittle and poor electrical conductor which can be compensated by Design but unlike Cu a close CTE match with Si ).

5. But thats not all Folks - this tiny Co. with just 3 PhDs and Physicists has also solved the biggest TSV integration problem thats keeping all these Labs and various Tool Vendors new to the game ( in Herb's Osterreich they love to build big complex "Maschine" - Physics be damned ) -- intent on optimizing their individual process steps ( e,g. back up wafer bond / debond ) at the risk of compromising the whole process -- awake at night.

6. We did cover more, e,g. as to how to get the electrical benefits of TSVs w/o actually having to drill holes in live Silicon, circuitry and packages that make it possible. We already have some of these Alternatives ( using the concept of Active Interconnects ) under development - especially for the very large Server & SmartPhone markets - and have started publishing.

7. TSV development is orders of magnitude more complex than Flip Chip and would benefit from the same type of brutal, theory-driven Program Management practiced at the world's largest semiconductor Co., but since they have money in the Bank to stay on Moore's Law and thus continue single chip solutions they don't need TSVs that badly. So unless there is a radical shake - up in the TSV programs "outside", incl. at the Foundries, the present slow pace of TSV development will persist.

Morale : give TSVs a fair chance, they need a respite from these overly enthusiastic bloggers, embarassingly out of their depth, and at Conferences lets not blather about Supply Chain Issues, the technical probems are not all solved yet

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ASML at Semicon West 2013: SRAM scaling has Stopped!

7/18/2013

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2nd edition of: "Dimensional Scaling and the SRAM Bit-Cell"

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi adds information to his previous blog post: Dimension Scaling and the SRAM Bit-Cell.

I just downloaded the ASML presentation from Semicon West2013 site - ASML's NXE Platform Performance and Volume Introduction. Slide #5 - IC manufacture's road maps - says it all.

Embedded SRAM will scale from 0.09ÂµmÂ² at 22-20nm node to 0.06ÂµmÂ² at 11-10nm node. In other words only 30% reduction instead of the 4x reduction expected of historical dimension scaling, to roughly 0.02ÂµmÂ²!!!

In our previous blog (attached below) that followed ISSCC 2013 we saw some early indication of this slowdown. Yet we were still surprised to realize how bad it really is. This might explain why after resisting IBM and other pushes for embedded DRAM, Intel announced few month ago that its Haswell processor will incorporate embedded DRAM after all.

Another point from this ASML slide is the adaption of monolithic 3D by the NAND Flash vendors. We believe this is a start of a trend, and that logic vendors has now one more reason to follow it.

Previous Blog:

One Thing that ISSCC 2013 Highlighted to Us
Dimensional Scaling and the SRAM Bit-Cell

The IEEE International Solid-State Circuit Conference Feb 17-21, 2013 just ended in San Francisco last week, and the issue of dimensional scaling as it relates to EUV and future per transistor device cost was an important topic in the plenary session. One important, and perhaps overlooked, aspect of the industryâ€™s scaling issue relates to the future of the SRAM bit-cell within this framework of dimensional scaling. We would like to shine some light on this impending issue.

As widely reported in the industry and articulated by ASMLâ€™s Executive VP & CTO Martin van den Brink at ISSCC 2013, there is substantial evidence that without EUV the cost of logic transistors is most likely going up with scaling. One slide he used to illustrate this is below:

The above slide arrived after Martin had presented another non-encouraging slide, showing the same view from three companies: a Broadcom chart of increasing cost per gate correlated with dimensional scaling, together with the now famous Nvidia chart of no more crossover of transistor cost below 28nm, and third a GlobalFoundries chart showing some limited value for EUV.

We may attribute Martin statements to ASML interest in promoting EUV, but since ASML has already received significant EUV participation from INTEL, Samsung and TSMC, it might indicate further bumps are on the road to bringing EUV to market. We don't know if EUV will ever become real, but we do know very well that it is been delayed, and delayed again, and delayed again. It was made public recently that EUV has probably already missed the 10nm process node -â€œ10nm will be optical,â€ said Ajit Manocha, chief executive of GlobalFoundries.
An even more interesting slide was presented by van den Brink:

This chart brings up an important aspect of dimensional scaling that has not been discussed much before - the scaling of the SRAM bit-cell. According to this chart, the SRAM bit-cell size might not be reduced from the 20nm to 10 nm node, and might even get larger at 7nm as it may need more than 8 transistors. (Sound familiar? Fabs are doing the same with BEOL metallization scalingâ€¦little or none)

Modern logic devices demand a significant amount of embedded SRAM. In fact, more than 50% of the typical logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010)

The dominant embedded SRAM bit-cell architecture has been the 6 transistor cell (6T). And for many years this very cell has been hand-crafted using special design rules independently developed by foundries for every new technology node. It makes sense: the SRAM cell is a unique structure that does not obey normal logic design rules as it drives output against output anytime a write cycle is being performed. In many cases it is the SRAM cell that is the most sensitive portion of the logic device to process parameter variations and this sensitivity greatly impacts end device yield.

It well known that scaling the SRAM bit-cell has become harder and harder. Some vendors have already moved away from the 6T bit-cell in preference to the 8T (eight transistors) bit-cell. ISSCC 2013 had a significant number of papers that were presented using 8T SRAM. The few papers who kept the 6T SRAM embedded in their logic devices were forced to add read/write support circuits and additional overhead to enable the 6T bit-cell to function reliably.

Since SRAM bit scaling is now not able to keep up with logic scaling, the overall end device cost scaling could be even more disappointing than the transistor or gate cost illustrations above.

Of course, well aware of this trend, IBM has been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that in their 32nm product line the use of the embedded DRAM has given IBM the equivalent of a process node scaling benefit. Yet, as of now, most other vendors have not adopted eDRAM due to the process complexity and cost it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimensional scaling as the DRAM capacitor will be very hard to scale, the extra power for supporting DRAM will not be available and the cost of advance process development to add in extra complexity will be too high.

Accordingly we can learn from the recent ISSCC that dimensional scaling is facing the cost challenges we were aware of before in addition to new challenges that we might not have been aware of: the cost and the active/passive power handicaps due to the incompatibility of the 6T SRAM bit-cell with scaling.

As we have suggested before, now that monolithic 3D is practical, we could advance and maintain Moore's Law by augmenting dimensional scaling with 3D IC scaling. We could enjoy depreciated equipment charges for more years and much lower R&D engineering outlays that would bring down production and development costs, and also enjoy improvements to power and performance.

Another exciting option is to replace the 6T SRAM bit-cell with the 1T bi-stable floating body memory cell invented by Zeno Semiconductor. The Zeno bit-cell provides two stable states, analogous to an SRAM while only consuming ~20% area of a traditional 6T SRAM and requires considerably less power. The area and power savings over a traditional 6T SRAM improve further with scaling. Most excitingly the Zeno bit-cell is compatible with existing logic processes.

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Please Help Me Understand IBM - Common Platform Technology Forum 2013

2/10/2013

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"Innovations for Next Generation Scaling"

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses The Common Platform Technology Forum 2013.

The 2013 Forum today (Feb 5, 2013) started with a presentation by Dr. Gary Patton, VP, IBM Semiconductor Research & Development Center. Gary very clearly articulated the two irresolvable challenges the industry now faces:

On chip interconnect
Lithography

These two challenges connect very well with our recent blog IEDM 2012 - The Pivotal Point for Monolithic 3D IC. Gary showed both the exponential increase of RC which results from the dimensional scaling of copper below 100nm width and the high cost associated with double and quad patterning. In addition, he showed how the extreme scaling of the copper metallization creates reliability challenges such as fatal EM modes, and scaling of the insulator k breeds TDDB and strength issues. As a reminder, in the recent IEDM (Dec. 2012) short course, IBM presented the following slide indicating that interconnect now dominates device power!

L. Chang, D.J. Frank - IEDM 2012 Short Course – IBM Watson Research Center

Gary also presented a multi-decade past to future slide that resembles the one presented here below. The decade ending at the year 2000 was the good old days of easy scaling of planar transistor, which he called the gate oxide limit. Then the industry followed with a decade of "Material Innovation" that he called the planar device limit, and starting in 2010 is the beginning of the "3D Era" - 3D transistors and stacked devices.

Figure 2

Finally he shared with us his vision of 3D devices with three planes of devices:

Logic Plane
Memory Plane
Photonic Plane

A vision we mutually share.

Now, here is my failure to understand. As a company who has been in the forefront of 3D and TSV research, IBM is well aware of the severe limitations of TSV as an alternative for vertical interconnect. The following cross-sectional picture by IBM, presented at the recent GSA Summit, clearly illustrates how large a TSV is in comparison to an interconnect via.

IBM Systems and Technology Group – GSA Silicon Summit 2012 (S.s lyer) – 2012 IBM Corporation

With TSVs of 5 micron diameters (and pitches of 15 micron due to keep out zones from stress issues) vs. vias of less than 50 nm, the ratio in vertical connectivity is 1:10,000 as illustrated in the following chart by Perinne Batude of CEA Leti.

Figure 4

Clearly IBM technologists are well aware of the many research papers showing that TSVs, with their relatively huge size compared to all the other on-chip elements, diminish the performance or power benefits in folding designs to 3D. For example, the chart below was presented by Kim at the 2011 IEEE International Interconnect Technology Conference. The chart illustrates the performance benefits of folding a design twice (4 tiers of transistors) as dependent on the via size. At a via size of 5 microns there are actually no benefits, while at a via size of 0.1 micron the benefits are the equivalent of two nodes of dimension scaling!!!

Figure 5

So can someone please explain to me how come IBM is still talking about TSV as if it is the only representative of the "3D Era"???

And particularly now, when monolithic 3D is finally practical, and the NAND Flash memory vendors are adopting it across the board!?

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IEDM 2012 - The Pivotal Point for Monolithic 3D IC

1/27/2013

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We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses The Pivotal Point for Monolithic 3D IC.

From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here’s why:
We start with the EE Times article IEDM goes deep on 3-D circuits, starting with "Continuing on the theme of 3-D circuit technology addressed in an earlier post about this year’s International Electron Device Meeting, Rambus, Stanford University and an interesting company called Monolithic 3D will address issues related to cooling 3-D circuits. .." and follow with a quote from the abstract to IEDMs short course "Emerging Technologies for post 14nm CMOS" organized by Wilfried Haensch, of IBM’s Watson Research Center:

"Scaling the dimension was the key for the unprecedented success of the development of IC circuits for the last several decades. It now becomes apparent that scaling will become increasingly difficult due to fundamental physical limits that we are approaching with respect to power and performance trade-offs. This short course will give an overview of several aspects in this “end-of-scaling” scenario. ..."

We then continue with statements made by Dr. Howard Ko, a Senior Vice President and General Manager of the Silicon Engineering Group of Synopsys in his 2013: Next-generation 3-D NAND flash technology article:

"Yet there are a variety of developments in another type of 3-D scaling that are likely to have a similarly large impact on semiconductors in the near future - 3-D devices for NAND flash.... And as in planar CMOS logic, NAND flash technology has been progressively scaled to smaller feature sizes, becoming the process leader in driving the smallest line-widths in manufacturing as evidenced by the current 1x-nm (~19-nm) process node. Yet, despite plans to scale down to the 1y-nm (~15-nm) and possibly 1z-nm (~13-nm) nodes, the traditional planar floating gate NAND flash architecture is approaching the scaling limit, prompting the search for new device architectures. Not to be upstaged by the planar to 3-D (FinFET) transition in logic devices, NAND flash has embarked on its own 3-D scaling program, whereby the stacking of bit cells allows continuous cost-per-bit scaling while relaxing the lateral feature size scaling."

In our recent blog 3D NAND Opens the Door for Monolithic 3D we discussed in detail the adoption of monolithic 3D for the next generations of NAND Flash. The trend was very popular subject of this year’s IEDM and is nicely illustrated by this older chart:

Figure 1

And accordingly the updated ITRS 2012 present the change from dimension scaling to monolithic 3D scaling as presented in the following slide.

Figure 2

This year’s IEDM brought up two of the driving forces behind the shift from dimensional scaling to monolithic 3D IC scaling, that we will detail below as #1 and #2.
The Current 2D-IC is Facing Escalating Challenges:

On-chip interconnect (#1)

Dominates device power consumption
Dominates device performance
Penalizes device size and cost

Lithography (#2)

Dominates Fab cost
Dominates device cost and diminishes scaling benefits
Dominates device yield
Dominates IC development costs

The problem with on-chip interconnect didn’t start today. This vintage Synopsys slide below clearly indicates that on-chip interconnect started to dominate overall device performance a decade ago:

Figure 3

In response, the industry has spent an enormous amount of money to convert from aluminum to copper and to low-K inter-metal dielectrics. But now, we have very few additional options left (perhaps air-bridge?) as illustrated by the following chart:

Figure 4

It shows that neither Carbon Nano Tube (CNT) nor Optical interconnect are better than copper, and that monolithic 3D still is the best path.

The practiced ‘band-aid’ fix so far has been throwing more transistors (they are getting cheaper, right? No longer. See father below) at the problem in the form of buffer and repeaters. But as we scale down we need exponentially more of these ban-aids as illustrated by the following:

Figure 5

Copper, however, is now reaching its inflection point as was articulated in a special session organized by Applied Materials attached to this IEDM, The 14 nanometer node is expected to be an inflection point. Quoting from the abstract:

"The 14 nanometer node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design. On December 11, 2012, Applied Materials, Inc. will host an important forum in San Francisco to explore the path that interconnect technology must take to keep pace with transistor scaling and the transition to new 3D architectures.” (emphasis added)

This had been illustrated before in the following chart

Figure 6

And to make it crystal clear, IBM presented the following chart in its short course:

Figure 7

Power is now dominating IC design and clearly dimensional scaling does not improve the interconnect’s impact – see the following chart built from the ITRS Roadmap. The only effective path forward that addresses interconnect is monolithic 3D.

Figure 8

As for the second challenge – lithography – we start again with an old chart by Synopsys:

Figure 9

The implication is that any new node of dimensional scaling comes with escalating lithography costs; and sure enough, that’s what is happening. When litho costs are plotted over time, it fits a log-linear scale….this is not a sustainable trend.

The following chart illustrate the lithography escalating cost of equipment which directly reflect the wafer cost.

Figure 10

This resulted in the following slide by IBM at the GSA Silicon Summit 2012:

Figure 11

Quoting from the slide: "Net: neither per wafer nor per gate [are] showing historical cost reduction trends"

Another EE Times IEDM12 article covering a keynote given by Luc van den Hove, chief executive of IMEC, IEDM: Moore’s Law seen hitting big bump at 14 nm, repeats the same conclusion. In fact, some vendors are already changing course accordingly. GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium (11 December, 2012) during IEDM12 week also acknowledged that their 14nm node will have a 20nm node metal pitch, and, just like GlobalFoundries, a similar die size and increase in per-transistor cost. So it would seem that also for lithographic reasons, the industry’s next generation path, and the continuation of Moore's Law, would be achieved by leveraging the third dimension.

Now that monolithic 3D is feasible and practical, the time has come to move in this new direction, as has been nicely illustrated by this concluding chart below

Figure 12

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Can Heat Be Removed from 3D-IC Stacks?

12/19/2012

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We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses how can heat be removed from 3D-IC Stacks.

Thanks to everybody who came to IEDM this year, and especially to those I met and who came to paper 14.2, delivered by Hai Wei of Stanford University. You can find the meeting paper and slides here.

One of the big challenges facing 3D-IC is how to remove the heat dissipated on the upper layers to keep a high performance chip temperature within the system and reliability constraints and prevent hot spots. Most existing proposed techniques rely on arrays of TSVs and thick (xxum) silicon layer to conduct and spread the heat laterally and vertically. We propose that properly designed PDNs* (Power Delivery Networks) can significantly contribute to heat removal in both parallel (think TSV and xx um thick Si layers) and monolithic/sequential (think 100nm Si layer) 3D-ICs.

We investigated both parallel and monolithic in the paper. Here, I will, of course, focus more on the monolithic challenges and solutions, but I will make some important comparisons to parallel at the end.

Since the 130nm node, we have entered an era in our industry where we are not only using new materials, but also new device structures. I have written previously about the risk associated with this, and (hopefullyâ€¦) made a case for monolithic 3D technology being the best way for the industry to move forward, still enjoying Mooreâ€™s Law type economics (i.e., lower cost) but with a much lower development risk.

Life is getting thin and narrow in our businessâ€¦.so, how best to take advantage of this nanometer and angstrom era and avoid the economic (think EUV at 110+M$ a pop, or double/quad patterning) and atomistic (think 7 nm) brick walls coming? Monolithic 3D stacking technology is the answer: keeping the next evolutionary step of our industry in the wafer fab, where the batch economics of the silicon wafer can be enjoyed, and avoiding the costly piece-part assembly processes of TSVs.

One of the basic tenets of monolithic 3D is the ability to have thin (preferably monocrystalline) silicon layers that enable very small vertical interconnect manufacturing, and hence a large (>1 million/cm2) layer to layer vertical interconnect density in the stack. This opens up the possibility for powerful new architectures and devices, such as Amdahl's wafer scale computer (see blog, website, technology) and cost effective MLC 3D memories.

Two implications arise from the thin (on the order of 100nm or less) silicon layer stacking. First, that fully depleted (FD) devices, and hence silicon islands floating in an insulator such as silicon dioxide, will be the norm. Second, taking full advantage of a manufacturable aspect ratio etching (5:1 to 10:1), we will end up with a large density of very small layer to layer vias (of 1-2 lambda diameter), where vertical interconnect density rivals the horizontal density of interconnect that we have enjoyed thru the many cycles of Dennard scaling. FD devices are soon to be the norm in 2DICs; for example, the thin UTBBOX of STMicro/GlobalFoundries and the narrow FinFets of Intel/TSMC (incidentally, at IEDM12, Intel was criticized for doping the finsâ€¦).

Both of these implications, FD devices in islands of Si and very dense vertical interconnect, play a significant role in how we propose to solve a major challenge in 3D stacking.

Since the stacked layers are not in direct contact with the heat sink:
How do we get the heat out of the stacked layers???

In short, the answer is to take the heat out of each silicon island with the power delivery network, move it laterally in the metal interconnect of that stack layer (just as if we had a thick silicon layer underneath), and then vertically move the heat to the heat sink with that large density of interlayer vias (which we can now make due to the thin stacked layer being very thin).

Hereâ€™s a picture of what we are doing:

Figure 1

Sounds at least plausible, right?

Well, thatâ€™s what we set out to show, with the heavy lifting done by our friends at Stanford. Hai Wei & Tony Wu of Professor Subhasish Mitra's group, Professor Mitra, and Professor Fabian Pease, were the drivers in creating the simulation approach and engine to see if this works as we thought it might. It did, and then ended up developing a tool that may be very useful for future 3DIC design work.

Hai and Tony describe in the paper and the presentation the details of the simulation approach, engine, assumptions, and methodologies developed. Quite a nice piece of work! They have built an analysis framework that can be adapted for exploring technology-circuit-application interactions for a wide variety of 3D technologies, cooling options, and PDN designs. Types of 3DIC technologies modeled are conventional TSVs, called parallel 3D integration by many in the industry, and monolithic 3D integration, a type of sequential 3D integration. Cooling options range from conventional air cooling of the heat sink (2 W/KÂ·cm2) to external liquid cooling (10 W/KÂ·cm2) for high power systems. PDN designs studied ILV densities from 0 to 4 million/cm2.

That said, what are the essential takeaways?

First, the cooling benefits of PDNs are essential to achieve monolithic 3D integration. Without accounting for PDNs in the 3DIC thermal model, it will be next to impossible to achieve the desirable thermal characteristics and result of a 3D IC stack. Further, the density of ILVs is important to achieving the system thermal constraint. In the 100nm thick Si example below, the desired maximum chip temperature is 85Â°C or less.

Figure 2

Second, a processor can be effectively cooled, with no hot spots, using PDNs in a monolithic 3D configuration. Hai and Tonyâ€™s thermal analyses of core-on-core and memory-on-core designs, utilizing the OpenSPARC T1 industrial multi-core design operating running an 8-threaded program that solves the Black-Scholes application (i.e., hot), showed significant improvement and no hot spots. The top silicon layer is 100nm thick and the hottest parts of the chips were operating at 138 W/cm2. Those hottest parts, the EXU units, were stacked directly on top of each other to show the worst case.

Figure 3

Combining these two seems to indicate that no PDN in the model versus designing and optimizing with thermal-aware PDNs makes the difference between being able to run the design (processor on processor in this example) at only 1/3 of the full power density or at a full power.

Figure 4

Thatâ€™s the essential take-away for monolithic. Mimic the lateral heat conduction of thick silicon with the PDNs of the thin silicon stack layer, and then get that heat vertically to the heat sink with the dense network of vias provided by the monolithic 3D integration.

For the parallel 3D integration case, the 5um thick silicon greatly helps with the lateral heat conduction to the TSVs. With a properly designed PDN; however, there can be a significant savings in the number of TSVs (ILVs on chart below) used to vertically conduct the heat away, and thus offers a significant area savings by eliminating many of those big TSVs and Keep Out Zones (KOZs). (Note: for both the parallel and monolithic cases, Hai made the KOZ twice the ILV diameter as a conservative choice)

Figure 5

Moreover, by use of a properly designed PDN and an optimized density of TSVs, the maximum power density of the top layer in can be increased considerably â€¦. from 35 to 50 W/cm2 for the parallel 3D case.

Figure 6

It is worth noting an important point from these graphs: At the optimum design point, where the density of ILVs coupled to the PDN satisfies the desired 50W/cm2 max allowed power density, the required number of TSVs to effectively conduct the heat costs about 3% of the chip area. For the monolithic case, the chip area cost is about half that.

A high density of small vias not only makes possible some powerful product architectures such as logic-cone level redundancy, but is also key to producing area efficient vertical heat conduction networks.

BC

*Patent Pending technology

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3D-IC: Two for one

MonolithIC 3D Inc. at IEEE International Conference on 3D System Integration (3D IC)

"Moore's Law Dead by 2022" - Then, Before or .... ?

Monolithic 3D is Now in Production: Samsung Starts Mass Producing Industry’s First 3D Vertical NAND Flash

Monolithic 3D is now on the Road-Map for 2019

EUV vs. TSV: Which one will become production ready first?

ASML at Semicon West 2013: SRAM scaling has Stopped!

2nd edition of: "Dimensional Scaling and the SRAM Bit-Cell"

Previous Blog:

One Thing that ISSCC 2013 Highlighted to Us
Dimensional Scaling and the SRAM Bit-Cell

Please Help Me Understand IBM - Common Platform Technology Forum 2013

"Innovations for Next Generation Scaling"

IEDM 2012 - The Pivotal Point for Monolithic 3D IC

Can Heat Be Removed from 3D-IC Stacks?

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