We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the FPGA as ASIC Alternative. 

In our recent blog 28nm – The Last Node of Moore's Law we outlined the recent dramatic change that has happened after many years of cost reduction associated with dimensional scaling. It is clear now that 28 nm will provide the lowest cost per gate for years to come. In this blog we will assess the potential implications for the ASIC and the FPGA markets. Over the last two decades we have seen escalating mask set costs associated with dimensional scaling and accordingly escalating NRE costs. At the recent 2014 SEMI Industry Strategy Symposium (ISS) Ivo Bolsens, Xilinx CTO, presented the following chart of ASIC design cost escalation: 

The dramatic increases of ASIC design cost have had a real effect on the ASIC market, reducing the number of new designs and dramatically reducing the number of vendors serving the ASIC market.

One would expect that such a trend would have a very positive effect on the FPGA market, as there is no mask-set cost associated with an FPGA design and, accordingly, far lower NRE costs per design. The following fictitious chart presented in the EE Times article: What’s the number of ASIC versus FPGA design starts?, illustrates these expectations.

Surprisingly, this did not really happen. The following chart presents the overall FPGA market during the last decade according to the financial results of Xilinx, Altera and Actel.

The FPGA market growth could be compared to the overall semiconductor market growth as presented in the chart below (the market in 2013 was $305B). Clearly the FPGA market growth during the last decade is similar to the overall semiconductor market growth, and there is no indication of any benefits from the escalating ASIC mask-set cost and its associated NRE.

The FPGA technology started in the mid-1980s as an alternative to the popular ASIC technology then – the Gate Array. The acronym FPGA stands for Field Programmable Gate Array. During the 1990s the Gate Array technology lost its appeal and the ~$20B Gate Array market shrunk dramatically and effectively ceased to exist. Analyst expected that this will have a dramatic positive impact on the FPGA market, which did grow some but far from the expectations. The trend of escalating NRE driven by dimensional scaling and escalating lithography costs kept on going in the 2000s and drove down the number of ASIC designs. And, again, analysts expected a huge surge in the FPGA market. Clearly, this did not happen. 

In the following we will present our theory why it did not happen and some potential implications for the future.

We believe that the stagnation of FPGA growth is mostly due to the inefficiency of the FPGA technology. Most FPGAs use SRAM as the programming or ‘switch’ technology. Interconnects are the dominating resource in modern designs. Within an SRAM based FPGA the programming of interconnects is implemented by an SRAM cell control of a pass transistor, driver, or bidirectional driver. The following chart illustrates the diffusion area associated for such Programmable Interconnect Cell (PIC) assessed in 45nm technology and compared to the size of mask-defined equivalent – the via. The results indicate that the cell area overhead for the SRAM PIC is over 30X when compared to a via, which does not include the additional circuit overhead area needed to program and control the SRAM PIC.

This number had been reported in the industry for many years. A 2007 research paper by Ian Kuon and Prof Jonathan Rose (IEEE Transaction on Computer-Aided Design of IC and System) says this clearly: “In this paper, we have presented empirical measurements quantifying the gap between FPGAs and ASICs for core logic. We found that for circuits implemented purely using the LUT based logic elements, an FPGA is approximately 35 times larger and between 3.4 to 4.6 times slower on average than a standard-cell implementation.”

This high programmability overhead suggests that many of the current ASIC designs cannot be replaced by an FPGA design. Consequently, when advanced technology NRE is too high, the alternative is to use older node ASIC technologies. Since the number one driver for cost of mask-sets and NRE is the associated capital, the cost of older technologies goes down dramatically over time. The 30X area penalty means that one could use a node that is five generations older and have a competitive solution when compared to current node FPGA. Taking into account the 60% gross margin of the FPGA companies and the overhead of using a fixed-sized device of an FPGA family rather than a custom tailored Standard Cell device, these could compensate for an additional two nodes. Looking again at the design costs as illustrated in the Xilinx chart above, we can see that at 180 nm the design costs are pretty low and the mask set costs are too small even to register on the chart.

What has really happened is that many designs chose to use older node standard cells instead of an FPGA. In his last keynote presentation at the Synopsys user group (SNUG 2014) Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys newer tools to improve older node design effectiveness. The following chart is one of them and it also includes in its left side the current distribution of design starts. One can easily see that the most popular current design node is at 180nm. Clearly even such old node provides a better product than the state of the art FPGA.  

Now we understand why the escalating mask set and NRE costs have not resulted in a surge of FPGA designs but rather pushed designers to user older technology nodes that had depreciated enough to make their NRE cost less of an issue. The following chart of Design Starts per Node by IBS was recently presented in a Synopsys article "The new landscape of advanced design". It shows the design starts trend over time and, not surprisingly, indicates that designers migrate to more advanced nodes over a longer time and that the up and coming node these days is just 65 nm.

Recently EE Times published our blog, 28nm – The Last Node of Moore's Law. In it we presented that the 28nm node will be the end of cost reduction for dimensional scaling. Most analysts accept by now that 28 nm is going to be the lowest cost per gate for many years to come. 

There are potentially many implications of this change in Moore’s Law. One of those implications could affect the future of FPGAs.
Traditionally FPGAs have been, and still are, a technology driver of new logic technology nodes. This early adoption gave the FPGA customer a constantly better programmable platform for their designs. Now that dimensional scaling does not provide better cost, it will result in a build-up of pressure for FPGA customers to use a depreciated technology node as an alternative. Over time designers would see the NRE of 65nm going down to about what the 180nm NRE is today. Comparing a 65nm Standard Cell design to an FPGA of 28nm suggests that far more designs could be better off with Standard Cell. As 20 nm and 14 nm FPGAs would not provide a better cost than the 28 nm one, it means that the FPGA market could see a growing challenge in the coming years. 
 
Designers chose older nodes not just for its lower mask-set and NRE costs but also for availability of broader embedded options such as flash memories and analog cells. But those are becoming available on newer nodes over time as well. The 65 nm node is now ramping up and would become the preferred choice for new designs in a few years, as its mask-set cost and NRE keep going down thanks to deprecation and broader availability. As volume production of older designs winds down, vendors are reducing their costs to bring new designs in, and will soon make the 65 nm as easy to access as 180 nm is now. FPGA vendors will release newer products on 20nm and 14nm but those would not offer lower production costs than the 28 nm FPGA products and will be less and less competitive versus a ‘not too old’ technology node such as 65 nm. It only seems logical that these new semiconductor industry dynamics will have a negative effect on the FPGA market and a positive effect on ASIC and Structured ASIC technologies. 

Thus it behooves us to consider what can the FPGA vendors do to keep their business growth.
Interestingly, the same trend that now works against FPGA technologies could be used to improve their competitiveness. In the early days two major FPGA technologies were competing in the market. The SRAM technology and the anti-fuse technology. The SRAM technology had higher switch overhead, but ended up winning because it benefitted from two major advantages. First, it did not need any major process changes and could be adapted to newer nodes as soon as those could be fabricated. Second was their ability to reprogram the device over and over again. Now that new process nodes do not provide lower costs, FPGA vendors could look to other than SRAM technology as a new path to improve their programmable platforms. As for anti-fuse, the significant effort in recent years to develop RRAM technology opens the possibility of adopting antifuse technology that could offer re-programmability. Even more important is the fact that re-programmability these days is far less important as all FPGA designs utilize simulation technology and other EDA tools, as the trial and error methodology no longer can be effectively used for modern designs. 

A special type of antifuse programmable technology could be most effective – Antifuse-based 3D High Density FPGA. This type of programmable fabric leverages anti-fuse metal to metal technology, which use 3D transistors for programming the anti-fuses. The 3D transistors could handle the higher voltage required for the programming and provide the interconnect programming with minimal device density impact. The 3D anti-fuse programmable fabric density is very similar to a via programmable fabric. Via programmable fabrics has been used with structured ASICs such as those offered by eASIC and Triad Semiconductors (ViASIC). They provide a programmable fabric with about a 2X area penalty vs. mask-defined standard cell technologies. These antifuses could be made as one time or reprogrammable devices and be fully replaced by mask-defined vias for even lower cost volume production, as illustrated by the following chart

Going forward, the semiconductor industry needs to go through fundamental change. No longer is it sufficient to scale using the next node of dimensional scaling to provide better overall device value. From the 28 nm node going forward, the industry needs to open up for a broad range of innovation so to continue offering better products. We can only hope that this will drive the industry back to fast growth and support the future market of Internet-of-Things and Internet-of-Everything.

We have been hearing about the imminent demise of Moore’s Law quite often recently. Most of those predictions have been targeting the 7nm node and 2020 as the end point. But we need to recognize that 28nm is actually the last node of Moore's Law, beyond which we can make smaller transistors and pack more of them into the same die size but we can not reduce the cost, and in most cases, the same SoC will have a higher cost!

The famous Moore's Law was presented as an observation by Moore in his 1965 Electronics paper "The future of integrated electronics". Quoting: "The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years." Clearly Moore's Law is about "The complexity for minimum component costs", and the minimum component cost will be at the 28nm node for many years, as we will detail in the remainder of this blog.

The following chart was presented by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during Semi’s recent ISS 2014 Europe Symposium:

Hartmann is making the case that the "Moore's Law discontinuation due to cost stagnation or increase" applies to bulk technologies, which is the technology base of the majority of the industry.

ST information is backed by Globalfoundries as we can see from the following chart presented at the 2013 SOI Consortium workshop in Kyoto, Japan.

The above Globalfoundries chart shows that the lowest cost transistor is at the polySiON 28nm node.

Beyond 28nm, scaling becomes extremely expensive due to double litho, HKMG, FinFET, etc. The increase in wafer cost is illustrated by the recent NVidia chart from Semicon Japan (Dec. 2013) below:

The increase in wafer cost eats away the 2X transistor density gain per node as is illustrated by this ASML slide from Semicon West (2013):

However, the SoC end product silicon area is dependent on the SRAM bit cell size far more than on the general transistor density. This is the fundamental challenge now facing dimensional scaling - SRAM Bit scaling has been dramatically slowed beyond 28nm.
At 28nm the bitcell size is about 0.12µm². The following chart by imec reported in Status update on logic and memory roadmaps (Oct 2013):

Beyond 28nm, the SRAM bit scaling rate is about 20% per node instead of the historical 50%. And the situation is actually far worse as is illustrated by the following chart, presented in an invited paper by Dinesh Maheshwari, CTO of Memory Products Division at Cypress Semiconductors, at ISSCC 2014. It was also at the center of our recent blog "Embedded SRAM Scaling is Broken and with it Moore's Law."

Accordingly, the SRAM Mb/mm² scales far less than the bitcell due to factors such as:

• Smaller transistors have less drive, thus requiring breaking the SRAM into smaller blocks, creating more overhead area costs
  
• Smaller transistors have a higher level of variation, also requiring breaking the SRAM into smaller blocks
  
• The need for more overhead such as read assist circuits and write assist circuits
  
• Tighter metal pitches begat higher RC, thus again requiring breaking the SRAM into smaller blocks
  

Moreover, SoCs need I/O pads and their circuits, and other analog circuitry, all of which scale at a rate far less than 2x per node.

Furthermore, the exponential increase in BEOL RC as is illustrated by the following chart, presented by Geoffrey Yeap, VP of Technology at Qualcomm in his invited IEDM 2013 paper, results in an exponential increase of number of drivers and repeaters. This suppresses the effective gate density increase to only a factor of x1.6, or less.

Summarizing all of these factors, it is clear that for most SoCs, the 28nm will be for the coming years the node for "minimum component costs".

As an industry, we are facing a paradigm shift because dimensional scaling is no longer the path for cost scaling. New paths need to be explored such as SOI and monolithic 3D integration. It is therefore fitting that the traditional IEEE conference on SOI has expanded its scope and renamed itself to IEEE S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This new unified conference will help us to improve efficiency and establish this conference as a world class international venue to present and learn about the most up-to-date trends in CMOS and post-CMOS Scaling. The conference will provide both educational and cutting edge research in SOI and monolithic 3D and other supporting domains. These technologies were not part of the mainstream semiconductor past; accordingly, it is a golden opportunity to catch-up with these technologies now. Please mark your calendar for this opportunity to contribute and learn about SOI and monolithic 3D technology, as these technologies are well positioned to keep the semiconductor industry's future momentum.

The chart below was presented at ISSCC 2014 by Dinesh Maheshwari, CTO of Memory Products Division at Cypress Semiconductors. The slide clearly illustrates that embedded SRAM ("eSRAM") scaling is broken. 

Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let’s discuss it further.Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let’s discuss it further.
The following slide was presented by Intel at their recent analyst day. It illustrates the impact of dimensional scaling on advanced wafer cost ($/mm²) mostly due to the escalating cost of lithography. Intel believes it can compensate for this exponential wafer cost increase by increasing their transistor density (mm²/transistor) to maintain historical cost reduction of transistor cost ($/transistor).

Perhaps it can, but at this time we keep hearing about delays in ramping up the 14nm line. (See "Broadwell Coming, but Not Until the End of the Year.") This reminds us of the famous joke, "Will make it on the volume," since increasing transistor density is directly related to the aggressive dimensional scaling that was driving the escalating wafer cost in the first place.

Most industry players confirm that cost-reduction for transistors has stopped beyond the 28nm process node, as is illustrated by the ASML chart below. This chart was presented at SEMICON West 2013.

It also clear that EUV is not going to be ready for the 16/14nm node. In fact, most observers are in agreement that EUV will also miss the 10nm node.

For some applications, keeping the cost-per-transistor about the same while reducing power or increasing speed might still justify going to 20nm or 14nm. The IMEC/Cypress chart above indicates that this will not be true for most designs. The fraction of the die area used for eSRAM is consistently growing with scaling, and it already regularly exceeds 50%. The following two charts from Semico, which were recently updated, illustrate this for advanced SoC and average SoC implementations.

Taking into account that 16/14 nm silicon is almost twice as expensive per unit area as that of 28 nm, this implies that beyond 28nm, SoC costs for the same functionality will escalate for most designs, and this will dampen even further the transition to advanced nodes such as 20nm or 16/14nm!

This clearly seems to indicate a paradigm shift after 50 years of consistent cost-reduction with dimensional scaling. Indications of this were already presented in our blog, Paradigm Shift: Semi Equipment Tells the Future, and in recent news articles such asAnalysis: ASML Stops 450mm Dead and Intel Cancels Fab 42.

Some people will attempt to brush aside Maheshwari's chart shown above, yet multiple sources indicate this is a true new reality that should not be ignored. We first reported it in our blog on ASML at Semicon West 2013, SRAM Scaling Has Stopped, which was backed up by the following IMEC chart as reported in Status Update on Logic and Memory Roadmaps.

This IMEC chart shows that the reduction of eSRAM bitcell area below 28nm is much less than the 50% expected size-reduction per technology node.

Furthermore, TSMC reported at IEDM 2013 that their bitcell for 16nm is 0.07µm2, and at ISSCC2014 Samsung presented similar results for 14nm finFETs as shown in the following slide.

It appears that the TSMC and Samsung bit cell sizes are in line with the IMEC table presented above. It also appears that these trends become even worse when comparing the size of high performance block RAM between technology nodes as presented by Maheshwari.

In the case of block RAM, additional aspects need to be taken into consideration, such as the die size impacts required for implementing a new technology such as finFET. In its ISSCC 2014 paper, Samsung identified complications involved with the transition from planar to finFET, such as quantized width, strong PMOS, and a lack of the body-bias effect. Samsung disclosed a die size impact of 0.87% in order to add a Disturbance Noise Reduction (DNR) scheme to deal with its larger, more stable High Performance (HP) bit-cell. Samsung did not disclose the area impact of its proposed Negative Bitline write assist scheme used with their high density HD bit-cell, but we can assume it is likely significantly larger than the proposed scheme for the HP bit-cell.

Some of the issues that are holding back scaling eSRAM were presented in our recent blog: The Most Expensive SRAM in the World -- 2.0. Bitcell scaling is getting harder, much harder, and even more so is the ability to scale large blocks of embedded SRAM. When we add the fact that the amount of embedded memory is growing faster than the amount of logic cells, one can predict dark clouds for SoC scaling beyond 28nm. It seems that brute-force scaling is simply not practical anymore, but two technology innovations could solve the SRAM memory scaling problem and provide a scalable high density memory if adopted soon by the industry.

The first innovation is the One-Transistor SRAM (1T SRAM) developed by Zeno Semiconductor. This 1T SRAM utilizes an existing fab process, provides a 90% bitcell size reduction versus conventional 6T SRAM, and it will keep scaling beyond 28nm. The second innovation is that of monolithic 3D, which enables a very effective heterogeneous integration scheme, thereby allowing for the SRAM layer to be optimized for memory while the logic layer can be optimized for logic. (See Monolithic 3D eDRAM on Logic.)

So, what do you think? Do you still believe that traditional scaling is the way to go? Or do you think that we will need to rely on new technologies like 1T-SRAM and monolithic 3D in order to maintain the pace of SoC development?

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the latest news in semiconductor industry, the headlines that dominated last week's news papers about TSMC and Intel. 

 On January 14, 2014 we read on the Investors.com headlines page - Intel Seen Gaining Huge Pricing Advantage Over TSMC. Just three days later comes the responding headline: TSMC: We're "Far Superior" to Intel and Samsung as a Partner Fab.
These kinds of headlines are not seen too often in the semiconductor business domain and it is not clear what the objectives are for such. It will be hard to believe that this is an attempt to manipulate the investor community, yet there are only a handful of super high volume design wins that are driving the leading edge devices, and for those wins the fight should be taking place in the 'board' room. So let’s dive a bit into the details behind these headlines.
 The first headline relates to Jefferies analyst Mark Lipaci releasing an analysis report stating: "Intel will have a die size and transistor cost advantage over Taiwan Semiconductor (TSM) for the first time by fourth-quarter 2014, which could lead to a 50% pricing advantage in processors in 12 months, and a 66% pricing advantage in 36 months". We can find more information in the blog titled: Intel: Primed for Major Phone, Tablet Share on Cheaper Transistors, Says Jefferies. Quoting Lipaci: "At the same time that Intel has started focusing on computing devices in mobile form factors, it appears that TSMC is hitting a wall on the transistor cost curve. The chart below was presented by TSMC’s CTO. We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC for the first time ever in 4Q14. We believe Intel extends that cost lead 24 months after than in 2016."
Lipaci then used the following chart to illustrate the build up of Intel advantage vs. TSMC.

The Jefferies report goes further and provides the following charts for 14nm and 10nm.

 Clearly the primary advantage that the report is pointing out is the lack of the double margin associated with the foundry model vs. the IDM model. It seems that this argument has clearly been disproven by now. In the early days of the foundry industry most IDMs would argue that the foundry model would not work because of the double margin aspect - the foundry would need about 50% gross margin and then the fables company would need an additional 50% gross margin - which would make it completely uncompetitive vs. the IDM. 20 years later it was proven, again, that there is no "free lunch". The chip fabrication business needs a margin to be sustainable and the design business needs a margin to be sustainable. And the better business model is to have those managed by different companies as each could build excellence in its own value proposition. Intel did enjoy for many years effective exclusivity in the Windows based processors. Intel has not been able so far to show much success in mobile or any other non-Windows market. Since Intel is now trying to position themselves as a better foundry than TSMC, then clearly for their potential foundry customers this double margin argument is moot.  
 The charts above also compare Intel’s cost advantage vs. TSMC older nodes (Intel's 14nm vs. TSMC's 20 nm and Intel's 10nm vs. TSMC's 16nm). It is not clear that Intel is so far ahead. Intel 14nm had been delayed to the first quarter of 2014 and TSMC has committed to be in volume production in the later part of 2014. But the real competition is on the ability to bring fabless companies to volume using one's advanced process node. Key to this is the availability of libraries, EDA full tool set support, and major IP such as ARM processors. It is far from being clear that Intel is really far ahead of TSMC in this critical area. And then, these days it is not so clear that using a more advanced process node buys one an end-device cost advantage. In fact, the foundries have already made it clear that beyond the 28nm node they do not see cost reduction, due to the extra cost associated with advanced node lithography and other issues. Even Intel admitted at their latest analyst day that advanced nodes are associated with escalating depreciation and other costs, as illustrated by the following Intel chart - see the left most graph.

We should note that the Y axes of these graphs are logarithmic which indicate a significant increase of deprecation costs. However, Intel claims it will more than neutralize this increase of costs by accelerating the dimensional scaling when going to 14nm and 10nm, as is presented with the middle graph above. This would lead to an overall sustaining of the historical cost per transistor reduction as is illustrated by the rightmost graph above. Note: the asterisk (*) on those graphs indicates that numbers relating to 14nm and 10nm are forecasts only. Since Intel is committed to be in volume production at the 14nm node any day now, the number associated with 14nm should not be a forecast anymore and we hope to see them released soon.

The simple indication of technology node effective transistor density these days would be the bit cell size. As we have presented many times before, modern SoC device area is dominated by the embedded 6T SRAM. At IEDM 2013, TSMC made public their 6T SRAM bit cell area for 16nm: 0.07 sq. micron. We could not find any Intel public release for their 14nm 6T SRAM bit cell size. We did find an Intel chart for older nodes. This 6T bit cell size chart was presented at IDF2012:

Accordingly the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² = 0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm should be about 0.03 sq. micron or even smaller. As we don't have any official number we could wait until their early production devices of the 14nm node get analyzed or to the eventual release of their number. But short of an official number, we did find a 2013 presentation from the TRAMS project, of which Intel is a partner, as illustrated in the following charts:

It is now clear that EUV will not be available for the 14nm node, and accordingly the bit cell size from the chart above is 0.062 sq. micron. This is a bit better than that of TSMC but a far cry from 0.03 sq. micron.

If Intel does have a really good number, it would be reasonable to expect that they will make it public soon, to entice the high volume fabless companies such as Qualcomm and Apple to explore Intel’s foundry option.


As for the Jefferies analyst assertion "We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC", it is not clear if Intel’s R&D budget is truly larger. TSMC’s R&D budget is dedicated to the foundry side of the business while Qualcomm, Apple, ARM and many other fabless vendors R&D budgets support the design part of any new product release. The total ecosystem behind TSMC and ARM is clearly not smaller than that of Intel. In this month’s SEMI ISS Conference, IC Insights provided very interesting numbers regarding the record of 2013 as was reported in a blog titled:Is Intel the Concorde of Semiconductor Companies?


Top 10 CAPEX Spenders in 2013:

1. Samsung $12B
   
2. TSMC $11.2B
   
3. Intel $10.5B
   
4. GF $5.5B
   
5. SK Hynix $3.7B
   
6. Micron $3B
   
7. Toshiba $2.9B
   
8. UMC $1.5B
   
9. Infineon $880M
   
10. ASE (OSAT) $770M
    

Yes, Samsung and TSMC both outspent Intel. Just wait until you see the capacity numbers and you will know why.

Top 10 IC Wafer Capacity Leaders in 2013:

1. Samsung 12.6%
   
2. TSMC 10%
   
3. Micron 9.3%
   
4. Toshiba 8%
   
5. SK Hynix 7%
   
6. Intel 6.5%
   
7. ST 3.5%
   
8. UMC 3.5%
   
9. GF 3.3%
   
10. TI 3.0%
    

Clearly Intel is not larger than TSMC as a foundry and it is not clear why would it have a sustainable per transistor cost advantage.

Cost is important but it is far from being the only parameter when choosing a foundry partner. Selecting a foundry partner is truly selecting a partner. The design of leading edge devices is a very costly and lengthy effort, and has a pivotal effect on the business success for the fabless customer. TSMC had built trustful relationships for many years with its fabless customers. It is not clear how easy it is going to be for Intel to become a trustful foundry partner. So far it seems that Intel is still a proud IDM that insists that its customer will support its branding like the "Intel Inside" campaign or the recent announcement of Branding the cloud: Intel puts its stamp on cloud services across the globe. Intel’s repeating emphasis of their transistor cost advantage vs. that of TSMC suggests that Intel considers TSMC as their main competition for the mobile and tablet business. But then their consistent offering of SoC products for the space, as illustrated by the recent Intel chart below, and the Jefferies' cost analysis above, suggests that Intel is actually an IDM competing with the likes of Qualcomm in this space. It may create concerns in the minds of potential fables customers.

And as a final note, we don't know how much better the Intel process at 14nm and 10nm is vs. that of TSMC. We do know that when we ask someone for directions, if he says ‘make a right turn’ but with his hand he is pointing left, we should go ahead and turn left. So along with all of these confusing statements we learned just this week that Intel Cancels Fab 42, which was supposed to be the most advanced large capacity fab effort of Intel. I wonder if it should be considered as the hand pointing....

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about IEDM 2013. 

Let’s start with the short answer - because:

A. SOI is cheaper to fabricate than FinFet with comparable performance, and it is easier and cheaper to build FinFet on SOI which then provides better performance.

B. SOI is the natural technology for monolithic 3D IC for all overlaying transistor layers, and monolithic 3D is the most effective path to keep Moore's Law

C. SOI, or better 'XOI', is the most efficient path for most of the new concepts such as alternate materials for transistor construction and other structures like nano-wires.

Let’s now elaborate and discuss each of these points.

Starting with A: The following chart from Globalfoundries was presented on June 2013 at the FD-SOI Workshop, Kyoto, Japan. The chart illustrates that the best cost per transistor is the classic polysilcon gate at the 28nm node, that FD-SOI is cheaper than bulk with comparable performance at 28nm HKMG, and that FD-SOI at 20nm is cheaper than 14nm FinFet at the same performance level.

Similar information was presented by IBS (International Business Strategies), in Oct 2013 at the SOI Summit Shanghai, China.

And before that D. Handel Jones of IBS in a 2012 White Paper presented the following table.

Clearly the SOI substrate costs much more than the bulk substrate ($500 vs. $120), but the improvement in performance and the reduction of cost associated with FD processing neutralizes the substrate costs and makes the SOI route far more attractive. The following charts were included in a Comparison Study of FinFET on SOI vs. Bulk done by IBM, IMEC, SOITEC and Freescale:

For the second point "B, SOI is the natural technology for monolithic 3D", in monolithic 3D the upper semiconductor layer is very thin (<100nm) and is placed over oxide to isolate it from the interconnection structure underneath - hence SOI.

In this month’s IEDM 2013 two papers (9.3, 29.6) presented exciting demonstrations of monolithic 3D IC. It is interesting to note that Prof. Emeritus Chenming Hu of Berkeley (past TSMC CTO) who is now very famous due to his pioneering work on FinFets, is a co-author of these two pioneering works on monolithic 3D IC. The following figures illustrate the natural SOI structure of the upper transistor layers: 

In his invited paper at IEDM 2013 Geoffrey Yeap, VP of Technology at Qualcomm, articulates why monolithic 3D is most effective path for the semiconductor future: " Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law." As illustrated by his Fig. 17 below.

Clearly dimensional scaling is not providing transistor cost reduction beyond the 28 nm node, and the large fabless companies--Qualcomm, Broadcom, Nvidia, and AMD—recently reported this fact once again. The industry is trying to accommodate this new reality, while still rushing to develop and adopt more advanced nodes at escalating costs and complexity. And it is encouraging to see that Qualcomm are actually 'putting their money where their mouth is" as CEA Leti just recently announced an agreement with Qualcomm to Evaluate Leti’s Non-TSV 3D Process. Thus it was natural for Leti to include in their presentation at their promotional event in conjunction with this year’s IEDM 2013, slides advocating monolithic 3D as an alternative to dimensional scaling.

Leti’s presentation goes even further. One can see that in the following Leti slide, monolithic 3D is positioned as a far better path to keep the industry momentum and provides the cost reduction that dimensional scaling does not provide any more. Monolithic 3D also does this with far less costly fab infrastructure and process R&D. As the slide sums up: "1 node gain without scaling," or, as others may say, the new form of scaling is ‘scaling up’. 

In respect to point C regarding integration of other materials, we must admit that this is still area of advanced research and contains many unknowns. What we do know is that the silicon related worldwide infrastructure is unparalleled and will not be easily replaced. Accordingly, future technologies would have the best chance by first integrating with the existing silicon infrastructure, which in many cases is easier to do with SOI. To illustrate this we can refer to some other work presented in the IEDM 2013. Such as Stanford work (19.7) titled: "Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits" illustrated in the following chart:

Other work is about integrating photonics with CMOS which was covered in a recent article titled Is There Light At The End Of Moore’s Tunnel? and includes the following illustrations:

Clearly SOI and monolithic 3D integration have a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This new unified conference will help us to improve efficiency and establish this conference as a world class international venue to present and learn about the most up-to-date trends in CMOS and post-CMOS Scaling. The conference will provide both educational and cutting edge research in SOI and monolithic 3D and other supporting domains. These technologies were not part of the main stream semiconductor past; accordingly it is a golden opportunity to catch-up with these technologies now. Please mark your calendar for this opportunity to contribute and learn about SOI and monolithic 3D technology, as these technologies are well positioned to keep the semiconductor industry's future momentum.  

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about Moore's Law and the impact of it on the industry today.

The assertion that Moore made in April 1965 Electronics paper was:"Thus there is a minimum cost at any given time in the evolution of the technology. At present, it is reached when 50 components are used per circuit. But the minimum is rising rapidly while the entire cost curve is falling (see graph below)." 

"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years."

Clearly Moore's law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays - transistors) to achieve minimum cost will double every year.
The reduction of cost per component for many years was directly related to the reduction in feature size - dimensional scaling. But many other technology improvements made important contributions as well, such as increasing the wafer size from 2" all the way to 12".
But many observers these days suggest that 28nm will be the optimal feature size with respect to cost for many years to come. Below are some charts suggesting so:

And more analytical work by IBS’ Dr. Handel Jones

Graphically presented in the following chart

Or as nicely drawn by Globalfoundries

Recently EE Times reported that EUV Still Promising on IMEC's Road Map. IMEC provided a road map to transistor scaling all the way to 5nm, as illustrated in the following chart:

Yes, we probably can keep on scaling but, clearly, at escalating complexity and with completely new materials below 7nm. As dimensional scaling requires more advanced lithography it is clear that costs will keep moving up, and the additional complexity of transistor structures and all other complexities associated with these extreme efforts will most likely drive the costs even higher.
Looking at the other roadmap chart provided by IMEC and focusing on the SRAM bit cell in the first row, the situation seems far worse:

Since at 28 nm SRAM bit cell is already 0.081μm2, this chart indicates that future transistor scaling is barely applicable to the SRAM bit cell, which effectively is not scaling any more.
Unfortunately, most SoC die area is already dominated by SRAM and predicted to be so even more in the future, as illustrated by the following chart:

Source:. Y. Zorian, Embedded memory test and repair: infrastructure IP for SOC yield, in Proceedings the International Test Conference (ITC), 2002, pp. 340–349
Dimensional scaling was not an integral part of Moore's assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore. The following chart captures Samsung’s view of the future of dimensional scaling for NV memory, and it seems relevant to the future of logic scaling just as well.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about the scaling process that makes monolithic 3D IC practical.

In the 1960s, James Early of Bell Labs proposed three-dimensional structures as a natural evolution for integrated circuits. Since then many attempts have been made to develop such a technology. So far, none have been able to overcome the 400°C process temperature limitation imposed by the use of aluminum and copper in modern IC technologies for the underlying interconnects without great compromises. The “Holy Grail” of 3D IC has been the monolithic 3D, also known as sequential 3D, where a second transistor layer could be constructed directly over the base wafer using ultra-thin silicon – less than 100nm – thus enabling a very rich vertical connectivity.

Accordingly the industry developed a 3D IC technology based on TSV (Thru Silicon Via) where each strata (wafer) could be independently processed, then after thinning at least one wafer, place in a 3D configuration, and then connect the strata with TSV using a low temperature  (<400°C) process. This independent (parallel) processing has its own advantages; however, the use of thick layers (>50 µm) greatly limits the vertical connectivity, requires development of all new processing flows, and is still too expensive for broad market adoption. On the other hand, monolithic 3D IC provides a 10,000x better vertical connectivity and would bring many additional benefits as was recently presented in the IEEE 3D IC conference.

The semiconductor industry is always on the move and new technologies are constantly being introduced making changes the only thing that is constant. For the most part dimensional scaling has been associated with introducing new materials and challenges, thereby making process steps that were once easy far more complex and difficult. But not so in respect to monolithic 3D IC.

The amount of silicon associated with a transistor structure was measured in microns in the early days of the IC industry and has now scaled down to the hundreds and the tens of nano-meters. The new generation of advanced transistors have thicknesses in nanometers as is illustrated in the following ST Micro slide.

Dimensional scaling has also brought down the amount of time used for transistor activation/annealing, to allow sharper transistor junction definition, as illustrated in the following Ultratech slide

Clearly the amount of heat associated with transistor formation has reduced dramatically with scaling as less silicon gets heated for far less time.

And unlike furnace heating or RTP annealing, with laser annealing the heat is coming from the top and directed only on small part of the wafer as illustrated below.

The following illustrates Excico pulsed excimer laser which can cover 2×2 cm2 of the wafer.

Worth noting that this week we learned of good results when utilizing Excico laser annealing for 3D memory enhancement – Laser thermal anneal to boost performance of 3D memory device.

These trends help make it practical to protect the first strata interconnect from the high temperature process required for the second strata transistor formation. As the high temperature is on small amount of silicon for a very short time and for a small part of the wafer, the total amount of thermal energy required for activation/annealing is now very small.

One of the three most newsworthy topics and papers included in the 2013 IEDM Tip Sheet for the “Advances in CMOS Technology & Future Scaling Possibilities” track was a monolithic 3D chip fabricated using a laser (reported by Solid State magazine “Monolithic 3D chip fabricated without TSVs“). Quoting: “To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then used a novel low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated high performance – 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products.”

Furthermore, in last two weeks we presented in the IEEE 3D IC and IEEE S3S conferences an alternative simulation based work. We suggested to use a smart-cut® for the formation of the second strata (and not amorphous silicon crystallization) with innovative shielding layers to protect the first strata interconnect, as illustrated below.

Currently there are at least three different laser annealing systems offered on the market. The shielding layers could be adjusted according to the preferred choice of the laser annealing system. Our simulations show that if an excimer laser such as one offered by Excico is used, then even without these shielding layers the first strata routing layers are not adversely impacted by the laser annealing process.

Summary: In short, dimensional scaling is becoming harder and yet it makes monolithic 3D easier. We should be able to keep scaling one way or the other (or even both), and keep enjoying the benefits.

Note: smart-cut® s a register TM of Soitec

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi details MonolithIC 3D Inc's participation at the upcoming events in 3D IC field and the key role of the company in each event. 

This coming October there are two IEEE Conferences discussing 3D IC, both are within an easy drive from Silicon Valley.

The first one is the IEEE International Conference on 3D System Integration (3D IC), October 2-4, 2013 in San Francisco, and just following in the second week of October is the S3S Conference on October 7-10 in Monterey. The IEEE S3S Conference was enhanced this year to include the 3D IC track and accordingly got the new name S3S (SOI-3D-Subthreshold). It does indicate the growing importance and interest in 3D IC technology.

This year is special in that both of these conferences will contain presentations on the two aspects of 3D IC technologies. The first one is 3D IC by the use of Through -Silicon-Via which some call -”parallel” 3D and the second one is the monolithic 3D-IC which some call “sequential.”

This is very important progress for the second type of 3D IC technology. I clearly remember back in early 2010 attending another local IEEE 3D IC Conference: 3D Interconnect: Shaping Future Technology. An IBM technologist started his presentation titled “Through Silicon Via (TSV) for 3D integration” with an apology for the redundancy in his presentation title, stating that if it 3D integration it must be TSV!

 Yes, we have made quite a lot of progress since then. This year one of the major semiconductor research organization – CEA Leti – has placed monolithic 3D on its near term road-map, and was followed shortly after by a Samsung announcement of mass production of monolithic 3D non volatile memories – 3D NAND.

We are now learning to accept that 3D IC has two sides, which in fact complement each other. In hoping not to over-simplify- I would say that main function of the TSV type of 3D ICs is to overcome the limitation of PCB interconnect as well being manifest by the well known Hybrid Memory Cube consortium, bridging the gap between DRAM memories being built by the memory vendors and the processors being build by the processor vendors. At the recent VLSI Conference Dr. Jack Sun, CTO of TSMC present the 1000x gap which is been open between  on chip interconnect and the off chip interconnect. This clearly explain why TSMC is putting so much effort on TSV technology – see following figure:

On the other hand, monolithic 3D’s function is to enable the continuation of Moore’s Law and to overcome the escalating on-chip interconnect gap. Quoting Robert Gilmore, Qualcomm VP of Engineering, from his invited paper at the recent VLSI conference: “As performance mismatch between devices and interconnects increases, designs have become interconnect limited. Monolithic 3D (M3D) is an emerging integration technology that is poised to reduce the gap significantly between device and interconnect delays to extend the semiconductor roadmap beyond the 2D scaling trajectory predicted by Moore’s Law…” In IITC11 (IEEE Interconnect Conference 2011) Dr. Kim presented a detailed work on the effect of the TSV size for 3D IC of 4 layers vs. 2D. The result showed that for TSV of 0.1µm – which is the case in monolithic 3D – the 3D device wire length (power and performance) were equivalent of scaling by two process nodes! The work also showed that for TSV of 5.0µm – resulted with no improvement at all (today conventional TSV are striving to reach the 5.0µm size) – see the following chart:

So as monolithic 3D is becoming an important part of the 3D IC space, we are most honored to have a role in these coming IEEE conferences. It will start on October 2nd in SF when we will present a Tutorial that is open for all conference attendees. In this Monolithic 3DIC Tutorial we plan to present more than 10 powerful advantages being opened up by the new dimension for integrated circuits. Some of those are well known and some probably were not presented before. These new capabilities that are about to open up would very important in various market and applications.

In the following S3S conference we are scheduled on October 8, to provide the 3D Plenary Talk for the 3D IC track of the S3S conference. The Plenary Talk will present three independent paths for monolithic 3D using the same materials, fab equipment and well established semiconductor processes for monolithic 3D IC. These three paths could be used independently or be mixed providing multiple options for tailoring differently by different entities.

Clearly 3D IC technologies are growing in importance and this coming October brings golden opportunities to get a ‘two for one’ and catch up and learn the latest and greatest in TSV and monolithic 3D technologies — looking forward to see you there.

Join MonolithIC 3D Inc. at the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference on October 7th thru 10th, 2013 in Monterey, CA. The conference will start with three plenary talks, one for each of the conference tracks. We are most honored for being invited to give the 3D Plenary Talk. Our thanks to the organizing committee for their invitation.  We are pleased to see monolithic 3D technology is rapidly becoming part of the 3D IC field. MonolithIC 3D Inc. will be represented by Zvi Or-Bach, President and CEO of the company.

The 3D Plenary Talk will describe “Practical Process Flows for Monolithic 3D”. In this session Mr. Or-Bach will present three approaches to obtain 3D logic ICs. You can access the Technical Program of the Conference here.

Zvi Or-Bach: “Monolithic 3D ICs provides a practical short term path to keep the semiconductor industry on track with Moore's Law as dimensional scaling is reaching its diminishing return phase. Monolithic 3D IC allows the existing industry infrastructure and silicon knowledge to be utilized while research activities continue the search for other alternatives. It should be mentioned that we are also honored to be giving a tutorial on monolithic 3D at the IEEE 3D System Integration Conference on Oct 2-4, 2013, in San Francisco. At the tutorial we plan to present the many significant additional benefits that are available with monolithic 3D IC."

The three approaches which will be presented at S3S for monolithic 3D ICs are:

RCAT – Process the high temperature on a generic structure prior to layer transfer , and finish with cold processes; i.e., etch & depositions.

Gate Replacement (Gate Last HKMG) – Process the high temperature on a repeating structure prior to layer transfer, and finish with 'gate replacement' cold processes.

Laser Annealing – Use short laser pulses to locally heat and anneal the top layer while protecting the interconnection layers below from the topside heat.

In addition, the company will also present at the poster session the thermal compatibility of laser annealing of newly built 3D structures with transistors and interconnect circuits lying beneath in “Thermal Considerations for Monolithic Integration of Three-Dimensional Integrated Circuits”. This work was done in collaboration with the Department of Electrical Engineering, IIT-Bombay, India.

Abstract of poster: A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.

Please join us at the 2013 S3S Conference held this year in Monterey, CA October 7th thru 10th, 2013. Here you can find the registration link and fee information to attend the conference.

Join MonolithIC 3D Inc. at IEEE International Conference on 3D System Integration (3D IC) on October 2nd -4th, 2013 in San Francisco, CA. Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. will present a guest tutorial on 3D IC edge. The company will also give the presentation: “Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC” in session VII of the event. You can access the Technical Program of the Conference here.

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. will be featured as guest speaker to present a tutorial on Monolithic 3D IC. The tutorial describes the advantages of monolithic 3d as an alternative to maintain the exponential increase in integration. Some of the advantages of this technology include reductions of cost, decreases in power consumption, and improvements in performance, and bring some new and compelling benefits like:

• Continuing reductions in die size and power, 
  
• Significant advantages for reusing the same fab line and design tools,
  
• Heterogeneous Integration
  
• Processing multiple layers simultaneously, offering multiples of cost improvement
  
• Logic redundancy, allowing 100x integration at good yields
  
• Modular Platforms
  

“Monolithic 3D is a disruptive semiconductor technology. It builds on the existing infrastructure and know-how, and could bring to the high tech industry many more years of continuous progress. While it provides the advantages that dimensional scaling once provided, monolithic 3D offers many more options and benefits. And the best of all is that it could be done in conjunction with dimensional scaling. Now that monolithic 3D is practical, it is time to augment dimensional scaling with monolithic 3D-IC scaling.”

Even more, the company will also give a presentation in session VII on a new path for monolithic 3D IC: “Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC”. This work was done in collaboration with the Department of Electrical Engineering, IIT Bombay, India.

Abstract of presentation: Classical dimensional scaling faces challenges from growing on-chip interconnect time delays, and escalating lithography costs and layout limitations. In this paper, we present practical integration schemes for developing cost-efficient 3D ICs in a monolithic fashion, which employ fully depleted transistor channels and laser annealing to achieve sharper junction definition.

Join us at the most important event in the 3D IC industry held this year in San Francisco, CA on October 2nd - 4th, 2013. Here you can find the registration link and fee information to attend the conference.