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Moore’s Law Indeed stopped at 28nm!

12/20/2023

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Yet at the right time - 2014, Zvi was the only one to clearly state "Moore’s Law has stopped at 28nm!"

In the dynamic field of semiconductor technology, the ongoing discourse surrounding Moore's Law has experienced a notable evolution, prominently featuring Zvi Or-Bach's (MonolithIC 3D’ CEO) 2014 assertion. His statement that transistor cost scaling reached a pivotal juncture at 28 nm and remained static across four subsequent generations has attracted significant attention. The statement was recently validated by Milind Shah from Google in the Short Course (SC1.6) at IEDM 2023. The unequivocal statement, "Transistor cost scaling (0.7X) stalled at 28 nm and remains flat gen over gen'-4, confirming what was initially foreseen in earlier public viewpoints and blogs in 2014 predicting the conclusion of Moore's Law.
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A Historical Perspective on Moore's Law
Moore's Law, as originally stated is "The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue”
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Accordingly it envisioned the cost optimum will be achieved by doubling of transistor density every two years. Reflections on the journey from 1 micron to 0.1 micron reveal numerous predictions about the 'End of Moore's Law,' not always proven accurate. It was in this dynamic context that Zvi Or Bach's unequivocal statement in 2014 stood out, declaring decisively, "Moore’s Law has stopped at 28nm!"
That was while Intel kept declaring that Moore’s law will prevail for many years to come. Intel published it road map to keep cost per transistor reduction for the foreseeable future as indicated by their following slide.
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Zvi did reference Intel claims in his 2014 article in EE Times https://www.eetimes.com/intel-vs-intel/

Zvi Or Bach's 2016 Technical Assertion
Building upon his 2014 insights, Zvi Or Bach delved deeper in 2016, presenting a technical analysis that underlined the stagnation of transistor cost scaling at 28 nm. His meticulous examination considered factors such as escalating lithography cost, and transistor complexity (HKMG, FinFET), resulting in escalating wafer costs, ultimately asserting that this node marked the conclusion of Moore's Law in terms of cost scaling.

The latest technical discussions at IEDM 2023, facilitated by Google SC1.6's Short Course, have substantiated Zvi Or Bach's assertion from 2014. The technical validation affirming "Transistor cost scaling (0.7X) stalled at 28 nm and remains flat gen over gen " stands as a pivotal. This empirical confirmation not only solidifies the ongoing debate with tangible data but also fortifies the technical credibility of Zvi's initial forecast.
Follow-up Publications and Referenced Insights
The impact of Zvi Or Bach's 2014 publications reverberated through the industry, as evidenced by a cascade of follow-up publications citing his work. Design and Reuse, PhoneArena, SmartBrief, EE Times Asia, and others recognized the significance of the technical insights, amplifying the discussion and contributing to the evolving narrative surrounding the conclusion of Moore's Law.

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2024 Forecast: Hybrid Bonding Steps Up

12/4/2023

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2024 is poised to be the inflection point for commercial use of hybrid bonding, is poised to become a central technology in all major semiconductor segments: logic, DRAM, and NAND.
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We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc.
YMTC introduced the use of hybrid bonding for 3D NAND a few years ago, and now Kioxia/WD, one of the main 3D NAND vendors, is also releasing a 218 (BiCS8) 3D NAND product to volume production that utilizes hybrid bonding. This indicates the coming trend in NAND devices, termed "CMOS Directly Bonded to Array" (CBA).

For DRAM, it has been announced that the high-bandwidth memory (HBM) product, HBM4, will be introduced in 2025 utilizing hybrid bonding. Additionally, all DRAM vendors are actively pursuing 3D DRAM development using hybrid bonding. Samsung has disclosed an alternative for DRAM using 4F2 Cell and Hybrid Bonding, which will be presented at this year's IEDM and may be introduced to the market soon.

Early use of hybrid bonding in logic products took place in 2023 with AMD's 3D Cache technology. In 2024, Intel is scheduled to release its A20 process using Back Side Power Delivery (BSPD), also called PowerVia, which also uses bonding and extreme thinning technology. Extreme thinning overcomes one of the handicaps of 3D technologies, through-silicon vias (TSVs), using nano-TSVs, which are essentially simple via processes. As major foundries embrace extreme thinning, it is expected that many new applications of 3D heterogeneous integration using hybrid bonding will emerge soon after.

AI computing could become the next-generation technology driver in 2024. As previously reported, China may win in AI computing by using hybrid bonding to enable DRAM over processor to bridge the "memory wall" through an an approach called near memory computing. While the current actors are not the first-tier vendors, this is expected to change due to the insatiable appetite for computing power by Large Language Model (LLM) vendors. According to OpenAI's calculations, the amount of computing used in global AI training has grown exponentially since 2012, doubling every 3.43 months on average. Currently, the amount of computing has expanded 300,000 times, far exceeding the growth rate of computing power. One indication of this emerging trend is the press release issued this week by UMC, titled "UMC Launches W2W 3D IC Project with Partners, Targeting Growth in Edge AI."

Conclusion

Hybrid bonding is becoming a key technology driving the next generation of semiconductor devices. 2024 is likely to be the pivotal point for hybrid bonding adoption across all major semiconductor segments, including logic, DRAM, and NAND. Additionally, hybrid bonding is expected to play a major role in the development of next-generation AI computing solutions.
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