We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi details MonolithIC 3D Inc's participation at the upcoming events in 3D IC field and the key role of the company in each event. 

This coming October there are two IEEE Conferences discussing 3D IC, both are within an easy drive from Silicon Valley.

The first one is the IEEE International Conference on 3D System Integration (3D IC), October 2-4, 2013 in San Francisco, and just following in the second week of October is the S3S Conference on October 7-10 in Monterey. The IEEE S3S Conference was enhanced this year to include the 3D IC track and accordingly got the new name S3S (SOI-3D-Subthreshold). It does indicate the growing importance and interest in 3D IC technology.

This year is special in that both of these conferences will contain presentations on the two aspects of 3D IC technologies. The first one is 3D IC by the use of Through -Silicon-Via which some call -”parallel” 3D and the second one is the monolithic 3D-IC which some call “sequential.”

This is very important progress for the second type of 3D IC technology. I clearly remember back in early 2010 attending another local IEEE 3D IC Conference: 3D Interconnect: Shaping Future Technology. An IBM technologist started his presentation titled “Through Silicon Via (TSV) for 3D integration” with an apology for the redundancy in his presentation title, stating that if it 3D integration it must be TSV!

 Yes, we have made quite a lot of progress since then. This year one of the major semiconductor research organization – CEA Leti – has placed monolithic 3D on its near term road-map, and was followed shortly after by a Samsung announcement of mass production of monolithic 3D non volatile memories – 3D NAND.

We are now learning to accept that 3D IC has two sides, which in fact complement each other. In hoping not to over-simplify- I would say that main function of the TSV type of 3D ICs is to overcome the limitation of PCB interconnect as well being manifest by the well known Hybrid Memory Cube consortium, bridging the gap between DRAM memories being built by the memory vendors and the processors being build by the processor vendors. At the recent VLSI Conference Dr. Jack Sun, CTO of TSMC present the 1000x gap which is been open between  on chip interconnect and the off chip interconnect. This clearly explain why TSMC is putting so much effort on TSV technology – see following figure:

On the other hand, monolithic 3D’s function is to enable the continuation of Moore’s Law and to overcome the escalating on-chip interconnect gap. Quoting Robert Gilmore, Qualcomm VP of Engineering, from his invited paper at the recent VLSI conference: “As performance mismatch between devices and interconnects increases, designs have become interconnect limited. Monolithic 3D (M3D) is an emerging integration technology that is poised to reduce the gap significantly between device and interconnect delays to extend the semiconductor roadmap beyond the 2D scaling trajectory predicted by Moore’s Law…” In IITC11 (IEEE Interconnect Conference 2011) Dr. Kim presented a detailed work on the effect of the TSV size for 3D IC of 4 layers vs. 2D. The result showed that for TSV of 0.1µm – which is the case in monolithic 3D – the 3D device wire length (power and performance) were equivalent of scaling by two process nodes! The work also showed that for TSV of 5.0µm – resulted with no improvement at all (today conventional TSV are striving to reach the 5.0µm size) – see the following chart:

So as monolithic 3D is becoming an important part of the 3D IC space, we are most honored to have a role in these coming IEEE conferences. It will start on October 2nd in SF when we will present a Tutorial that is open for all conference attendees. In this Monolithic 3DIC Tutorial we plan to present more than 10 powerful advantages being opened up by the new dimension for integrated circuits. Some of those are well known and some probably were not presented before. These new capabilities that are about to open up would very important in various market and applications.

In the following S3S conference we are scheduled on October 8, to provide the 3D Plenary Talk for the 3D IC track of the S3S conference. The Plenary Talk will present three independent paths for monolithic 3D using the same materials, fab equipment and well established semiconductor processes for monolithic 3D IC. These three paths could be used independently or be mixed providing multiple options for tailoring differently by different entities.

Clearly 3D IC technologies are growing in importance and this coming October brings golden opportunities to get a ‘two for one’ and catch up and learn the latest and greatest in TSV and monolithic 3D technologies — looking forward to see you there.

Join MonolithIC 3D Inc. at the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference on October 7th thru 10th, 2013 in Monterey, CA. The conference will start with three plenary talks, one for each of the conference tracks. We are most honored for being invited to give the 3D Plenary Talk. Our thanks to the organizing committee for their invitation.  We are pleased to see monolithic 3D technology is rapidly becoming part of the 3D IC field. MonolithIC 3D Inc. will be represented by Zvi Or-Bach, President and CEO of the company.

The 3D Plenary Talk will describe “Practical Process Flows for Monolithic 3D”. In this session Mr. Or-Bach will present three approaches to obtain 3D logic ICs. You can access the Technical Program of the Conference here.

Zvi Or-Bach: “Monolithic 3D ICs provides a practical short term path to keep the semiconductor industry on track with Moore's Law as dimensional scaling is reaching its diminishing return phase. Monolithic 3D IC allows the existing industry infrastructure and silicon knowledge to be utilized while research activities continue the search for other alternatives. It should be mentioned that we are also honored to be giving a tutorial on monolithic 3D at the IEEE 3D System Integration Conference on Oct 2-4, 2013, in San Francisco. At the tutorial we plan to present the many significant additional benefits that are available with monolithic 3D IC."

The three approaches which will be presented at S3S for monolithic 3D ICs are:

RCAT – Process the high temperature on a generic structure prior to layer transfer , and finish with cold processes; i.e., etch & depositions.

Gate Replacement (Gate Last HKMG) – Process the high temperature on a repeating structure prior to layer transfer, and finish with 'gate replacement' cold processes.

Laser Annealing – Use short laser pulses to locally heat and anneal the top layer while protecting the interconnection layers below from the topside heat.

In addition, the company will also present at the poster session the thermal compatibility of laser annealing of newly built 3D structures with transistors and interconnect circuits lying beneath in “Thermal Considerations for Monolithic Integration of Three-Dimensional Integrated Circuits”. This work was done in collaboration with the Department of Electrical Engineering, IIT-Bombay, India.

Abstract of poster: A major consideration for practical integration of 3D integrated circuits is compatibility of the thermal processes used to build new transistors in the vertical dimension, with sustained viability of the devices already fabricated beneath. Major contributions to the thermal profile of IC processes are laser-based anneals, rapid-thermal anneals and deposition processes, and traditional furnace processes for both annealing and film deposition. In this work, we consider the thermal compatibility of laser annealing of newly built 3D structures, with the ICs lying beneath.

Please join us at the 2013 S3S Conference held this year in Monterey, CA October 7th thru 10th, 2013. Here you can find the registration link and fee information to attend the conference.

Join MonolithIC 3D Inc. at IEEE International Conference on 3D System Integration (3D IC) on October 2nd -4th, 2013 in San Francisco, CA. Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. will present a guest tutorial on 3D IC edge. The company will also give the presentation: “Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC” in session VII of the event. You can access the Technical Program of the Conference here.

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc. will be featured as guest speaker to present a tutorial on Monolithic 3D IC. The tutorial describes the advantages of monolithic 3d as an alternative to maintain the exponential increase in integration. Some of the advantages of this technology include reductions of cost, decreases in power consumption, and improvements in performance, and bring some new and compelling benefits like:

• Continuing reductions in die size and power, 
  
• Significant advantages for reusing the same fab line and design tools,
  
• Heterogeneous Integration
  
• Processing multiple layers simultaneously, offering multiples of cost improvement
  
• Logic redundancy, allowing 100x integration at good yields
  
• Modular Platforms
  

“Monolithic 3D is a disruptive semiconductor technology. It builds on the existing infrastructure and know-how, and could bring to the high tech industry many more years of continuous progress. While it provides the advantages that dimensional scaling once provided, monolithic 3D offers many more options and benefits. And the best of all is that it could be done in conjunction with dimensional scaling. Now that monolithic 3D is practical, it is time to augment dimensional scaling with monolithic 3D-IC scaling.”

Even more, the company will also give a presentation in session VII on a new path for monolithic 3D IC: “Pulsed Laser Annealing: A scalable and practical technology for monolithic 3D IC”. This work was done in collaboration with the Department of Electrical Engineering, IIT Bombay, India.

Abstract of presentation: Classical dimensional scaling faces challenges from growing on-chip interconnect time delays, and escalating lithography costs and layout limitations. In this paper, we present practical integration schemes for developing cost-efficient 3D ICs in a monolithic fashion, which employ fully depleted transistor channels and laser annealing to achieve sharper junction definition.

Join us at the most important event in the 3D IC industry held this year in San Francisco, CA on October 2nd - 4th, 2013. Here you can find the registration link and fee information to attend the conference.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses the EE Times blog piece: Moore's Law Dead by 2022, Expert Says.

“Moore’s Law Dead by 2022” announces EE Times headline reporting Bob Colwell’s keynote at Hot Chips this week. Actual quote: "Moore's Law -- the ability to pack twice as many transistors on the same sliver of silicon every two years -- will come to an end as soon as 2020 at the 7nm node". Collwell told the audience that DARPA “tracks a list of as many as 30 possible alternatives to the CMOS technology that has been the workhorse of Moore's Law …My personal take is there are two or three promising ones and they are not very promising,". Colwell is the Director of DARPA’s Microsystems Technology Office (MTO) and has both visibility and credibility in these matters. In fact, this is not his first time to publicly state the end of Moore's Law -- he did so at  ACM SIGDA and DAC meetings earlier this year. His slide (below) clearly presents the gap between the end of dimensional (Dennard) scaling and the establishment and ramp-up of alternatives to the current silicon based technology.

The discussion at EE Times remind us that we have "been hearing this for 20 years or more", so why is it different now? Well, even in the crying wolf story the wolf eventually did come! This time the signs are very clear. In fact, one could argue that as far as cost reduction, Moore's Law is already dead. The following ASML chart clearly shows it.

Taking into account additional information released during the recent Semicon West, it seems that effective cost for most fabless companies might even go higher with future scaling. Even if we ignore the fact that most foundries chose to keep their metal rules at 20nm when going to 14nm node, with the associated end-device cost implications, advanced nodes come with many additional layout restrictions. Those create circuit design and interconnect overheads that eat away a large part of theoretical scaling benefits. Quoting Andrew Kahng: "Constant area-factors allowed prior node scaling to be 2x, however since 2009 the real scaling has been 2E(2/3)x or ~1.6x due to an “IC Design Gap". Add to it the fact that embedded memory SRAM bit cell is expected to barely scale, as shown in the following slide, and end-product costs might go up even for the same SoC complexity! 

The following chart from Samsung clearly illustrates this dynamics for NAND, but from the above discussion it may be even more true for SoC.

The issue of cost has very significant implications. For the semiconductor industry Moore's Law is not just a matter of pride: it became one of its fundamental business drivers. In the food industry vendors keep on selling food as it get consumed, clothing and car industry products get worn out or go out of fashion. But in the semiconductor industry old products mostly get displaced by better new products – the upgrades. Imagine what would happen to the major industry players’ stock if they were to update their projections to expect 20% reduction in revenue!!!
And 20% might be a conservative number once the dynamics of the last 30 years would hit a hard stop.
The following Samsung chart is a good illustration of where we are and the choice that at least Samsung has made:

We can keep on hoping that the wolf will never come, just as it hasn't before. Or we can take action now before 'they comes'.

Samsung, Toshiba and the rest of the NAND industry are already taking action. On the SoC side the challenges are as severe, yet at this point the industry is consumed by the enormous efforts to bring up FinFETs. It may even bring up compound semiconductors (III-V) for the next node (10nm), but then what? At what cost? For what kind of return?

It seems to me that the right moves are:

First, logic design market needs to adopt an alternative to the embedded memory. IBM stated at the recent Common Platform Forum that adopting eDRAM  gave it the equivalent benefit of one node scaling. This was seconded by Intel’s recent announcement of integrating eDRAM with their new Haswell processor - Intel eDRAM attacks graphics in pre-3-D IC days. An even better option would be the one transistor two state memory breakthrough solution recently developed by Zeno Semiconductors. 

Second, logic design needs to follow the NAND industry by developing monolithic 3D technology for SoC and logic products. In a recent blog we reported that CEA Leti has placed Monolithic 3D is now on the roadmap for 2019. We are pleased to announce that we will provide a tutorial on  monolithic 3D as a part of the upcoming IEEE 3D IC Conference  in early October in San Francisco, and we will follow with a plenary talk the following week at the IEEE S3S Conference in Monterey. In these conferences we also plan to present a new practical process flow for monolithic 3D, leveraging industry’s shift to laser annealing. This technology supports 3D technologies we had presented in the past, and can be used independently for new monolithic 3D process flows. We are looking forward to meeting you all there.