Hughes Metras, Leti’s VP of Strategic Partnerships North America, introduced the lead talk at their SemiconWest 2014 Leti Day about monolithic 3D technology as the “solution for scaling.” Hughes presented the Leti device technology roadmap which showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to well past 5nm. Here’s the important piece of that roadmap, which highlights the partnership with Qualcomm (ST and IBM helped with some of the work as well):

The lead talk was given by device scientist Olivier Faynot, Leti’s Device Department Director.  He titled his talk “M3D, a disruptive approach for further scaling,” and began with why the industry needs a solution for scaling.

Most in the industry are in agreement that scaling past the 22nm node, while still quite technically feasible, has priced itself out of most markets. Olivier discussed the what (transistor costs are no longer decreasing) and the why (litho cost escalation and connectivity inefficiencies of energy and delay). And then he made the statement: “if we just keep the current (2Xnm) technology, we can go farther in cost scaling.” [note: see the following blogs and comments for more info on this crucial topic:  Tech Design Forums summary "3D and EDA need to make up for Moore’s Law, says Qualcomm" and Zvi-Or-Bach’s EETimes blogs Qualcomm Calls for Monolithic 3D IC and  28nm - The Last Node of Moore's Law.]

Oliver showed a summary of a DAC2014 paper and a Qualcomm/GeorgiaTech DAC2014 paper Power/Performance/Area analysis of M3D for an FPGA:

The solution is to build the stack sequentially, in a monolithic fashion. Olivier described their monolithic 3D, or sequential 3D, process flow where the lower-level (first layer) of transistors and its interconnect are conventionally made, then inter-level metal is crafted to help the vertical interconnection, and then a second layer of monocrystalline silicon is layer transferred and oxide-oxide low temperature bonded to the top of the inter-level metal dielectric. This is a blanket layer so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin (10-200nm final), so that direct alignment thru that thin layer to the lower level alignment marks can be made with conventional equipment and achieve conventional alignment tolerances (single digit nanometers).

Now upper-level transistors are formed utilizing SPER (Solid Phase Epitaxial Regrow) for junction doping at 475-600°C and other lower (<400°C) temperature processing for gate stacks, etc. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. Note that the lower level transistor Ni salicides are stabilized with platinum co-deposition and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.

Oliver also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. He called the laser (pulsed and short wavelength) option of solving the thermal challenge of monolithic 3D as the “crème brûlée” of methods and they were ‘seeing good results.’ Hopefully we will see published data soon. For more information on SPER and laser processing please see my recent blog Monolithic 3DIC: Overcoming silicon defects.

Oliver was also asked in the Q&A if stress was a big issue. He replied that stress was not an issue, rather, the biggest challenges were integration ones (how to form a low temp top transistor, stability of the local interconnect level, and the bottom transistor salicide stability). Olivier was asked in the Q&A what the observed performance differences were between the upper-level and lower-level transistors. He replied” Currently we are achieving 95% (of the lower for the upper). We believe we can make 100%.”

Leti has a 14nmPDK ready to go for those who want to design a test circuit in their monolithic 3D flow. They have ELDO, HSPICE, Virtusoso, Calibre, StarRC, etc. files available.

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December 2013, Leti signed an agreement to work with Qualcomm – Qualcomm to Evaluate Leti’s Non-TSV 3D Process. ST and IBM have also been working with Leti in various aspects, for example, IBM & Leti used COMPOSE3 to simulate a monolithic InGaAs nFET monolithically over a SiGe pFET on SOI.

CEA-Leti has been busy working on processing flows to enable monolithic 3D devices since before 2009. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper entitled, “Advances in 3D CMOS Sequential Integration,” where she showed results for a sequentially processed P over N (no metal between transistors layers) testchip Batude’s 2011 IEDM paper showed a 50nm 3D sequential structure on 10nm channel silicon:

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications, both parallel and monolithic, with an inauguration event in January 2011. As well, back in December 2013, Soitec and CEA renewed their long-standing partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. I would like to invite you to the IEEE S3S Conference: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference will be held October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

See you there!

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the shift in semi equipment, a paradigm confirmed lately.

Our blog Paradigm shift: Semi equipment tells the future, was focused on the quote: “Now more money is spent on upgrading existing facilities, while new capacity additions are occurring at a lower pace.” And now, just prior to Semicon West, we have the conclusion of the recent SEMI’s World Fab Forecast — Technology Node Transitions Slowing Below 32 nm. The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. The following chart illustrates this new paradigm:

The report states: “The cost per wafer has become an increasing concern below the 32nm node.   The expected cost reduction benefit of production at smaller nodes is diminishing and is not keeping pace with the scaling benefits in many cases.  This has widespread and fundamental implications for an industry long following the cadences of Moore’s Law… These may be contributing factors as to why some volume fabs are exhibiting a lag in beginning production of new technology node.  Now evident quantitatively for the first time, there is evidence of a clear slowdown in volume production scaling of leading technology node transitions.” (emphasis added)

It is fitting to point to the comment made to EE Times coverage on Semicon West – 13 Things I Heard at Semicon West: “No matter what Intel says, Moore’s Law is slowing down,” said Bob Johnson, a semiconductor analyst for Gartner. “Only a few high-volume, high-performance apps can justify 20 nm and beyond.” He sees problems ahead for logic chips in general,” and to follow with quotes from another EE Times article – Silicon Highway Narrows, Twists: “Most foundries have yet to start buying the capital equipment needed for the 14/16 nm node, which for many will be the first to support FinFETs, says Trafas of KLA-Tencor. Gear companies hope the orders start coming in the fall…Indeed, he says, one of the big questions many capital equipment execs will bring to this year’s Semicon West event on July 7 is, “When will the 16/14 nm investments begin?”

Since the 65 nm node, escalating costs of fab and process technology development and design, as illustrated in the chart below, put a huge pressure on the industry.

These escalating costs drove consolidation in the industry, cutting down to a handful the vendors who are still pursuing the leading edge.

At the recent (2014) SST ConFab in Las Vegas Bill McClean shared his annual report on Major trends shaping the future IC Industry. Bill reports: “Over the last two decades, the percentage of capex being spent by the top 5 has steadily increased to its current 70% with the big three of Samsung, Intel and TSMC being responsible for over 50%.” This is illustrated by the following chart.

Clearly the escalating costs drove out most but the largest vendor, but now we are facing the ”second punch” – the diminishing returns.

In the recent ITC conference Harry J. Levinson of GlobalFoundries in his talk: Lithography Issues for High Volume Manufacturing” presented the following chart:

The dramatic increase of lithography cost eats away the historical transistor cost reduction resulting from reduced dimensions, as we reported in our blog Qualcomm: Scaling down is not cost-economic anymore – so we are looking at true monolithic 3D. Quoting Qualcomm “One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down it’s not cost-economic anymore. It’s creating a big problem for us.” Accordingly we detailed in our blog that Moore’s Law has stopped at 28nmand following nodes would not provide lower transistor cost, and for most application will result in higher SoC costs.

We should not be surprised that the production ramp up below 28 nm is extremely slow. There is too much money involved to put it into the wrong place.

Going back to the SEMI World Fab Forecast, the authors ask “What’s next?” and respond: “Many in our industry are grappling with what to do as they have perceived the coming slowdown in technology node transitions.  IC manufacturers are now increasingly looking outside of conventional lithography and wafer size scaling approaches to pick up the pace of cost reduction while increasing transistor density and performance. Using memory as an example, to cope with increasing challenges in continuing to scale 2D, memory companies are looking into 3D.”

So the memory vendors already started shifting their Capex budget to scaling up with 3D NAND, instead of scaling to smaller dimension. Recently Qualcomm announced their collaboration with SMIC – China’s SMIC-Qualcomm 28-nm Deal: Why Now? – indicating more capacity build-up for 28 nm with looking forward to scaling up with monolithic 3D for logic as well. Quoting: ”Going forward, SMIC will also extend its technology offerings on 3DIC and RF front-end wafer manufacturing in support of Qualcomm”.

It is clear now that we are seeing a paradigm shift in the semiconductor equipment industry. After many decades of relentless dimensional scaling every two years, there is a change coming and we see a lower rate of dimensional scaling and exploration of other paths, to keep industry’s march on. We do believe that the next few decades will be about scaling with 3D Integration and we are pleased to see many others thinking the same.

The 2014 S3S Conference is scheduled for October 6-9, 2014, at the Westin San Francisco Airport, and would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about monolithic 3d technology for future scaling.

At the CEA-Leti Day July 8 during Semicon West, Hughes Metras, Leti's vice president of strategic partnerships for North America, introduced the lead talk about monolithic 3D technology as the "solution for scaling." The Leti device technology roadmap that Hughes presented showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to past 5 nm.Olivier Faynot, Leti's device department director and a well-known device scientist (with more than 170 papers/publications), entitled his talk "M3D, a disruptive approach for further scaling" and started with why the industry needs such a solution.

The majority of people in the industry agree that scaling past the 22nm node, though still quite technically feasible, has priced itself out of most markets. Faynot discussed the "what" (transistor costs are no longer decreasing) and the "why" (litho cost escalation and connectivity inefficiencies of energy and delay). Then he said, "If we just keep the current [2Xnm] technology, we can go farther in cost scaling."

Tech Design Forum's summary of a Qualcomm executive's DAC 2014 keynote offers more information on this crucial topic. So do a pair of EE Times blogs by Zvi Or-Bach.

The solution is to build the stack sequentially in a monolithic fashion. (See Monolithic 3D IC Technologies.) Faynot described a process flow wherein the lower level (first layer) of transistors and its interconnect are made conventionally, some interlevel metal is crafted to help the vertical interconnection, and a second layer of monocrystalline silicon is layer transferred and oxide-oxide bonded at low temperature to the top of the interlevel metal dielectric. This is a blanket layer, so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin, so that direct alignment to the lower-level alignment marks can be made with conventional equipment, and conventional alignment tolerances (single-digit nanometers) can be achieved.

Upper-level transistors are formed utilizing solid-phase epitaxial regrow (SPER) for junction doping at 475-600°C and lower-temperature processing (less than 400°C) for things like gate stacks. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. (Note that the lower-level transistor salicides are stabilized with platinum and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.)

In the Q&A session, Faynot was asked what the observed performance differences were between the upper-level and lower-level transistors. "Currently, we are achieving 95%" of the lower for the upper, he said. "We believe we can make 100%."

He also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. The laser option of solving the thermal challenge of monolithic 3D is the "crème brûlée" of methods, and Leti is "seeing good results." Hopefully, we will see published data soon. My recent Solid State Technology blog offers more information on SPER and laser processing.

Faynot was also asked if stress is a big issue. He replied that stress is not an issue. Rather, the biggest challenges are integration ones.

Leti has a PDK ready to go for those who want to design a test circuit in their monolithic 3D flow. The company has ELDO, HSPICE, Calibre, StarRC, and other files available, and it has said that monolithic 3D offers savings of at least 55% on area, 23% on performance, and 25% on power over 2D.

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December, Leti signed an agreement to work with Qualcomm. ST and IBM have also been working with Leti in various areas.

Since before 2009, CEA-Leti has been busy working on processing flows to enable monolithic 3D devices. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper "Advances in 3D CMOS Sequential Integration" (subscription required). In that paper, she and her co-authors showed results for a sequentially processed P over N (no metal between transistor layers) test chip. In an IEDM 2011 paper, she and her colleagues showed a 50nm 3D sequential structure on 10nm channel silicon, illustrated below.

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications -- both parallel and monolithic -- with an inauguration event in January 2011. In December 2013, Soitec and CEA renewed their longstanding partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference is scheduled for Oct. 6-9 at the Westin San Francisco Airport. CEA-Leti will present its work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon. With five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories, this would be a great opportunity to learn more about monolithic 3D technology.

-- Brian Cronquist is vice president of technology and IP at MonolithIC 3D Inc. He has 35 years of semiconductor industry experience as senior director of technology development and foundry at the nonvolatile FPGA provider Actel (now Microsemi), starting and building Chartered Semiconductor-Singapore (now GlobalFoundries), running startup wafer fab engineering teams at Sierra Semiconductor (now PMC-Sierra), and developing process technology at AMI and Synertek/Honeywell. He has published more than 100 technical papers in the fields of semiconductor microelectronic radiation effects and hardening, as well as new 3D-IC, logic, antifuse, and flash processes, devices, and reliability. He holds more than 60 issued/pending patents.

We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about overcoming silicon defects in monolithic 3d.

As dimensional scaling has reached the diminishing return era there is a buildup of interest in monolithic 3D as an alternative path forward. Both memory and logic vendors are moving to monolithic 3D. The memory vendors are in transition to 3D NAND and Samsung has already announced mass production of their V-NAND. BeSang has been working in monolithic 3D memory for many years and has recently signed a license agreement with SK Hynix. And now, in the logic arena, Qualcomm has voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling.” The reason is economic: … “although we are still scaling down, it’s not cost-economic anymore” (Karim Arabi, DAC 2014).

A key aspect of monolithic 3D is engineering the second layer to be especially thin, on the order of 100nm or less. This provides for tiny (10s of nm diameter) vertical connections which are dense, manufacturable, and stress-free.  They can be manufactured with well understood processing as these vertical connections would look very much like the metal to metal vias that the industry has been making for decades. This avoids the 10+ micron sized TSVs of parallel 3D and their associated reliability hazards, process cost, Keep Out Zones, and ‘newness risk’.

When performance is important, single crystal silicon based transistors are the way to go for stacked layers. So far, it seems that the best technique to form such thin mono-crystal layers with the required thickness control is to use the volume production and well proven ion-cut process. Many of the high performance monolithic 3D process flows utilize ion-cut techniques, sometimes called ‘Smart-Cut’.

However, use of ion-cut creates a small number of crystal defects in the very thin single crystal layer-transferred film. I’ll talk about some techniques that may be employed to solve this but, first, let’s explore why defects are created in the ion-cut process.

The high dosage of ions used in the process creates damage to the silicon lattice at, and near, the ion-stopping depth, such that the lattice becomes brittle there; hence, can be ‘cut’ or ‘exfoliated’ with a force (e.g., knife, water jet) or thermal anneal. After separation of the layer to be transferred from the donor substrate, this ‘donor layer’ will still have some of the silicon lattice damage from the embrittlement on one surface, and may also have some damage from the splitting process itself. Soitec, in the manufacture of SOI wafers, utilizes 1100-1200°C thermal anneals (both oxidizing and non-oxidizing) in combination with chemical-mechanical polishing (CMP) to repair the crystalline damage, as part of its SmartCut (ion-cut) process. However, these damage repair anneals are not compatible with the commonly used low melting point/hi-diffusivity interconnect metals like copper or aluminum of the lower device layer in a 3D stack. BeSang has a nice tutorial video explaining this on their website. Here’s a snapshot:

Further, the passage of the ions used in the ion-cut process creates a lower level of damage to the silicon lattice of the bulk of the to-be-transferred donor layer as the ions pass thru the lattice. This bulk lattice damage can cause junction leakage, and lower the performance of devices. Annealing this type of lattice damage requires temperatures of about 600°C or greater, which – again – is incompatible with the commonly used interconnect metals of the lower device layers in a 3D stack.

Now let’s look at two silicon device proven methods that are available to overcome the ion-cut induced defects and can be applied to the ion-cut layer transfer for monolithic 3D devices and  structures.

Radu et al. of Soitec, in U.S. Patent Application Publication 2013/0026663, describe a method for curing defects associated with ion-cut implantation by a CMP and then a laser anneal of the transferred singe crystal silicon layer.

Singe crystal silicon donor wafer 1 is ion-implanted with a heavy dose of hydrogen or helium ions to create a brittle region 11 as shown in Fig. 1A. Then the donor wafer is flipped over and bonded to the top of a receiver substrate 2 that may have transistors and interconnect metallization 20, shown in Fig. 1B. Layer 3 is a low thermal conductivity or thermal insulating layer that will help thermally protect the transistors and interconnect metallization 20 of substrate 2.

Fracturing along the brittle region 11 may be done with any number of techniques, such as mechanical knife, water or gas jet, etc., leaving behind transferred silicon layer 10. The transferred layer surface 12 may be CMP’d to remove the majority of the roughness and surface defects, resulting in Fig. 1C.

However, there are still bulk lattice damage centers in transferred silicon layer 10. Radu et al. takes care of them thermally by applying pulses of electromagnetic energy. Specifically mentioned are the pulsed lasers of Excico and JPSA.

The wavelength of the irradiation is chosen such that the majority of the pulsed energy is absorbed in transferred layer 10. The low thermal conductivity or thermal insulating layer 3 minimizes the thermal diffusion from the heated transferred layer 10 to the interconnect metallization and must be designed properly to handle the thermal pulse of the layer above. Temperatures high enough to cure the ion-cut induced defects and reactivate any ion-cut deactivated dopants in transferred layer 10 can be achieved. For example, as Figs. 5A and B show, the transferred thin (0.8um in this case) silicon layer (a) may achieve a temperature well above 1000°C from the laser pulse, and the interface (b) between substrate 2 and thermal insulating layer 3 will stay well below 400°C.

Fig. 5A shows the JPSA laser at 193nm and 20ns pulse FWHM (Full-Width Half-Max) and Fig. 5B shows the Excico laser at 308nm and 160ns pulse FWHM.

We have also published work on laser annealing at 2013 IEEE 3DIC and 2013 IEEE S3S Conferences showing how scaling trends can make monolithic 3D practical and the substantial design space of the laser wavelength/energy/pulse width, top layer thickness, and shielding/thermal protection layers which can make single crystal monolithic 3D possible.

Clearly, stacking of ultra-thin layers of defect free single crystal silicon can be readily accomplished and the tools to realize this are available from at least two vendors.

At ESSDERC (43rd Solid State Device Research Conference) in September of 2013, Radu et al. in collaboration with CEA-Leti, presented a different way of obtaining low defect single crystal silicon stacks. Low temperature Solid Phase Epitaxial Re-grow (SPER) is combined with ion-cut to demonstrate defect free diodes with processing temperatures less than 500°C.

SPER utilizes a small amount of crystalline silicon as a template to re-crystallize an amorphous silicon layer at temperatures just above 475°C and can be used to activate dopants above the solubility limit.

SPER can be combined with low temperature ion-cut (SmartCut) and bonding techniques to obtain defect free single crystal devices. Donor wafer doped silicon is amorphized before bonding and ion-cut implanted to create the brittle zone, flipped and bonded to the handle, SPER processed, and then thinned to remove the End Of Range defects.

No crystalline defects were seen utilizing the usual physical means:

However, the tougher test to satisfy is always the electrical one. Radu showed excellent diode characteristics, resistivity, concentration and mobility recovery. Here are some of their diode I(V) curves:

I would not be surprised if demonstration of transistors is published in the near future.

So, hopefully I have given you at taste of how ready an important piece of the monolithic 3D puzzle is to delivering on its promises. Back in December 2013, Soitec and CEA-Leti renewed their long-standing partnership for five additional years. I think it is safe to say that more will be coming soon.

Give me a call or email if you want to talk more…

Monolithic 3D moving forward for SoC and logic devices. The latest news in the semiconductor industry reveals an important strategic relationship between Qualcomm Technologies and Semiconductor Manufacturing International Corporation SMIC. The latest is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in mainland China. "SMIC is further strengthening its strategic relationship with Qualcomm Technologies. SMIC will work with Qualcomm Technologies in bringing new 28nm design-ins and products for the growing mobile communication industry. Going forward, SMIC will also extend its technology offerings on 3D IC and RF front-end wafer manufacturing in support of Qualcomm Technologies". As Zvi Or-Bach, Presindet and CEO of MonolithIC 3D Inc. recently reported in our blog: "Qualcomm Calls for Monolithic 3D IC", first developing EDA with help of Georgia Tech., than support the process development at CEA Leti, and now setting up volume production with SMIC. This is the first announcement of moving to monolithic 3D for SoC and logic devices after Samsung already reported mass production of for monolithic 3D in first 3D vertical NAND flash.

Source:

- SMIC and Qualcomm Collaborate on 28nm Wafer Production in China – Solid State Magazine [http://electroiq.com/blog/2014/07/smic-and-qualcomm-collaborate-on-28nm-wafer-production-in-china/];

- China's SMIC-Qualcomm 28-nm Deal: Why Now? - EE Times [http://www.eetimes.com/document.asp?doc_id=1322988&piddl_msgid=306046#msg_306046];