We are proud to announce that our paper, “Design of Highly Stackable Charge Trap-Based 3D DRAM,” was recognized with the Best Paper Award at IEEE TENCON 2025. This recognition highlights research focused on addressing important challenges in future memory technologies and advancing the development of highly scalable memory architectures.
As conventional DRAM technologies approach scaling limitations, challenges such as RC delay, reliability constraints, power consumption, and integration complexity continue to become increasingly significant. Existing approaches to next-generation 3D DRAM often face difficulties in stacking large numbers of memory layers due to complex memory cell structures. To address these limitations, our work proposes a novel charge trap-based 3D DRAM (CT 3D DRAM) architecture designed for highly scalable three-dimensional integration.
The proposed architecture utilizes a simplified one-transistor (1T) memory cell with a poly-Si channel and Schottky barrier source/drain contacts formed by metal silicide. Through this design approach, the structure aims to reduce complexity while improving scalability, power efficiency, and thermal management for future memory systems.
To validate the proposed concept, the study combined device design through simulation with experimental fabrication and characterization of planar CT DRAM devices. The results demonstrated promising memory operation characteristics, including reliable program and erase behavior, retention performance, and strong endurance characteristics.
The proposed CT 3D DRAM architecture also offers advantages in power consumption and heat dissipation. By utilizing metal source/drain structures and optimized bit-line and word-line configurations, the design demonstrates the potential for highly stacked memory architectures while maintaining efficient device operation. This work identifies CT 3D DRAM as a promising candidate for future high-density memory applications and emerging memory platforms such as CXL memory.
Download link of the Paper
The proposed architecture utilizes a simplified one-transistor (1T) memory cell with a poly-Si channel and Schottky barrier source/drain contacts formed by metal silicide. Through this design approach, the structure aims to reduce complexity while improving scalability, power efficiency, and thermal management for future memory systems.
To validate the proposed concept, the study combined device design through simulation with experimental fabrication and characterization of planar CT DRAM devices. The results demonstrated promising memory operation characteristics, including reliable program and erase behavior, retention performance, and strong endurance characteristics.
The proposed CT 3D DRAM architecture also offers advantages in power consumption and heat dissipation. By utilizing metal source/drain structures and optimized bit-line and word-line configurations, the design demonstrates the potential for highly stacked memory architectures while maintaining efficient device operation. This work identifies CT 3D DRAM as a promising candidate for future high-density memory applications and emerging memory platforms such as CXL memory.
Download link of the Paper
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