We have a guest contribution today from Ze'ev Wurman, MonolithIC 3D Inc.'s Chief Software Architect. Ze'ev discusses the upcoming IITC and the contribution of 3D technology to minimizing wire-length distribution.

Does Size Matter?

The next International Interconnect Technology Conference (IITC 2012) will be held in San Jose in a couple of weeks (June 4-6). This is a good opportunity to recall that, in some sense, the reason for scaling silicon down has changed in recent years from packing more transistors in a square (or cubic) millimeter to increasing functionality and performance at reduced power. An ever higher fraction of the power dissipation resides in the interconnect – both in the net switching itself as well as in the ever-increasing number of repeaters required to re-power more and more “long” nets.

Estimates of the area dedicated to repeaters as technology shrinks vary but even if the early predictions of 70% cells being dedicated to repeaters at 32 nm may have not come to pass (Saxena, TCAD 2004), a large fraction of chip power is now dissipated by interconnect structures. This is particularly true in FPGAs where the interconnect share of routing-related dynamic power may easily reach 2/3 of the power, but even non-programmable devices have been reported to have half of their power dissipated in the wires already at 90nm. The following slide is from the 2006 High Performance Embedded Computing workshop.

Last year IITC included a paper from Georgia Tech (Dae Hyun Kim, et al., Impact of Through-Silicon-Via Scaling on the Wirelength Distribution of Current and Future 3D ICs) that explores the impact of 3D on the average wire-length of deep submicron ICs. This paper differs from many others in that it explores the impact as a function of TSV size, and it models TSVs from the currently feasible 5 micron, with a 5:1 aspect ratio for the corresponding 25 micron thick silicon layer, down to a futuristic 100 nm, with a 50:1 aspect ratio for a 5 micron thick layer. Such futuristic TSV actually gets close to a monolithic process, which can achieve silicon thickness of one micron and below. Here is a key chart from this paper:

As we can see, a small-sized TSV can significantly reduce the average wire-length by up to 50%, and reflects an improvement equivalent to two or three technology generations. In other words, a 4-way stacked 32nm chip with monolithic-style vertical connectivity can have wire-length distribution as good as a 16nm cutting edge technology, with the associated reduction in power and increase in performance, but using a relatively inexpensive and depreciated fab line.

Yet there is a fly in this ointment – TSVs with aspect ratio of 50:1 are not likely to happen, and using nanometer-TSV with extremely thin silicon layers to maintain AR below 10 creates problems of its own. Just recently IMEC reported stress issues at 25 micron thickness and “found that increase in the die thickness from 25 to 50 um resulted in a stress reduction of 3X. Final conclusions were that 50 um thickness die were currently much better option for scalable manufacturable process.” In other words, the road to nanometer-scale vertical connections does not go through scaling down TSVs but through monolithic process and layer transfer.

I find all this a nice illustration of the importance of the monolithic stacking approach that is also easily visible using our free simulator, IntSim.

Transformation to 3D monolithic stacking is much more than simply saving on a footprint by slicing and stacking the same design. The rich vertical connectivity offered by monolithic stacking significantly reduces the average distance between source and destination and therefore improves performance, saves power, saves total area, and allows players to continue using older process fabs to achieve cutting edge results at a cheaper cost. The chart below illustrates such savings at 22nm technology:

The future of Moore’s Law and the continued well-being of our industry is in the small nanometer-sized TSV, not in the big micron-sized TSVs used today that are so hard to manage. And let’s hope that the upcoming IITC will be at least as interesting as last year’s.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about the latest news regarding the reversal of the trend from Foundry model back to the IDM model.

Are we facing a dramatic reversal of the trend from the Foundry model back to the IDM model???

Recently Rick Merritt of EE Times reported on his interview with Mark Bohr, "Mr. Process Technology at Intel," and wrote: "It’s the beginning of the end for the fabless model according to Mark Bohr."

Quite naturally this caused many responses, with the majority of them hinting that Intel is trying to break into the smart mobile space by sowing doubt in the future of the existing ecosystem around TSMC-ARM and multiple fabless vendors.

We recently wrote two very relevant blog entries:

Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies? 04/02/2012
and
Why Samsung will give Morris Chang sleepless nights 02/05/2012


With recent reports about Qualcomm having issues with TSMC, Apple not being able to shift out from Samsung (their competitor) to TSMC, AMD having severe issues and trying to shift some of manufacturing from GlobalFoundries to TSMC, and straight out statements such as:  "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless," one can't avoid the question: Are we facing a dramatic reversal of the trend from the Foundry model back to the IDM model???


It does seem that advanced scaling these days provides a significant advantage to the integrated model, where trade-offs between design, library EDA, and manufacturing, provide a better end product. Such an integration advantage manifests itself with respect to yield, now that the majority of the yield losses are design-related rather than random defects, and to manufacturing cost, as some of the layers needs double or even triple/quad patterning. 


Accordingly, this might explain why both TSMC and GlobalFoundries recently announced investment in 3D IC processing lines (TSMC plans 3-D IC assembly launch early in 2013, GlobalFoundries installs gear for 20-nm TSVs). As the current scaling trend works against them, they both chose to move the game to a court where an ecosystem would be more powerful than corporate vertical integration.


We at MonolithIC 3D Inc. are very pleased to see 3D ICs becoming a key business strategy, and truly believe that adding monolithic 3D manufacturing capabilities will extend foundries’ strategic benefits even further. Monolithic 3D, with its 10,000x better vertical connectivity, provides an exciting alternative to pure dimensional scaling. Moore's law is about doubling the number of transistors, which could be easily achieved using existing process and lithography by simply doubling the number of layers carrying transistors. Scaling through the third dimension provides power, speed, and cost benefits similar – or even better -- than we once used to get from dimensional scaling (see "Why Monolithic 3D" for more information).


In addition, monolithic 3D provides benefits that cannot be achieved with dimensional scaling such as pulling out embedded memory into another layer on top of the logic. In a typical SoC the embedded memory may represent 50% of the die area and include hundreds of memory macros, requiring too many vertical connections for TSV but is a very simple task for monolithic 3D integration. A dedicated memory layer also allows optimizing the first layer for logic and the second layer for memory, which could be even a DRAM rather than SRAM, and would need fewer costly metal layers. Another advantage is the realization of logic-cone-level logic redundancy, as described in Monolithic 3D IC Could Increase Circuit Integration by 1,000x and in Redundancy & Repair with Monolithic 3D.


In summary, the current trend in the semiconductor industry indicates that IDMs have a significant advantage in the leading edge dimensional scaling race. Foundries recognize it and are responding by adding 3D capabilities. They could do even better by also adding monolithic 3D.