We have been hearing about the imminent demise of Moore’s Law quite often recently. Most of those predictions have been targeting the 7nm node and 2020 as the end point. But we need to recognize that 28nm is actually the last node of Moore's Law, beyond which we can make smaller transistors and pack more of them into the same die size but we can not reduce the cost, and in most cases, the same SoC will have a higher cost!

The famous Moore's Law was presented as an observation by Moore in his 1965 Electronics paper "The future of integrated electronics". Quoting: "The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years." Clearly Moore's Law is about "The complexity for minimum component costs", and the minimum component cost will be at the 28nm node for many years, as we will detail in the remainder of this blog.

The following chart was presented by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during Semi’s recent ISS 2014 Europe Symposium:

Hartmann is making the case that the "Moore's Law discontinuation due to cost stagnation or increase" applies to bulk technologies, which is the technology base of the majority of the industry.

ST information is backed by Globalfoundries as we can see from the following chart presented at the 2013 SOI Consortium workshop in Kyoto, Japan.

The above Globalfoundries chart shows that the lowest cost transistor is at the polySiON 28nm node.

Beyond 28nm, scaling becomes extremely expensive due to double litho, HKMG, FinFET, etc. The increase in wafer cost is illustrated by the recent NVidia chart from Semicon Japan (Dec. 2013) below:

The increase in wafer cost eats away the 2X transistor density gain per node as is illustrated by this ASML slide from Semicon West (2013):

However, the SoC end product silicon area is dependent on the SRAM bit cell size far more than on the general transistor density. This is the fundamental challenge now facing dimensional scaling - SRAM Bit scaling has been dramatically slowed beyond 28nm.
At 28nm the bitcell size is about 0.12µm². The following chart by imec reported in Status update on logic and memory roadmaps (Oct 2013):

Beyond 28nm, the SRAM bit scaling rate is about 20% per node instead of the historical 50%. And the situation is actually far worse as is illustrated by the following chart, presented in an invited paper by Dinesh Maheshwari, CTO of Memory Products Division at Cypress Semiconductors, at ISSCC 2014. It was also at the center of our recent blog "Embedded SRAM Scaling is Broken and with it Moore's Law."

Accordingly, the SRAM Mb/mm² scales far less than the bitcell due to factors such as:

• Smaller transistors have less drive, thus requiring breaking the SRAM into smaller blocks, creating more overhead area costs
  
• Smaller transistors have a higher level of variation, also requiring breaking the SRAM into smaller blocks
  
• The need for more overhead such as read assist circuits and write assist circuits
  
• Tighter metal pitches begat higher RC, thus again requiring breaking the SRAM into smaller blocks
  

Moreover, SoCs need I/O pads and their circuits, and other analog circuitry, all of which scale at a rate far less than 2x per node.

Furthermore, the exponential increase in BEOL RC as is illustrated by the following chart, presented by Geoffrey Yeap, VP of Technology at Qualcomm in his invited IEDM 2013 paper, results in an exponential increase of number of drivers and repeaters. This suppresses the effective gate density increase to only a factor of x1.6, or less.

Summarizing all of these factors, it is clear that for most SoCs, the 28nm will be for the coming years the node for "minimum component costs".

As an industry, we are facing a paradigm shift because dimensional scaling is no longer the path for cost scaling. New paths need to be explored such as SOI and monolithic 3D integration. It is therefore fitting that the traditional IEEE conference on SOI has expanded its scope and renamed itself to IEEE S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This new unified conference will help us to improve efficiency and establish this conference as a world class international venue to present and learn about the most up-to-date trends in CMOS and post-CMOS Scaling. The conference will provide both educational and cutting edge research in SOI and monolithic 3D and other supporting domains. These technologies were not part of the mainstream semiconductor past; accordingly, it is a golden opportunity to catch-up with these technologies now. Please mark your calendar for this opportunity to contribute and learn about SOI and monolithic 3D technology, as these technologies are well positioned to keep the semiconductor industry's future momentum.

While many have recently predicted the imminent demise of Moore’s Law, we need to recognize that this actually has happened at 28nm. From this point on we will still be able to double the amount of transistors in a single device but not at lower cost. And, for most applications, the cost will actually go up.

Let’s go back to 1965 and Moore’s paper in "Electronics, Volume 38, Number 8, April 19, 1965 The future of integrated electronics". The following figure represented Dr. Moore’s observation with regard to three consecutive technology nodes. Quoting: ..."the cost advantage continues to increase as the technology evolves toward the production of larger and larger circuit functions on a single semiconductor substrate. For simple circuits, the cost per component is nearly inversely proportional to the number of components, the result of the equivalent piece of semiconductor in the equivalent package containing more components. But as components are added, decreased yields more than compensate for the increased complexity, tending to raise the cost per component. Thus there is a minimum cost at any given time in the evolution of the technology"

“The complexity for minimum component costs has in-creased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years”The public information we now have indicates that:

a. The 28nm node is quite mature and we cannot expect that optimum integration vs. yield will double for it.

b. All that we know about the more advanced nodes (22/20nm, 16/14nm, …) indicates that the cost per transistor is not going to be reduced significantly vs. that of 28nm.

c. What we now know about embedded SRAM (“eSRAM”), I/O and other analog functions, indicates that most SoCs will end up at a higher cost as compared to 28nm.

Let’s recap using a few public charts to help tell the story of how we have reached that conclusion.

It starts with the escalating cost of lithography as illustrated in this 2013 chart from GlobalFoundries:

We should mention here that based on information released during last week’s SPIE Advanced Lithography (2014), it seems EUV is not going to be ready for the N+1 node (10nm). These costs, as well as other capital costs, increase, and thus drive up the wafer price as illustrated by the recent NVidia chart from Semicon Japan (Dec. 2013) below:

This escalating wafer cost eats away the higher transistor density gains, as articulated by NVidia and calculated by IBS’ Dr. Handel Jones and shown in the following table:

This is nicely illustrated by ASML slide from Semicon West (2013) below:

But this is just the smaller part of the problem. Advanced Integrated Circuits comprise far more than just logic gates. An SoC today contains a significant amount of embedded memories, I/Os and other support analog functions. Further, they include a large number of drivers and repeaters to reduce the RC delays that are escalating due to dimensional scaling. All of these scale very poorly.

The following chart was presented in an invited paper by Dinesh Maheshwari, CTO of Memory Products Division at Cypress Semiconductors, at ISSCC2014. It was also at the center of our recent blog “Embedded SRAM Scaling is Broken and with it Moore’s Law.”

This chart shows that eSRAM scaling is ~1.1X for decent performance as compared to ~4X for logic gates. The chart below (from Semico Research) shows that an average SoC has more than 65% of its die area allocated to eSRAM.

Consequently, the average SoC scaling to 16/14 nm could result in a significant cost increase, and hence 28nm is effectively the last node of Moore’s Law. To make things even worse, the remaining 35% of die area is not composed of only logic gates. More than 10% of the die area is allocated to I/O, pads and analog functions that either scale poorly or do not scale at all. And even in the pure logic domain scaling could not reach the potential 4X density improvements. The following chart was presented by Geoffrey Yeap, VP of Technology at Qualcomm, in his invited paper at IEDM 2013:

It illustrates the escalating interconnect RC delay with scaling – about 10X for two process nodes. This escalating RC delay eats away a significant part of the increase in gate density due to the exponential increase in buffer and driver counts and a similar increase in ‘white’ area kept for post layout buffer insertion, etc.

Final note: it seems clear that dimensional scaling has now reached negative returns, as is illustrated by the following GlobalFoundries chart:

The time is now to look for other alternatives, among which monolithic 3D seems a most compelling option. It allows us to leverage all our current silicon knowledge and infrastructure while continuing with Moore’s Law by scaling up at 28nm.

The chart below was presented at ISSCC 2014 by Dinesh Maheshwari, CTO of Memory Products Division at Cypress Semiconductors. The slide clearly illustrates that embedded SRAM ("eSRAM") scaling is broken. 

Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let’s discuss it further.Instead of the expected 4X density improvement for a large memory block with two nodes of scaling, the improvement range is only 1.6X for low performance to 1.1X at good performance. Since eSRAM dominates most SoC silicon area, we have to conclude that dimensional scaling is broken as well. Let’s discuss it further.
The following slide was presented by Intel at their recent analyst day. It illustrates the impact of dimensional scaling on advanced wafer cost ($/mm²) mostly due to the escalating cost of lithography. Intel believes it can compensate for this exponential wafer cost increase by increasing their transistor density (mm²/transistor) to maintain historical cost reduction of transistor cost ($/transistor).

Perhaps it can, but at this time we keep hearing about delays in ramping up the 14nm line. (See "Broadwell Coming, but Not Until the End of the Year.") This reminds us of the famous joke, "Will make it on the volume," since increasing transistor density is directly related to the aggressive dimensional scaling that was driving the escalating wafer cost in the first place.

Most industry players confirm that cost-reduction for transistors has stopped beyond the 28nm process node, as is illustrated by the ASML chart below. This chart was presented at SEMICON West 2013.

It also clear that EUV is not going to be ready for the 16/14nm node. In fact, most observers are in agreement that EUV will also miss the 10nm node.

For some applications, keeping the cost-per-transistor about the same while reducing power or increasing speed might still justify going to 20nm or 14nm. The IMEC/Cypress chart above indicates that this will not be true for most designs. The fraction of the die area used for eSRAM is consistently growing with scaling, and it already regularly exceeds 50%. The following two charts from Semico, which were recently updated, illustrate this for advanced SoC and average SoC implementations.

Taking into account that 16/14 nm silicon is almost twice as expensive per unit area as that of 28 nm, this implies that beyond 28nm, SoC costs for the same functionality will escalate for most designs, and this will dampen even further the transition to advanced nodes such as 20nm or 16/14nm!

This clearly seems to indicate a paradigm shift after 50 years of consistent cost-reduction with dimensional scaling. Indications of this were already presented in our blog, Paradigm Shift: Semi Equipment Tells the Future, and in recent news articles such asAnalysis: ASML Stops 450mm Dead and Intel Cancels Fab 42.

Some people will attempt to brush aside Maheshwari's chart shown above, yet multiple sources indicate this is a true new reality that should not be ignored. We first reported it in our blog on ASML at Semicon West 2013, SRAM Scaling Has Stopped, which was backed up by the following IMEC chart as reported in Status Update on Logic and Memory Roadmaps.

This IMEC chart shows that the reduction of eSRAM bitcell area below 28nm is much less than the 50% expected size-reduction per technology node.

Furthermore, TSMC reported at IEDM 2013 that their bitcell for 16nm is 0.07µm2, and at ISSCC2014 Samsung presented similar results for 14nm finFETs as shown in the following slide.

It appears that the TSMC and Samsung bit cell sizes are in line with the IMEC table presented above. It also appears that these trends become even worse when comparing the size of high performance block RAM between technology nodes as presented by Maheshwari.

In the case of block RAM, additional aspects need to be taken into consideration, such as the die size impacts required for implementing a new technology such as finFET. In its ISSCC 2014 paper, Samsung identified complications involved with the transition from planar to finFET, such as quantized width, strong PMOS, and a lack of the body-bias effect. Samsung disclosed a die size impact of 0.87% in order to add a Disturbance Noise Reduction (DNR) scheme to deal with its larger, more stable High Performance (HP) bit-cell. Samsung did not disclose the area impact of its proposed Negative Bitline write assist scheme used with their high density HD bit-cell, but we can assume it is likely significantly larger than the proposed scheme for the HP bit-cell.

Some of the issues that are holding back scaling eSRAM were presented in our recent blog: The Most Expensive SRAM in the World -- 2.0. Bitcell scaling is getting harder, much harder, and even more so is the ability to scale large blocks of embedded SRAM. When we add the fact that the amount of embedded memory is growing faster than the amount of logic cells, one can predict dark clouds for SoC scaling beyond 28nm. It seems that brute-force scaling is simply not practical anymore, but two technology innovations could solve the SRAM memory scaling problem and provide a scalable high density memory if adopted soon by the industry.

The first innovation is the One-Transistor SRAM (1T SRAM) developed by Zeno Semiconductor. This 1T SRAM utilizes an existing fab process, provides a 90% bitcell size reduction versus conventional 6T SRAM, and it will keep scaling beyond 28nm. The second innovation is that of monolithic 3D, which enables a very effective heterogeneous integration scheme, thereby allowing for the SRAM layer to be optimized for memory while the logic layer can be optimized for logic. (See Monolithic 3D eDRAM on Logic.)

So, what do you think? Do you still believe that traditional scaling is the way to go? Or do you think that we will need to rely on new technologies like 1T-SRAM and monolithic 3D in order to maintain the pace of SoC development?