Dimension Scaling and the SRAM Bit-Cell
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses Dimension Scaling and the SRAM Bit-Cell.
IEEE International Solid-State Circuit Conference Feb 17-21, 2013 just ended at San Francisco last week, and the issue of dimension scaling as it relates to EUV and future per transistor device cost was an important item in the plenary session. But the issue of scaling as it relates to the SRAM was an important item in many of the session as we will farther discus herein.
As widely reported Martin van den Brink ASML Executive VP & CTO articulate that without EUV cost of logic transistors is most likely go up with scaling as was illustrated by his following slide:
As widely reported Martin van den Brink ASML Executive VP & CTO articulate that without EUV cost of logic transistors is most likely go up with scaling as was illustrated by his following slide:
Source ASML
The above slide was presented after Martin had presented another non encouraging slide, showing a Broadcom chart of increasing cost per gate with dimension scaling together with Nvidia famous chart of no more crossover of transistor cost below 28nm and GlobalFoundries chart showing some limited value for EUV:
Figure 2
We may attribute Martin statements to ASML interest of promoting EUV, but since ASML already received significant EUV participation from INTEL, Samsung and TSMC it might indicate farther problems on the road to bring EUV to the market. We don't know if EUV is ever become real but we already know very well that it is been delayed and delayed again. It was made public recently that it probably already missed the 10nm process node.
The real interesting slid presented by van den Brink is the following:
The real interesting slid presented by van den Brink is the following:
Figure 3
This chart brings up an important aspect of dimension scaling that was not discussed much before - the scaling of the SRAM bit-cell.
Accordingly the SRAM bit-cell size might not be reduced from 20nm to 10 nm and might even get larger at 7nm as it may need more than 8 transistors.
Modern logic devices needs significant amount of embedded SRAM in fact more than 50% of the logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010)
Accordingly the SRAM bit-cell size might not be reduced from 20nm to 10 nm and might even get larger at 7nm as it may need more than 8 transistors.
Modern logic devices needs significant amount of embedded SRAM in fact more than 50% of the logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010)
Figure 4
The dominating embedded SRAM bit-cell used to be the 6 transistor cell. This cell was for many years hand crafted using special design rules by the foundries for every new technology node. But the SRAM cell is a unique structure that is not obeying normal logic design rules as it use output against output any time a write cycle is been performed. In many cases it is the cell that is the most sensitive to the process parameters (as been represented by the SPICE deck) and highly impact end device yield. It well known that scaling the SRAM bit-cell had become harder and harder. Some vendors had already moved away from the 6T (six transistor) to 8T (eight transistors) bit-cell as we could have learn in this ISSCC by the number of papers the were presenting 8T SRAM. And even those the kept the 6T had presented extra support circuits to enable it.
As SRAM bit scale is becoming less than 50% we had seen in the past, the end device scaling cost could be even more disappointing than the transistor or gate cost illustrations above.
Well aware of this IBM had been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that at 32nm product line IBM use of the embedded DRAM gave them the equivalent of process node benefits. Yet as of now most other vendors had not adapted the eDRAM due to process complexity it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimension scaling as the DRAM capacitor will be very hard to scale, the extra power for DRAM is not available and the cost of advance process development is too high to add in extra complexity.
Accordingly we could learn from these recent ISSCC that dimension scaling is facing the cost challenges we were aware of before plus one that we have might been less aware of but could hit us both on cost and on power due to the incompatibility of the 6T SRAM bit-cell with scaling.
As we suggested before, now that monolithic 3D is practical, we could advance and maintain Moore's Law by augmenting dimension scaling with 3D IC scaling, allowing depreciation and advance engineering to bring down costs and improvements to power and performance. And additional option is to replace the 6T SRAM bit-cell with the 1T - two stable states floating body memory cell invented by Zeno Semiconductor. The Zeno bit-cell is getting better with scaling save ~80% of the silicon area and require far less power, yet it provides two stable memory states, and would work on existing logic process.
As SRAM bit scale is becoming less than 50% we had seen in the past, the end device scaling cost could be even more disappointing than the transistor or gate cost illustrations above.
Well aware of this IBM had been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that at 32nm product line IBM use of the embedded DRAM gave them the equivalent of process node benefits. Yet as of now most other vendors had not adapted the eDRAM due to process complexity it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimension scaling as the DRAM capacitor will be very hard to scale, the extra power for DRAM is not available and the cost of advance process development is too high to add in extra complexity.
Accordingly we could learn from these recent ISSCC that dimension scaling is facing the cost challenges we were aware of before plus one that we have might been less aware of but could hit us both on cost and on power due to the incompatibility of the 6T SRAM bit-cell with scaling.
As we suggested before, now that monolithic 3D is practical, we could advance and maintain Moore's Law by augmenting dimension scaling with 3D IC scaling, allowing depreciation and advance engineering to bring down costs and improvements to power and performance. And additional option is to replace the 6T SRAM bit-cell with the 1T - two stable states floating body memory cell invented by Zeno Semiconductor. The Zeno bit-cell is getting better with scaling save ~80% of the silicon area and require far less power, yet it provides two stable memory states, and would work on existing logic process.
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