A recent Semi™ report titled SEMI Reports Shift in Semiconductor Capacity and Equipment Spending Trends reveals an important new trend in semiconductors: "spending trends for the semiconductor industry have changed. Before 2009, capacity expansion corresponded closely to fab equipment spending.  Now more money is spent on upgrading existing facilities, while new capacity additions are occurring at a lower pace, to levels previously seen only during an economic or industry-wide slowdown".
   Looking at the semi-equipment booking should be the first step in any attempt to assess future semiconductor trends. While talking is easy, spending billions of dollars is not. Vendors look deeply into their new design bookings and their future production needs before committing new dollars to long lead purchases for their manufacturing future needs. In the past decade it was relatively simple, as soon as a new process node reached production maturity vendors would place new equipment orders knowing that soon enough all new designs and their volume will shift to the new process node. But the Semi™ report seems to tell us that we are facing a new reality in the semiconductor industry – a Paradigm Shift.
  
  A while ago VLSI Research Inc. released the following chart with the question: Is Moore’s Law slowing down?

  The chart above indicates a coming change in the industry dynamic, and 2013 might be the year that this turns out to be a Paradigm Shift.
  Just few weeks ago at the SEMI ISS conference, Handel Jones of IBS presented many very illuminating charts and forecasts. The following chart might be the most important of them and it is the revised calculation of per gate cost with scaling.

  Clearly the chart reveals an unmistakable Paradigm Shift as 28nm is the last node for which dimensional scaling provides a per gate cost reduction. It makes prefect sense for the vendors and their leading edge customers to respond accordingly. Hence it easy to understand why more equipment is being bought to support 28nm and older nodes.
  The following table, also from Jones, illustrates this new reality.

  In the equipment business, more than 50% of demand comes from the memory segment where the dollars per sold wafer are much lower than in logic. It seems that the shift there has already taken place. Quoting Randhir Thakur, Executive Vice President, General Manager, Silicon Systems Group, Applied Materials, Inc -as was recently published in The shift to materials-enabled 3D: " our foundry/logic and memory customers that manufacture semiconductors are migrating from lithography-enabled 2D transistors and 2D NAND to materials-enabled 3D transistors and 3D NAND"..."Another exciting inflection in 2014 is our memory customers’ transition from planar two-dimensional NAND to vertical three-dimensional NAND. 3D technology holds the promise of terabit-era capacity and lower costs by enabling denser device packing, the most fundamental requirement for memory". Which fits nicely with the following illustration made by Samsung as part of their 3D-NAND marketing campaign.

  As for the logic segment, the 3D option is yet to happen. But as we wrote in respect to 2013 IEDM - More Momentum Builds for Monolithic 3D ICs. The following chart from CEA Leti illustrates the interest for monolithic 3D:

  It should be noted that monolithic 3D technology for logic is far behind in comparison to memory. Given that the current issues with dimensional scaling are clearly only going to get worse, we should hope that an acceleration of the effort for logic monolithic 3D will take place soon. In his invited paper at IEDM 2013, Geoffrey Yeap, VP of Technology at Qualcomm, articulates why monolithic 3D is the most effective path for the semiconductor future: "Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law." As illustrated by his Fig. 17 below.

  So, in conclusion, our industry is now going thru a paradigm shift. Monolithic 3D is shaping up as one of the technologies that would revive and sustain the historically enjoyed growth and improvements well into the future. The 2014 S3S conference scheduled for October 6-9, 2014 at the Westin San Francisco Airport will provide both educational opportunities and cutting edge research in monolithic 3D and other supporting domains. Please mark your calendar for this opportunity to contribute and learn about the new and exciting monolithic 3D technology.  

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the latest news in semiconductor industry, the headlines that dominated last week's news papers about TSMC and Intel. 

 On January 14, 2014 we read on the Investors.com headlines page - Intel Seen Gaining Huge Pricing Advantage Over TSMC. Just three days later comes the responding headline: TSMC: We're "Far Superior" to Intel and Samsung as a Partner Fab.
These kinds of headlines are not seen too often in the semiconductor business domain and it is not clear what the objectives are for such. It will be hard to believe that this is an attempt to manipulate the investor community, yet there are only a handful of super high volume design wins that are driving the leading edge devices, and for those wins the fight should be taking place in the 'board' room. So let’s dive a bit into the details behind these headlines.
 The first headline relates to Jefferies analyst Mark Lipaci releasing an analysis report stating: "Intel will have a die size and transistor cost advantage over Taiwan Semiconductor (TSM) for the first time by fourth-quarter 2014, which could lead to a 50% pricing advantage in processors in 12 months, and a 66% pricing advantage in 36 months". We can find more information in the blog titled: Intel: Primed for Major Phone, Tablet Share on Cheaper Transistors, Says Jefferies. Quoting Lipaci: "At the same time that Intel has started focusing on computing devices in mobile form factors, it appears that TSMC is hitting a wall on the transistor cost curve. The chart below was presented by TSMC’s CTO. We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC for the first time ever in 4Q14. We believe Intel extends that cost lead 24 months after than in 2016."
Lipaci then used the following chart to illustrate the build up of Intel advantage vs. TSMC.

The Jefferies report goes further and provides the following charts for 14nm and 10nm.

 Clearly the primary advantage that the report is pointing out is the lack of the double margin associated with the foundry model vs. the IDM model. It seems that this argument has clearly been disproven by now. In the early days of the foundry industry most IDMs would argue that the foundry model would not work because of the double margin aspect - the foundry would need about 50% gross margin and then the fables company would need an additional 50% gross margin - which would make it completely uncompetitive vs. the IDM. 20 years later it was proven, again, that there is no "free lunch". The chip fabrication business needs a margin to be sustainable and the design business needs a margin to be sustainable. And the better business model is to have those managed by different companies as each could build excellence in its own value proposition. Intel did enjoy for many years effective exclusivity in the Windows based processors. Intel has not been able so far to show much success in mobile or any other non-Windows market. Since Intel is now trying to position themselves as a better foundry than TSMC, then clearly for their potential foundry customers this double margin argument is moot.  
 The charts above also compare Intel’s cost advantage vs. TSMC older nodes (Intel's 14nm vs. TSMC's 20 nm and Intel's 10nm vs. TSMC's 16nm). It is not clear that Intel is so far ahead. Intel 14nm had been delayed to the first quarter of 2014 and TSMC has committed to be in volume production in the later part of 2014. But the real competition is on the ability to bring fabless companies to volume using one's advanced process node. Key to this is the availability of libraries, EDA full tool set support, and major IP such as ARM processors. It is far from being clear that Intel is really far ahead of TSMC in this critical area. And then, these days it is not so clear that using a more advanced process node buys one an end-device cost advantage. In fact, the foundries have already made it clear that beyond the 28nm node they do not see cost reduction, due to the extra cost associated with advanced node lithography and other issues. Even Intel admitted at their latest analyst day that advanced nodes are associated with escalating depreciation and other costs, as illustrated by the following Intel chart - see the left most graph.

We should note that the Y axes of these graphs are logarithmic which indicate a significant increase of deprecation costs. However, Intel claims it will more than neutralize this increase of costs by accelerating the dimensional scaling when going to 14nm and 10nm, as is presented with the middle graph above. This would lead to an overall sustaining of the historical cost per transistor reduction as is illustrated by the rightmost graph above. Note: the asterisk (*) on those graphs indicates that numbers relating to 14nm and 10nm are forecasts only. Since Intel is committed to be in volume production at the 14nm node any day now, the number associated with 14nm should not be a forecast anymore and we hope to see them released soon.

The simple indication of technology node effective transistor density these days would be the bit cell size. As we have presented many times before, modern SoC device area is dominated by the embedded 6T SRAM. At IEDM 2013, TSMC made public their 6T SRAM bit cell area for 16nm: 0.07 sq. micron. We could not find any Intel public release for their 14nm 6T SRAM bit cell size. We did find an Intel chart for older nodes. This 6T bit cell size chart was presented at IDF2012:

Accordingly the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² = 0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm should be about 0.03 sq. micron or even smaller. As we don't have any official number we could wait until their early production devices of the 14nm node get analyzed or to the eventual release of their number. But short of an official number, we did find a 2013 presentation from the TRAMS project, of which Intel is a partner, as illustrated in the following charts:

It is now clear that EUV will not be available for the 14nm node, and accordingly the bit cell size from the chart above is 0.062 sq. micron. This is a bit better than that of TSMC but a far cry from 0.03 sq. micron.

If Intel does have a really good number, it would be reasonable to expect that they will make it public soon, to entice the high volume fabless companies such as Qualcomm and Apple to explore Intel’s foundry option.


As for the Jefferies analyst assertion "We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC", it is not clear if Intel’s R&D budget is truly larger. TSMC’s R&D budget is dedicated to the foundry side of the business while Qualcomm, Apple, ARM and many other fabless vendors R&D budgets support the design part of any new product release. The total ecosystem behind TSMC and ARM is clearly not smaller than that of Intel. In this month’s SEMI ISS Conference, IC Insights provided very interesting numbers regarding the record of 2013 as was reported in a blog titled:Is Intel the Concorde of Semiconductor Companies?


Top 10 CAPEX Spenders in 2013:

1. Samsung $12B
   
2. TSMC $11.2B
   
3. Intel $10.5B
   
4. GF $5.5B
   
5. SK Hynix $3.7B
   
6. Micron $3B
   
7. Toshiba $2.9B
   
8. UMC $1.5B
   
9. Infineon $880M
   
10. ASE (OSAT) $770M
    

Yes, Samsung and TSMC both outspent Intel. Just wait until you see the capacity numbers and you will know why.

Top 10 IC Wafer Capacity Leaders in 2013:

1. Samsung 12.6%
   
2. TSMC 10%
   
3. Micron 9.3%
   
4. Toshiba 8%
   
5. SK Hynix 7%
   
6. Intel 6.5%
   
7. ST 3.5%
   
8. UMC 3.5%
   
9. GF 3.3%
   
10. TI 3.0%
    

Clearly Intel is not larger than TSMC as a foundry and it is not clear why would it have a sustainable per transistor cost advantage.

Cost is important but it is far from being the only parameter when choosing a foundry partner. Selecting a foundry partner is truly selecting a partner. The design of leading edge devices is a very costly and lengthy effort, and has a pivotal effect on the business success for the fabless customer. TSMC had built trustful relationships for many years with its fabless customers. It is not clear how easy it is going to be for Intel to become a trustful foundry partner. So far it seems that Intel is still a proud IDM that insists that its customer will support its branding like the "Intel Inside" campaign or the recent announcement of Branding the cloud: Intel puts its stamp on cloud services across the globe. Intel’s repeating emphasis of their transistor cost advantage vs. that of TSMC suggests that Intel considers TSMC as their main competition for the mobile and tablet business. But then their consistent offering of SoC products for the space, as illustrated by the recent Intel chart below, and the Jefferies' cost analysis above, suggests that Intel is actually an IDM competing with the likes of Qualcomm in this space. It may create concerns in the minds of potential fables customers.

And as a final note, we don't know how much better the Intel process at 14nm and 10nm is vs. that of TSMC. We do know that when we ask someone for directions, if he says ‘make a right turn’ but with his hand he is pointing left, we should go ahead and turn left. So along with all of these confusing statements we learned just this week that Intel Cancels Fab 42, which was supposed to be the most advanced large capacity fab effort of Intel. I wonder if it should be considered as the hand pointing....

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about IEDM 2013. 

Let’s start with the short answer - because:

A. SOI is cheaper to fabricate than FinFet with comparable performance, and it is easier and cheaper to build FinFet on SOI which then provides better performance.

B. SOI is the natural technology for monolithic 3D IC for all overlaying transistor layers, and monolithic 3D is the most effective path to keep Moore's Law

C. SOI, or better 'XOI', is the most efficient path for most of the new concepts such as alternate materials for transistor construction and other structures like nano-wires.

Let’s now elaborate and discuss each of these points.

Starting with A: The following chart from Globalfoundries was presented on June 2013 at the FD-SOI Workshop, Kyoto, Japan. The chart illustrates that the best cost per transistor is the classic polysilcon gate at the 28nm node, that FD-SOI is cheaper than bulk with comparable performance at 28nm HKMG, and that FD-SOI at 20nm is cheaper than 14nm FinFet at the same performance level.

Similar information was presented by IBS (International Business Strategies), in Oct 2013 at the SOI Summit Shanghai, China.

And before that D. Handel Jones of IBS in a 2012 White Paper presented the following table.

Clearly the SOI substrate costs much more than the bulk substrate ($500 vs. $120), but the improvement in performance and the reduction of cost associated with FD processing neutralizes the substrate costs and makes the SOI route far more attractive. The following charts were included in a Comparison Study of FinFET on SOI vs. Bulk done by IBM, IMEC, SOITEC and Freescale:

For the second point "B, SOI is the natural technology for monolithic 3D", in monolithic 3D the upper semiconductor layer is very thin (<100nm) and is placed over oxide to isolate it from the interconnection structure underneath - hence SOI.

In this month’s IEDM 2013 two papers (9.3, 29.6) presented exciting demonstrations of monolithic 3D IC. It is interesting to note that Prof. Emeritus Chenming Hu of Berkeley (past TSMC CTO) who is now very famous due to his pioneering work on FinFets, is a co-author of these two pioneering works on monolithic 3D IC. The following figures illustrate the natural SOI structure of the upper transistor layers: 

In his invited paper at IEDM 2013 Geoffrey Yeap, VP of Technology at Qualcomm, articulates why monolithic 3D is most effective path for the semiconductor future: " Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law." As illustrated by his Fig. 17 below.

Clearly dimensional scaling is not providing transistor cost reduction beyond the 28 nm node, and the large fabless companies--Qualcomm, Broadcom, Nvidia, and AMD—recently reported this fact once again. The industry is trying to accommodate this new reality, while still rushing to develop and adopt more advanced nodes at escalating costs and complexity. And it is encouraging to see that Qualcomm are actually 'putting their money where their mouth is" as CEA Leti just recently announced an agreement with Qualcomm to Evaluate Leti’s Non-TSV 3D Process. Thus it was natural for Leti to include in their presentation at their promotional event in conjunction with this year’s IEDM 2013, slides advocating monolithic 3D as an alternative to dimensional scaling.

Leti’s presentation goes even further. One can see that in the following Leti slide, monolithic 3D is positioned as a far better path to keep the industry momentum and provides the cost reduction that dimensional scaling does not provide any more. Monolithic 3D also does this with far less costly fab infrastructure and process R&D. As the slide sums up: "1 node gain without scaling," or, as others may say, the new form of scaling is ‘scaling up’. 

In respect to point C regarding integration of other materials, we must admit that this is still area of advanced research and contains many unknowns. What we do know is that the silicon related worldwide infrastructure is unparalleled and will not be easily replaced. Accordingly, future technologies would have the best chance by first integrating with the existing silicon infrastructure, which in many cases is easier to do with SOI. To illustrate this we can refer to some other work presented in the IEDM 2013. Such as Stanford work (19.7) titled: "Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits" illustrated in the following chart:

Other work is about integrating photonics with CMOS which was covered in a recent article titled Is There Light At The End Of Moore’s Tunnel? and includes the following illustrations:

Clearly SOI and monolithic 3D integration have a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This new unified conference will help us to improve efficiency and establish this conference as a world class international venue to present and learn about the most up-to-date trends in CMOS and post-CMOS Scaling. The conference will provide both educational and cutting edge research in SOI and monolithic 3D and other supporting domains. These technologies were not part of the main stream semiconductor past; accordingly it is a golden opportunity to catch-up with these technologies now. Please mark your calendar for this opportunity to contribute and learn about SOI and monolithic 3D technology, as these technologies are well positioned to keep the semiconductor industry's future momentum.