At the Future of Memory and Storage Summit in Santa Clara this week, Samsung delivered a keynote [archived copy] titled “Driving the Wave of AI Revolution: 3D Innovations in Memory & Storage Architecture.” The title is worth pausing on. The organizing idea of the largest memory roadmap in the industry is now three-dimensional integration.

The headline announcement was V10 BV-NAND [archived copy], where BV stands for Bonding V-NAND. Samsung describes it as an industry first: a NAND architecture enabled by a new wafer bonding technology, with more than 400 layers and roughly 58 percent higher density than the previous generation. Thirteen years after Samsung introduced V-NAND at the 2013 Flash Memory Summit, the company has named its next NAND generation after the bonding step that makes it possible. Bonded two-wafer construction in NAND is no longer one vendor’s approach. It is the architecture, and it is now in the product name.

Samsung also previewed zHBM, which stacks HBM directly above the AI accelerator rather than beside it, in order to minimize the distance data travels between processor and memory. Samsung projects roughly eight times the performance of HBM5, and states that with next-generation wafer bonding it can reach more than ten times the memory density, three times the energy efficiency, and less than half the thermal resistance. Two details deserve attention. The density gain is attributed to wafer bonding rather than to more through-silicon vias. And zHBM contemplates customer-specific IP placed in the interlayer between the memory and the accelerator, which makes the bonding interface itself a place where logic lives.

Readers of this blog will recognize the destination. Our 2017 IEEE S3S paper, “A 1,000x Improvement in Computer Systems by Bridging the Processor-Memory Gap,” taught that the largest remaining gains in computing were not in the transistor but in the distance between compute and memory, and that placing memory directly on logic was how to collect them. Alibaba demonstrated the numbers at ISSCC 2022 with hybrid-bonded logic-to-DRAM. Qualcomm’s June 2026 High Bandwidth Compute announcement moved the idea onto a compute vendor’s datacenter roadmap. Samsung has now placed it on the roadmap of the world’s largest memory maker, with wafer bonding named as the enabler.

The pattern documented across our Record of Invention holds: publication, skepticism, third-party demonstration, industry adoption. What is different this time is the vocabulary. Wafer bonding and vertical integration are no longer described as alternatives to scaling. They are the roadmap, and one of them is now a product name.

In June 2014 this blog reported, under the title "Qualcomm Calls for Monolithic 3D IC," that Qualcomm had declared scaling down was no longer cost-economic and that it was looking at true monolithic 3D. That was twelve years ago.

At its Investor Day on June 24, 2026, Qualcomm went from looking to building. The company announced High Bandwidth Compute (HBC): a purpose-built compute die placed directly beneath an LPDDR memory stack, as the foundation of its datacenter roadmap. Qualcomm states that HBC delivers six times the bandwidth per watt of HBM and over 200 times the capacity of on-chip SRAM, with the first generation arriving on the AI250 accelerator in mid-2027. As Qualcomm's datacenter chief put it, "the congestion associated with HBM is gone."

A step forward, then, but in fairness only half a step. Qualcomm chose to connect its memory stack with pins rather than use hybrid bonding, and chose not to aggressively thin the memory wafers but rather use through-silicon vias. That is the costly path: TSVs consume silicon area, their practical pitch is orders of magnitude coarser than a bonded interface, and thick memory dies keep the via aspect ratios, and the costs, high. The full step, which we published and which Alibaba demonstrated at ISSCC 2022 with hybrid-bonded logic-to-DRAM, is hybrid bonding with extreme wafer thinning: sub-micron vertical pitch, millions of connections per square millimeter, and lower cost. HBC's architecture is right; its interconnect is a generation behind its own ambition. We expect the roadmap to catch up.

Readers of this blog have seen this architecture before. Our 2017 IEEE S3S paper, "A 1,000x Improvement in Computer Systems by Bridging the Processor-Memory Gap," taught exactly this: put the memory directly on the compute, remove the interconnect bottleneck, and the system-level gains dwarf anything remaining in dimensional scaling. Now a top-tier compute vendor has made memory-on-logic its flagship datacenter architecture, even if, so far, with only half of the toolkit.
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The pattern is the one documented across our Record of Invention: publication, skepticism, third-party demonstration, industry adoption. The processor-memory gap was always the industry's largest untapped opportunity. It is being tapped now, one roadmap at a time.

A newly published Japanese-language IP landscape report on Kioxia identifies MonolithIC 3D’s two pending U.S. International Trade Commission investigations as an emerging intellectual-property risk affecting Kioxia’s core 3D NAND business.

​The report, titled “Comprehensive Analysis of Kioxia Holdings—An IP Landscape of Patents, Technology and Business,” was published by Yorozu IP Strategy Consulting on July 14, 2026. It examines Kioxia’s financial position, 3D NAND and CMOS-bonded-array technology, patent portfolio, next-generation memory research and litigation exposure. (yorozuipsc.com)

While much of the report evaluates Kioxia’s technology and business strategy, it specifically highlights the two MonolithIC 3D Section 337 investigations. In the report’s executive summary, the author writes, as translated from Japanese:

“An intellectual-property risk has become apparent.”

The report identifies MonolithIC 3D as a U.S. patent owner and licensing company focused on 3D integration technology. It discusses the first investigation, Investigation No. 337-TA-1492, instituted by the USITC on March 26, 2026, against Kioxia and SK hynix entities. That investigation concerns certain NAND and DRAM memory chips and asserts seven U.S. patents. Its current target date is August 30, 2027. (usitc.gov)

The report also discusses MonolithIC 3D’s second complaint, based on five additional patents. The USITC instituted that proceeding as Investigation No. 337-TA-1506 on June 10, 2026. The second investigation covers certain NAND and DRAM memory chips and products containing those chips, and again names Kioxia and SK hynix entities as respondents. (usitc.gov)
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In both investigations, MonolithIC 3D is seeking limited exclusion orders and cease-and-desist orders. Such remedies could restrict the importation or U.S. sale of products found to infringe the asserted patents. As the USITC correctly notes, institution begins the investigation and does not constitute a decision on infringement, patent validity or the ultimate merits. (usitc.gov)

The report is noteworthy because it does not treat the MonolithIC 3D proceedings as an isolated litigation footnote. Instead, it places them directly within its assessment of Kioxia’s strategic patent position in 3D NAND, CBA and wafer-bonding technologies.

In its medium-term recommendations, the report advises Kioxia to examine the patent landscape surrounding CBA and wafer bonding and to compare its position with that of other major memory manufacturers. It then recommends that Kioxia:

“Monitor the progress of MonolithIC 3D’s first and second ITC investigations.”

The report further recommends evaluating the validity of the asserted 3D-integration patents and whether design-around measures may be required.

This is significant because CBA and related bonding technologies are becoming increasingly important to Kioxia’s future 3D NAND generations. By separating the memory array and peripheral-control circuits onto different wafers and then bonding them together, manufacturers can optimize the two structures separately and improve density, performance and manufacturing flexibility.
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The report therefore recognizes that patents covering 3D integration, bonding, vertical interconnects and related device structures may have strategic importance to Kioxia’s principal product roadmap.

The report also identifies events that could change its assessment of Kioxia. One such event would be substantive progress at the ITC toward a finding of a Section 337 violation or an exclusion order.

At that stage, the report states that Kioxia should:

“Reassess the intellectual-property risk.”

This represents an independent Japanese IP-strategy analysis acknowledging that the MonolithIC 3D proceedings could become commercially important as the investigations advance.

MonolithIC 3D has invested many years in developing and patenting technologies for three-dimensional semiconductor integration. The two pending USITC investigations are part of the company’s continuing effort to protect those inventions and obtain fair recognition for their use in commercial memory products.

The publisher notes that the report was generated with AI using publicly available information and may contain inaccuracies. That qualification should be kept in mind. Nevertheless, the report provides an interesting outside perspective on the growing importance of MonolithIC 3D’s patent portfolio and USITC proceedings within the global memory industry. (yorozuipsc.com)

We are proud to announce that our paper, “Design of Highly Stackable Charge Trap-Based 3D DRAM,” was recognized with the Best Paper Award at IEEE TENCON 2025. This recognition highlights research focused on addressing important challenges in future memory technologies and advancing the development of highly scalable memory architectures.
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As conventional DRAM technologies approach scaling limitations, challenges such as RC delay, reliability constraints, power consumption, and integration complexity continue to become increasingly significant. Existing approaches to next-generation 3D DRAM often face difficulties in stacking large numbers of memory layers due to complex memory cell structures. To address these limitations, our work proposes a novel charge trap-based 3D DRAM (CT 3D DRAM) architecture designed for highly scalable three-dimensional integration.

The proposed architecture utilizes a simplified one-transistor (1T) memory cell with a poly-Si channel and Schottky barrier source/drain contacts formed by metal silicide. Through this design approach, the structure aims to reduce complexity while improving scalability, power efficiency, and thermal management for future memory systems.

To validate the proposed concept, the study combined device design through simulation with experimental fabrication and characterization of planar CT DRAM devices. The results demonstrated promising memory operation characteristics, including reliable program and erase behavior, retention performance, and strong endurance characteristics.

The proposed CT 3D DRAM architecture also offers advantages in power consumption and heat dissipation. By utilizing metal source/drain structures and optimized bit-line and word-line configurations, the design demonstrates the potential for highly stacked memory architectures while maintaining efficient device operation. This work identifies CT 3D DRAM as a promising candidate for future high-density memory applications and emerging memory platforms such as CXL memory.

Download link of the Paper

"Welcome to another episode of "Beyond the Clouds: Edge-to-edge Transformation." Today, we have the privilege of speaking with Zvi Or-Bach, founder and CEO of MonolithIC 3D. Zvi's journey in the semiconductor industry is a fascinating tale of innovation, risk-taking, and relentless pursuit of technological advancement.

Zvi Or-Bach's roots trace back to Israel, where his early academic pursuits at Technion laid a strong foundation for his future endeavors. After completing his bachelor's degree in engineering, he served as a technical officer in the Israeli army. This unique blend of military discipline and academic excellence continued at the Weizmann Institute, where he earned a master's degree in Computer Science. It was during this period that Zvi's work on real-time video imaging caught the attention of Honeywell, leading to his first foray into the American tech landscape.

At Honeywell, Zvi immersed himself in the vibrant startup culture of the 128 Corridor, the second hub of innovation after Silicon Valley. His entrepreneurial spirit was further ignited when he returned to Israel as a chief engineer at Elbit Computers. This role not only bolstered his credentials but also set the stage for his first major entrepreneurial venture—Cubic Space Chips.

Chip Express marked Zvi's transition from a promising engineer to a visionary entrepreneur. The company initially aimed to sell laser micro-machining devices but pivoted to providing rapid prototyping services, a move that resonated with the burgeoning tech scene in Silicon Valley. Their innovative approach quickly attracted major clients, including Apple, and established Chip Express as a significant player in the industry.

Zvi's next venture, eASIC, came during the dot-com boom. Despite the initial challenges and the eventual sale to Intel, eASIC was instrumental in pioneering Structured ASIC technology, demonstrating Zvi's ability to stay ahead of industry trends. His resilience during the dot-com bust, funding operations out of his own pocket, showcased his unwavering commitment to innovation.

MonolithIC 3D, Zvi's current endeavor, epitomizes his vision for the future of semiconductors. Recognizing the limitations of traditional 2D scaling, Zvi has championed the shift towards 3D integration. His company's breakthroughs in hybrid bonding technology promise to revolutionize the industry by enabling higher performance and lower costs. Despite the initial skepticism, Zvi's persistence has paid off, with major industry players like AMD and Micron now adopting hybrid bonding.

Throughout his career, Zvi has been driven by a fearless attitude towards risk. His belief in the importance of innovation over complacency has been a guiding principle, one that he advises aspiring entrepreneurs to embrace. The path to success, according to Zvi, is fraught with challenges, but the potential rewards make the journey worthwhile.

​In addition to his professional achievements, Zvi's contributions extend to mentoring and supporting other startups. His role as chairman of Zeno Semiconductors and his ongoing efforts to develop new innovations reflect his dedication to nurturing the next generation of tech leaders."

In the dynamic field of semiconductor technology, the ongoing discourse surrounding Moore's Law has experienced a notable evolution, prominently featuring Zvi Or-Bach's (MonolithIC 3D’ CEO) 2014 assertion. His statement that transistor cost scaling reached a pivotal juncture at 28 nm has attracted significant attention. The statement was recently validated by Milind Shah from Google in the Short Course (SC1.6 ) at IEDM 2023. The unequivocal statement, "Transistor cost scaling (0.7X) stalled at 28 nm and remains flat gen over gen”, confirms what was initially foreseen in earlier public viewpoints and blogs in 2014 predicting the conclusion of Moore's Law.

​Source: Google, IEDM23 S.C1.6

​Despite the stalling of cost scaling, why is the industry still pushing for ever-smaller transistors, aiming for a mind-boggling 1 nm node? The answer lies in system-level benefits. As illustrated by this chart from Bill Dally, Chief Scientist at NVIDIA

Source: Bill Dally, Berkeley EECS, Nov 30, 2022.

This, in turn, drives the trend of leading computing devices like CPUs and GPUs reaching reticle size and beyond. The pursuit of ever-smaller nodes allows for even tighter integration of components on the chip, further boosting performance and efficiency.

Source: AMD

Unfortunately, logic and memory (DRAM, NAND) fabrication processes is very different. Accordingly, they are produced on different wafers and cannot be integrated by scaling. And making it even worse SRAM bit-cell scaling had stopped at the 5 nm node. 

Source: WikiChip

It seems that both AMD and TSMC  understood these trends and during the last couple of years adapted Hybrid Bonding technology to enable future progress in computing performance.

Source: TSMC 

Source: Dr. Lisa Su AMD ISSCC 2023 Tighter Integration Of Compute And Memor

​While current implementations like AMD's 3D V-Cache represent a stepping stone towards the full potential of 3D integration, significant hurdles remain. These include a fundamental shift in architectural thinking, moving from traditional edge interconnect to a novel 3D integration approach. Furthermore, achieving widespread adoption will require innovations in system-level redundancy, wafer-scale integration, and even on-chip RF networks. For a glimpse into this ambitious vision, look no further than Chapter 15* of the NANO-CHIPS 2030 book, aptly titled "A 1000× Improvement of the Processor-Memory Gap."(*Download the chapter here)

Zvi did reference Intel claims in his 2014 article in EE Times https://www.eetimes.com/intel-vs-intel/

Zvi Or Bach's 2016 Technical Assertion
Building upon his 2014 insights, Zvi Or Bach delved deeper in 2016, presenting a technical analysis that underlined the stagnation of transistor cost scaling at 28 nm. His meticulous examination considered factors such as escalating lithography cost, and transistor complexity (HKMG, FinFET), resulting in escalating wafer costs, ultimately asserting that this node marked the conclusion of Moore's Law in terms of cost scaling.

The latest technical discussions at IEDM 2023, facilitated by Google SC1.6's Short Course, have substantiated Zvi Or Bach's assertion from 2014. The technical validation affirming "Transistor cost scaling (0.7X) stalled at 28 nm and remains flat gen over gen " stands as a pivotal. This empirical confirmation not only solidifies the ongoing debate with tangible data but also fortifies the technical credibility of Zvi's initial forecast.

YMTC introduced the use of hybrid bonding for 3D NAND a few years ago, and now Kioxia/WD, one of the main 3D NAND vendors, is also releasing a 218 (BiCS8) 3D NAND product to volume production that utilizes hybrid bonding. This indicates the coming trend in NAND devices, termed "CMOS Directly Bonded to Array" (CBA).

For DRAM, it has been announced that the high-bandwidth memory (HBM) product, HBM4, will be introduced in 2025 utilizing hybrid bonding. Additionally, all DRAM vendors are actively pursuing 3D DRAM development using hybrid bonding. Samsung has disclosed an alternative for DRAM using 4F2 Cell and Hybrid Bonding, which will be presented at this year's IEDM and may be introduced to the market soon.

Early use of hybrid bonding in logic products took place in 2023 with AMD's 3D Cache technology. In 2024, Intel is scheduled to release its A20 process using Back Side Power Delivery (BSPD), also called PowerVia, which also uses bonding and extreme thinning technology. Extreme thinning overcomes one of the handicaps of 3D technologies, through-silicon vias (TSVs), using nano-TSVs, which are essentially simple via processes. As major foundries embrace extreme thinning, it is expected that many new applications of 3D heterogeneous integration using hybrid bonding will emerge soon after.

AI computing could become the next-generation technology driver in 2024. As previously reported, China may win in AI computing by using hybrid bonding to enable DRAM over processor to bridge the "memory wall" through an an approach called near memory computing. While the current actors are not the first-tier vendors, this is expected to change due to the insatiable appetite for computing power by Large Language Model (LLM) vendors. According to OpenAI's calculations, the amount of computing used in global AI training has grown exponentially since 2012, doubling every 3.43 months on average. Currently, the amount of computing has expanded 300,000 times, far exceeding the growth rate of computing power. One indication of this emerging trend is the press release issued this week by UMC, titled "UMC Launches W2W 3D IC Project with Partners, Targeting Growth in Edge AI."

Conclusion

Hybrid bonding is becoming a key technology driving the next generation of semiconductor devices. 2024 is likely to be the pivotal point for hybrid bonding adoption across all major semiconductor segments, including logic, DRAM, and NAND. Additionally, hybrid bonding is expected to play a major role in the development of next-generation AI computing solutions.

Shortly after ISSCC 2022, we were intrigued by Alibaba's presentation of a paper titled "184QPS/W 64Mb/mm2 3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation. System." The paper claimed a remarkable improvement of over 1,000 times in AI computing. Promptly, we published a blog about this breakthrough titled “China May Win in AI Computing”. However, we could not find any indication of Alibaba's revolutionary technology being adopted in the English electronics media until we stumbled upon Techinsights' advertisements for the Jasminer device teardown. Subsequently, we conducted a follow-up study of Chinese electronics media using Google Translate and uncovered numerous other activities by Chinese semiconductor vendors. It is well-known that the US restrictions on state-of-the-art semiconductor equipment and computing chips have significantly impacted China's competitive position in the field of AI. Nevertheless, it seems that certain Chinese companies are now exploring alternative approaches, such as Hybrid Bonding, as evidenced by the coverage below.
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Let's start with a bit of a background. In a paper presented at the 2017 IEEE S3S conference, titled "A 1,000x Improvement in Computer Systems by Bridging the Processor-Memory Gap," we introduced the potential of using hybrid bonding to overcome the "Memory Wall." We further elaborated on this concept in a book chapter, titled "A 1000× Improvement of the Processor-Memory Gap," published in the book NANO-CHIPS 2030,published in 2020.
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On June 15, 2022, a Chinese article titled "Breakthrough Bypassing the EUV Lithography Machine to Realize the Independent Development of DRAM Chips" reported that Xinmeng Technology had announced the development of a 3D 4F² DRAM architecture based on its HITOC technology. The company claimed that this architecture could be used as an alternative to advanced commercial DRAM. According to the article, this development represents another major innovation breakthrough in the field of heterogeneous integration technology, following the release of SUNRISE, an all-in-one AI chip for storage and computing. The article also reported that Haowei Technology had successfully used Xinmeng's HITOC technology for the latest tape-out of the Cuckoo 2 chip, resulting in a large-capacity storage-computing integrated 3D architecture.
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Techinsights is currently promoting a report titled "China breaks through restrictions with advanced chiplet strategy: 3D-IC Breakthrough in Chinese Ethereum Miner." According to the report, Techinsights discovered a storage mining design in the Jasminer X4 Ethereum miner ASIC, which was developed by the China-based manufacturer Jasminer. The report states that this design is the industry's first-ever use of DBI hybrid bonding technology with DRAM. Techinsights highlights that the Jasminer X4 demonstrates how a Chinese company can combine mature technologies to creatively produce high-performance, cutting-edge applications even under trade restrictions. The report also reveals that the X4 features a sizable 32 mm × 21 mm logic die that employs the earlier XMC (Wuhan Xinxin Semiconductor Manufacturing Co.) planar 40/45 nm CMOS.
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​During the 2023 China IC Leaders Summit, Seehi founder Xu Dawen gave a speech entitled "DRAM Storage and Computing Chips: Leading the Revolution of AI Large-Scale Computing Power." The company has published the speech on its website, and we have selected some of the key statements from it.
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“From the trend of AI development and restricted hardware, it can be seen that the scale of AI models increase by more than one order of magnitude every 2-3 years, and the peak computing power of chips increases by an average of 3 times every two years, lagging behind the development of AI models . However, memory performance lags behind even more, with an average increase of 80% in memory capacity every two years, a 40% increase in bandwidth, and almost no change in latency.”
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“At present, it is known that a single model requires more than 2,600 servers, which costs about 340 million U.S. dollars when converted into funds, and consumes about 410,000 kWh of electricity per day.” “Different from the model with CNN as the main framework, GPT is characterized by intensive memory access and irregular data handling, and insufficient data multiplexing.”
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In his talk Xu referenced the work published by Alibaba at ISSCC2022 – “In 2022, Bodhidharma Academy and Tsinghua Unigroup stacked 25nm DRAM on 55nm logic chips to build neural network computing and matching acceleration in recommendation systems. The system bandwidth reaches 1.38TBps. Compared with the CPU version, the performance is 9 times faster, and the energy efficiency ratio exceeds 300 times.”
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During his speech, Xu Dawen presented a table that compared different alternatives to memory cache.

“Through 3D stacking technology, we can achieve the distance between the processor and DRAM to the micron level or even sub-micron level. In this case, the wiring is very short and the delay is relatively small. Through this technology, thousands or even hundreds of thousands of interconnection lines can be completed per square millimeter, achieving higher bandwidth. In addition, eliminating the PHY and shorter wiring will result in lower power consumption and better cost performance. The entire chip is composed of multiple tiles, and each tile is stacked by DRAM and logic. The DRAM part is mainly to provide high storage capacity and high transmission bandwidth, and the logic part is mainly to do high computing power and efficient interconnection. The NoC communicates between the tiles. This NoC is an in/through NoC design. It is interconnected with adjacent tiles on the same plane and communicates with the memory in the vertical direction.”
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Finally he referenced their device called SH9000 GPT “which is based on the customer's algorithm and is integrated around the architecture layer, circuit layer, and transistor layer across layers. This set of technologies has successfully achieved excellent cost and energy efficiency ratios on mining machine chips. The theoretical peak power consumption of the SH9000 chip design may be slightly lower than that of the A100 (Nvidia), and the actual RTOPS is expected to be twice that of the opponent, which can achieve a better energy efficiency ratio.”
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Considering that both logic and DRAM devices were manufactured in China using relatively "old" nodes and still perform competitively compared to TSMC’ state-of-the-art devices and systems, it should be a matter of concern for all of us. This is particularly true since improvements solely through node scaling are no longer as significant as they used to be. The following table, released by TSMC for their 2025 N2 node, illustrates this point.
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Undoubtedly, the US restrictions on state-of-the-art semiconductor equipment and computing chips have greatly impacted China's competitive position in the field of AI. However, it appears that some Chinese companies are now exploring alternative approaches, such as Hybrid Bonding and heterogeneous system integration. While this new path presents its own challenges, it offers unprecedented advantages. Delaying the adoption of this new approach could result in an insurmountable gap in the future. The following chart from Applied Materials illustrates this point clearly.
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