This year Semicon West had a clear undertone – the roadmap forward is 3D IC. Yes, we can and we will keep pushing dimensions down, which for a few applications would be attractive, but for most designs the path forward would be “More than Moore.” As Globalfoundries' CEO Jha recently voiced: “it's clear that More-than-Moore is now mainstream rather than niche. …Really it is leading-edge pure digital that is the niche. Instead the high-cost leading edge processes are really niche processes optimized for applications in data centers or for high computational loads, albeit niches with volumes of hundred of millions of units per year.” Similarly, EE Times editor Rick Merritt subtitled his Semicon West summary Roadmap being drawn for chip stacks. All this is nicely illustrated by the following slide presented by An Steegen of IMEC for their pre-Semicon Technology Forum:

Leti, the other major semiconductor R&D organization, has gone even further by dedicating its Semicon West day entirely to 3D technologies, as can be seen in the following invitation:
2015-LetiDay-SanFrancisco

GOING VERTICAL WITH LETI: Solutions to new applications using 3D technologies

•         Welcome - Leti's 3D integration for tomorrow's devices > M.N Semeria

•         CoolCubeTM: 3D sequential integration to maintain Moore's Law > O. Faynot

•         Photonics: why 3D integration is mandatory > H. Metras

•         Computing: 3D technology for better performance > S. Cheramy

•         Lighting: 3D integration for cost effectiveness > I. C Robin

•         Nanocharacterization for 3D > P. Bleuet

•         Conclusion - Silicon Impulse > M.N Semeria
  

For more information: didier.louis@cea.fr
Come and visit Leti on European Pavilion

A similar view was also presented by Intel. Quoting Jeff Groff from his summary of Intel’s Q2 call: “In summary, it seems that Intel is executing fairly well on the process technology side of the business considering the ever increasing difficulty of pushing forward with Moore's Law. We can expect exciting new structures and materials (just maybe not at 10nm) and an increasing importance of 3-D structures in both logic and memory fabrication.” This echoes our blog Intel Calls for 3D IC, and was recently voiced by Intel’s process guru Mark Bohr: “Bohr predicted that Moore's Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.” It is also illustrated by his slide from ISSCC earlier this year.

The two concerns regarding 3D IC stacking using TSV are (a) Cost, noted in the slide above “Poor for Low Cost”, and (b) Vertical connectivity, as voiced by Mark Bohr: “Intel’s Bohr agrees that 3D structures will become more important. He said the kind of through-silicon vias used for today’s chip stacks need to improve in their density by orders of magnitude.”

These limitations are the driver behind the efforts to develop monolithic 3D technology. Monolithic 3D would provide a very cost effective alternative to dimensional scaling with 10,000x higher than TSV vertical connectivity, as illustrated by the following two slides of CEA Leti.

Prof. Subhasish Mitra of Stanford assesses a 1,000x improvement in energy efficiency using monolithic 3D. His summary at a Semicon West keynote panel: “We have an opportunity for a thousand-fold increase in energy efficiency…from collaboration between dense computing and memory elements and dense 3-D integration of them.”

While stacking using TSV does not require any change to the transistor (‘front-line’) process flow, all monolithic 3D process flows until recently required a significantly new transistor formation flow. Since the transistor process is where the majority of the R&D budget and talent is being allocated, and carries with it fresh reliability concerns, the industry has been most hesitant with respect to monolithic 3D adoption. Yet in this recent industry gathering there is a sense that industry wide interest is building up for 3D technologies. The success of 3D NAND as the first monolithic 3D industry wide adoption could help this new interest build even faster.

There is room for even more excitement. A recent technology breakthrough, first presented in IEEE S3S 2014 conference (Precision Bonders - A Game Changer for Monolithic 3D) introduced a game changer in the ease of monolithic 3D adoption. Enhancement of this breakthrough will be presented in this year’s IEEE S3S 2015. This new monolithic 3D flow allows the use of the existing fab transistor process for the fabrication of monolithic 3D devices, offering a most attractive path for the industry future scaling technology.


P.S.

A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program, three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies, and many other authors will be talking about their work on monolithic 3DIC and its ecosystem.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. 
Vivek Singh, an Intel fellow, in his DAC 2015 keynote Moore's Law at 50: No End in Sight presented again the Intel chart below suggesting straight (log) line transistor cost reduction with dimensional scaling. In fact, his cost/transistor drop even seems to accelerate beyond the linear at 14 and 10 nanometers.

Vivek Singh, an Intel fellow, in his DAC 2015 keynote Moore's Law at 50: No End in Sight presented again the Intel chart below suggesting straight (log) line transistor cost reduction with dimensional scaling. In fact, his cost/transistor drop even seems to accelerate beyond the linear at 14 and 10 nanometers.

Less than a week later, Handel Jones (IBS) in his blog 10nm Chips Promise Lower Costs published an update down to 10nm of his well-known chart, presented below, of transistor cost with scaling.

Yes, 10 nm transistor cost is a bit less than that of the 16/14nm node, but still higher than that of the 28nm node and clearly showing that the historical cost reduction of 30% per node stopped at 28nm node. From that point on Handel Jones’ cost projections have been either flat or even a bit higher. Clearly, those charts are in a striking contradiction!

The IBS chart had been supported by the other foundries and their customers, as illustrated by quotes such as the following: “Samsung spent several years developing its 14nm technology and debating which process node it would invest in after 28nm. Low expects that 28nm will still be a popular process node for years to come because of its price…The cost per transistor has increased in 14nm FinFETs and will continue to do so, …”(http://www.eetimes.com/document.asp?doc_id=1326369), “Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase. .. Now, although we are still scaling down it’s not cost-economic anymore” Karim Arabi, Qualcomm VP of engineering, DAC 2014 Keynote

While the Intel chart Y axis has nominal values, we can plot Intel’s straight line cost reduction on the IBS chart as illustrated below on a half log scale:

Before jumping to our assessment of the cost difference between the green bars and Intel’s blue line, I’d like to direct you to a very detailed comment made by the “IJD” reader to Handle Jones’ blog. IJD suggests that Intel cost reduction could be explained by Intel’s very high starting point “since they effectively have a monopoly in one of the highest-margin highest volume chip markets which is x86 CPUs.”
Intel has repeatedly used their chart in effort to promote their foundry business in competition with TSMC and in the process won the Altera business. Consequently, it seems important that we should compare Intel’s  costs as illustrated by the blue line vs. the green bars as reported by the rest of the industry.

We should consider the following points:

1.     The Intel chart, while illustrating a simple formula, does seem logically faulty. The exponentially escalating cost of wafers needs to be neutralized by exponentially escalating scaling beyond the historical 0.7x scaling. Yet the major driver of wafer cost is lithography and it seems illogical to further reduce wafer cost by doing even more of it. Specifically, the escalating wafer cost below 28nm is driven by the need of double patterning and processing of few critical layers.  Intel approach means that more layers would become critical and would need double patterning, driving the cost even higher.

2.     A $0.42 per transistor vs. $1.31 per transistor should have won Intel far more foundry business, yet their major win was a very high margin vendor – Altera, and the rumor was that Altera was planning to go back to TSMC for the 10nm node. Foundry business is extremely competitive, as the customer owns the product IP and can choose the lowest cost foundry in order to win the extremely competitive end-market such as the smart phone market.

3.     Intel’s $0.42 per transistor vs. the industry’s $1.31, combined with Intel’s command of the 86x CPU architecture, should have won Intel far more success in the Tablet market.

4.     Looking at the last 6 months of Intel stock chart (below) in comparison to TSMC, Qualcomm and Nvidia does not show any market forecast for Intel future business resulting from its ability to beat its competitors by more than 3x the manufacturing cost.

While Intel had consistently been the process technology leader, there is no special know-how or other unique advantage that could allow Intel to have 3x better costs than its competitors.

All we can do now is watch the market evolve and eventually tell us how the gap between these widely different cost estimates will be bridged.

In any event, it is clear that Intel’s solution to the escalating cost of lithography is not sustainable. Over-scaling interconnect on its own, as Intel has sometimes hinted at, is extremely problematic because interconnect RC delays are increasing exponentially with scaling. This is nicely illustrated in the Applied Materials chart below.

Source: B. Wu, A. Kumar, Applied Materials

The only visible solution for the coming decade is monolithic 3D. Quoting Geoffrey Yeap, VP of Technology at Qualcomm, at his invited paper at IEDM 2013: “Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.” And even Intel’s process guru Mark Bohr seems to have come around: “Bohr predicted that Moore's Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.” (http://www.v3.co.uk/v3-uk/news/2403113/intel-predicts-moores-law-to-last-another-10-years)

P.S.

A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program, three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies, and many other authors will be talking about their work on monolithic 3DIC and its ecosystem.

In his famous 1965 paper Cramming more components onto integrated circuits, Moore wrote: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year”. Dimensional scaling below 28nm will only increase the ‘component cost’ as described in 28nm – The Last Node of Moore's Law. While there is still a strong effort behind dimensional scaling to 14, 10 and 7nm – and possibly even beyond, a new scaling effort is emerging attempting to reduce the ‘component costs’ and increase integration by the other factors presented by Moore in his 1975 famous IEDM paper “Progress in digital integrated electronics.”. In the 1975 paper Moore updated the time scaling rate to every two years and suggested the following factors–see the following figure taken from his paper—helping to drive scaling forward:


1.     “Die size”—“larger chip area” 
2.     “Dimension”—“higher density” and “finer geometries” 
3.     “Device and circuit cleverness”

A fourth factor should have been added to the list above – improvement in manufacturing efficiency, which ensued from the increase in wafer sizes from 4” to 5” and all the way to the 12” of today.

In the past, all of these factors were aggregated into dimensional scaling as old fabs got obsolete and improvements predominantly were implemented in the new emerging node. Nowadays, as dimensional scaling has reached its diminishing returns phase, we can see a very diverse adaption of technology improvments.

In his keynote presentation at the 2014 Synopsys user group meeting, Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys’ newer tools to improve older node design effectiveness. The following is one of them

The following slide was taken from AMD’s President & CEO Dr. Lisa Su presentation in 2015 Semicon China, illustrating AMD’s improvements within the same 28nm technology node:

Even more significant would be the adoption of a breakthrough technology. A good example is the SRAM technology developed by Zeno Semiconductor, which has recently been validated on 28nm process. This new SRAM technology replaces the 6T SRAM bit cell with 1T SRAM (true SRAM - no refresh is needed) providing significant reduction of ‘component costs’ as is illustrated in the following two slides.

This new industry trend was nicely articulated by Kelvin Low of Samsung covered in “Samsung Describes Road to 14nm, FinFETs a challenge, FD-SOI an alternative.” Quoting: “Samsung spent several years developing its 14nm technology and debating which process node it would invest in after 28nm. Low expects that 28nm will still be a popular process node for years to come because of its price …The cost per transistor has increased in 14nm FinFETs and will continue to do so, Low said, so an alternative technology such as 28nm SOI is necessary.” Earlier, in the SOI Forum in its presentation “28FD-SOI: Cost effective low power solution for long lived 28nm” Samsung presented the following slide: 

“Device and circuit cleverness” as a factor would never stop but it is made of a series of individual improvements that will not be enough to sustain a long-term scaling path for the industry. An alternative long-term path will be “Die size” – “larger chip area,” which is effectively monolithic 3D, and manufacturing efficiency, which will have an important role in monolithic 3D. And who is better to call it than Mark Bohr of Intel? In a recent blog piece “Intel predicts Moore's Law to last another 10 years” Bohr is quoted predicting “that Moore's Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”   This new dimension for Moore’s Law is also illustrated in the following AMD’s Dr. Su slide:

And this is also visible in the marketplace by the industry-wide adoption of 3D NAND devices that Samsung started to mass-produce in 2014, and followed with a second generation 32 layer-stack device this year, as illustrated in their slide:

In the recent webcast “Monolithic 3D: The Most Effective Path for Future IC Scaling,” Dr. Maud Vinet of CEA Leti presented their “CoolCube” monolithic 3D technology, which was followed by our own, i.e., MonolithIC 3D, presentation. An important breakthrough presented by us was a monolithic 3D process flow that does not require changes in transistor-formation process and could be easily integrated by any fab at any process node.

Finally, I’d like to quote Mark Bohr again as we reported in our blog “Intel Calls for 3D IC”: “heterogeneous integration enabled by 3D IC is an increasingly important part of scaling". This is illustrated nicely by the following figure presented by Qualcomm in their ISPD ‘15 paper titled “3D VLSI: A Scalable Integration Beyond 2D”

In summary, the general promise of Moore’s Law is not going to end any time soon. Yet it is not going to be the simple brute-force x0.7 dimensional scaling that dominated the industry for the last 5 decades. Quoting Mark Bohr again, it “will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”

P.S.

A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. 
Starting as soon as 2016 Qualcomm is looking to leverage Monolithic 3D IC technology to win market share in the 8 billion smartphones that will be produced from 2014 to 2018 market, said Karim Arabi, vice president of engineering at Qualcomm, speaking at the International Symposium on Physical Design (ISPD-2015, Mar. 29-April 1). This was reported by the EE Times blog titled 3D Qualcomm SoC Testing on Horizon. Arabi’s presentation slides, along with the corresponding CEA Leti slides, are now available on the ISPD-2015 conference site.

Qualcomm’s long term focus on Monolithic 3D was reviewed in our EE Times blog Qualcomm Calls for Monolithic 3D. Qualcomm calls it now “3DV” and plans to use it for future scaling. See the following slide presented by Arabi.

Quoting: "Our 3D VLSI technology, which we call 3DV, enables die size to be shrunk in half, while simultaneously increasing yields,”...“The final advantage of 3DV chips,” according to Arabi, “is that you only need to use the most expensive and latest node technology on the bottom layer. For instance, the bottom layer housing the CPU, GPU and other high-speed devices can be fabricated at 10-to-14 nanometer, whereas the higher layers housing less critical functions can be fabricated at a less expensive relaxed node of, say, 28-nanometers.”
The following slide presented by Arabi illustrates their Monolithic 3D technology (“3DV”) process flow, which seem very similar to the CEA Leti CoolCube program co-sponsored by Qualcomm.

Arabi’s presentation also discussed the design tools available for Monolithic 3D. For the short term Qualcomm is planning to use conventional 2D EDA with scripts and an additional software program to design their Monolithic 3D devices as illustrated in the following two slides.

Arabi also discussed the Qualcomm work in respect to the thermal issues of such Monolithic 3D devices. The following summary slide provides the study’s conclusion: “3D temperatures are comparable or even better than 2D”.

CEA Leti, Qualcomm’s technology partner, presented their joint work with Mentor Graphics on Monolithic 3D EDA. The following slide illustrates how Monolithic 3D could improve the on-chip interconnect challenge and why other forms of 3D IC, such as TSV, do not.

The following slide of CEA Leti presents the Qualcomm motivation for Monolithic 3D.

Quoting from a Cadence blog titled: Moore’s Law 2.0—The End and Beginning of a New Era! – “At the sub-10nm level, electromigration, and process variations in manufacturing, amongst other effects, will be so large that the end of conventional silicon chip manufacturing at high yields and chip longevity might be reached. However, we have a way out of this predicament. The solution is to build up. If we cannot make it 2D anymore, let’s make it 3D. Think about Manhattan, in New York City. When 2D space gets tight you build up into 3D space. The same thing is occurring in semiconductor manufacturing.”

The memory industry is ramping up Monolithic 3D as we speak. 3D NAND has seen announcements from Intel, Micron and Toshiba joining Samsung. Now the logic industry is looking to adopt Monolithic 3D as we learn from this Qualcomm presentation at this ISPD-2015 and the Intel presentation at ISSCC-2015 discussed in our recent blog Intel Call’s for Monolithic 3D.



P.S.

A good conference to learn about this new scaling technology is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies.

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. 
Moore’s law has swept much of the modern world along with it. Some estimates ascribe up to 40 percent of the global productivity growth achieved during the last two decades to the expansion of information and communication technologies made possible by semiconductor performance and cost improvements... 

"Samsung and smartphones in general look to be in trouble and that's bad news for the electronics industry" wrote Rick Merritt in his Smartphone, Samsung in Trouble recent report from MWC15 in Barcelona. Rick clearly points to 14nm FinFET as the source of the problem and continues  "[i]f smartphone growth slows for lack of a driver, as tablet growth is already doing, the electronics industry could be in trouble ... it’s beginning to feel like another big bubble building up."

Few days later, the following chart supporting Rick’s impression was released in a new report from IHS. 

Source: IHS Quarterly Mobile Phone Display Shipment and Forecast Report

All this comes just as NASDAQ seems to finally be reaching back to the height of the Tech Bubble seen in the following chart:

About a year ago McKinsey published a report Moore’s law: Repeal or renewal? subtitled "Economic conditions could invalidate Moore’s law after decades as the semiconductor industry’s innovation touchstone. The impact on chipmakers and others could be dramatic." It goes on to say

As a result, Moore’s law has swept much of the modern world along with it. Some estimates ascribe up to 40 percent of the global productivity growth achieved during the last two decades to the expansion of information and communication technologies made possible by semiconductor performance and cost improvements... The law retains its predictive power because of constant improvements in production technology, which are driven by the industry’s “global semiconductor road maps.” These describe the progress required for the continuation of Moore’s law.

The report concludes with this: "We believe that interesting years lay ahead for the semiconductor industry because the steady evolution the industry historically counted on might be coming to an end."

And it does seem that this is ahead of us as we presented in our well-read blog 28nm: The Last Node of Moore's Law.

Since the publication of that blog more information has been released, mostly supporting the conclusion that 28 nm was the last node. This includes the following finding from a survey conducted by KPMG "Only a fourth of semiconductor business leaders believe Moore's Law will continue for the foreseeable future ... More than half said Moore’s Law will no longer apply at various nodes less than 22 nanometers, while 16 percent said it already has ended." Similarly,  Scott McGregor, President and CEO of Broadcom, spoke at SEMI Industry Strategy Symposium (ISS) in January (Exponentially Rising Costs Will Bring Changes) and indicated that the cost per transistor was rising after the 28nm, which he described as “one of the most significant challenges we as an industry have faced.” He provided the following slide in support:

"The reason for increasing transistor cost is the complexity of the devices, and the cost of the equipment required to produce them. … these costs are going up exponentially," he said.

The good news is that we now have an alternative, scaling up using monolithic 3D. As was presented in last year’s IEEE S3S-2014 conference and in our blog - Precision Bonders - A Game Changer for Monolithic 3D, monolithic 3D IC could be adopted by any current fab without the need for a new recipe for transistor formation, providing very competitive costs for a wide range of product enhancements and offers a long-term road map for the industry. 

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc.

At the recent ISSCC Intel presented the following slide. Quoting from Extremetech coverage: "At 10nm and below, the path forward will become increasingly murky. What Intel has proposed is essentially a shift towards other types of cost-saving technologies and process adoptions rather than relying on strict lithography improvement … Intel may be keeping its next-generation materials and lithography plans quiet, but the company does intend to push the envelope in other ways. 2.5D and 3D integration will be critical to the development of next-generation SoCs"

We clearly agree with Intel that the heterogeneous integration enabled by 3D IC is an "increasingly important part of scaling". This will become even more true as mobile and IoT markets increasingly will consume the lion share of the semiconductor business.

With respect to "Poor for Low Cost," this is only true for the TSV approach to 3D ICs. The following slide was presented in the recent 3D ASIP (2014) conference as the summary of "Will the Cost of 3D ICs Ever Be Low Enough for High Volume Products" presentation by Chest Palesko, a leading market researcher:

So, yes TSV-based 3D IC is "Poor for Low Cost".

But the other form of 3D IC, the Monolithic 3D, is the lowest cost path for future scaling!

Samsung’s 3D NAND is an early example of monolithic 3D enabled scaling, being driven primarily by the push to increase bit capacity while reducing the cost per bit. Monolithically scaling up is now part of the ITRS and is being adopted by all NAND vendors. Samsung was the first to bring 3D NAND to mass production using the monolithic 3D approach:

The next market segment adopting monolithic 3D scaling is the image sensors as recently reported by EE Times: CMOS Image Sensors Surpassing Moore's Law. Quoting: "imaging chips is downsizing the chip while simultaneously packing more pixels per unit size, thus one-upping processors and memory … The CMOS imaging industry may make the 3-D TSV obsolete – before the processor and memory industry has even widely adopted it – by perfecting a wafer bonding technique that allows the connection between layers to be made with copper-to-copper (Cu-to-Cu) interconnects nearly as small as regular vias."

While still in the R&D phase, there is momentum building for monolithic 3D in logic too, as reported by CEA Leti’s work in collaboration with ST Micro, IBM, and Qualcomm. This was presented in the S3S (2014), 3D ASIP (2014), and IEDM (2014) conferences. The following chart was presented by CEA Leti and shows the cost reduction and performance improvements enabled by monolithic 3D scaling:

A recent validation of the unreasonable costs associated with dimensional scaling beyond 28 nm could be calculated from a recent EE Times article TSMC to Start 10nm in 2017, Closing Gap with Intel. Quoting: "By the end of 2018, the company’s Taichung site will reach a monthly output capacity of 90,000 wafers at the 10nm and more advanced technology nodes, according to a report on the Chinatimes.com website. TSMC earlier this month said it would invest NT$500 billion ($15.9 billion) as part of an expansion at the Taichung site in central Taiwan." At two year’s depreciation, this represents $7,400 per wafer!!!

A misleading benefit which often gets attributed to dimensional scaling but has little to do with it, is the wide range of device improvements resulting from R&D efforts that typically coincide with the next scaling node. AMD’s recent presentation at ISSCC 2015 clearly illustrates this point by showing device improvements while still staying at the same 28 nm process node. As could be seen, major improvement in power, yield, and performance are possible over time without changing the technology node.

Monolithic 3D provides the industry many years of exponential integration growth while reducing cost and power by leveraging depreciation, learning curve, heterogeneous integration, low VT, SOI, shorter interconnections and many other powerful benefits of monolithic 3D, some of which are presented in our white paper The Monolithic 3D Advantage, monolithic 3D is far more than just an alternative to 0.7x scaling!!!

Until recently, the path to monolithic 3D required change to the front end-of-line process. An FEOL process change is always part of dimensional scaling, but is expensive, risky and in most cases done only by the leading edge companies. Now, as was presented in the recent IEEE S3S ‘14 conference, emerging precision bonders, such as from EVG or Nikon, enable a Game Changer for Monolithic 3D  - a "true monolithic 3D IC without the need for a new recipe for transistor formation. The process could be adopted by any current fab providing very competitive costs for a range of product enhancements and offers a long term road map for better offerings by scaling up."



P.S.

A good conference to learn about this new scaling technology is the IEEE S3S ‘15, in Sonoma, on October 5th thru 8th, 2015. Two leading researchers from Berkeley and Stanford Universities will give invited talks presenting their work on advanced monolithic 3D integration technologies.

"Dark Silicon" is that portion of the device that needs to be shut down to avoid overheating. In a recent IEDM 2014 short course by ARM's principal engineer Greg Yeric the dark silicon was projected to be "about one-third of total area in the 20nm technology node (including 16/14nm finFETs), increasing to as much as 80% by the 5nm node," as reported by a recent Darker Silicon blog. Unlike the time that dimensional scaling could follow Dennard’s Law, it is now getting harder to thin the gate dielectric without causing extreme rise in device leakage and "as a result, while feature sizes have continued to shrink, threshold voltage has not". The following chart is from a DAC ‘13 paper titled The EDA Challenges in the Dark Silicon Era:

This dark outlook seems even darker once the cost of this silicon is taken into account. At the last SEMI Industry Strategy Symposium (ISS), as reported  in a blog titled Exponentially Rising Costs Will Bring Changes Scott McGregor, President and CEO of Broadcom presented the following charts:

This paints a very dark future for the industry: we would need to invest exponentially more, to develop designs which use more expensive transistors, of which we would need to keep dark an increasing proportion. It seems that Broadcom's CEO conclusion is unavoidable - "major changes for the semiconductor industry moving forward".

Looking for the light at the end of the tunnel, we can quote ARM's CTO, Mike Muller in Cadence's blog titled ARM Keynote: Will ‘Dark Silicon’ Derail The Mobile Internet? : "So how to light things up? Muller started with three suggestions:

• Push forward on new silicon technologies such as silicon-on-insulator (SOI),
• Use energy-efficient, high-density memories to fill some of the "dark" space.
• Combine the best process technologies to fulfill various functions with 3D ICs, which will "become a critical part of how we deliver power-efficient solutions."

Indeed just this week it was reported in EE Times that Sony Joins FDSOI Club writing: "Sony was able to cut power consumption in its GNSS chip from 10mW to 1mW".

And at IEDM 2014 we could see multiple papers on monolithic 3D technologies and memories such as R-RAM being formed as part of the Back End Of Line on top of the logic, forming effectively monolithic 3D circuits. It should be pointed out that in the general case of monolithic 3D the upper transistor layers are naturally SOI so achieving even better power efficiency by combining the SOI reduction of transistor threshold while reducing the average interconnect length, further reduces interconnect power and delay. CEA Leti had a workshop presenting their momentum on monolithic 3D through collaboration with ST Micro and IBM and supported by Qualcomm titled CoolCube™, a powerful approach for further 3D VLSI scaling. The following chart from Leti presentation illustrates the monolithic 3D build up of world wide ecosystem:

And the monolithic 3D light gets even brighter. Until recently, the path to monolithic 3D required change to the front end-of-line process. An FEOL  process change is always part of dimensional scaling, but is expensive and in most cases done only by the leading edge companies. Now, as was presented in the recent IEEE S3S ‘14 conference,  the emerging precise bonders, such as from EVG or Nikon, enable a Game Changer for Monolithic 3D  - "true monolithic 3D IC without the need for a new recipe for transistor formation. The process could be adapted by any current fab providing very competitive costs for a range of product enhancements and offer a long term road map for better offerings by scaling up."
So while traditional dimensional scaling looks darker, the emerging monolithic 3D technology is poised to bring back the light.

PS 
A good conference to learn about these emerging technologies - SOI-3D-Subthreshold - is the IEEE S3S ‘15, inSonoma, on October 5th thru 8th, 2015. 

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr Or Bach presents the article published at the IEEE S3S 2014 Conference. Authors of article: Zvi Or-Bach, Brian Cronquist, Zeev Wurman, Israel Beinglass, and Albert Henning, MonolithIC 3D Inc., San Jose, CA 95124, USA.

For many years monolithic 3D was considered untenable due to the strict 400 ºC temperature limit imposed by the aluminum or copper interconnect. This led to the focus on TSV technology as the only viable path for 3D ICs. Unfortunately, it is now clear that the TSV flow in intrinsically expensive and accordingly being perpetually pushed to the future. In the recent years pioneering efforts were published providing practical paths for monolithic 3D logic devices [1-7]. But each and every one of those presented new transistor formation flows and comes along with some other non trivial process development challenges.

Recently a new wafer bonder has been introduced to the market by EVG [8]. While prior wafer bonders had about 1 micron alignment accuracy, the newly introduced Fusion Bonder has an alignment precision of 200nm (3σ). This paper proposes a process flow that leverages such precise bonder to provide a true monolithic 3D IC without the need for a new recipe for transistor formation. The process could be adapted by any current fab providing very competitive costs for a range of product enhancements and offer a long term road map for better offerings by scaling up.


Ion-Cut - A Layer Transfer Technology


The proposed flow utilizes a well-known process for single crystal thin layer transfer known as ion-cut technology. It involves hydrogen implantation, wafer bonding, and cleaving (Fig. 1). Ion-cut is a volume production qualified process that has been used for two decades in SOI wafer manufacturing. The technology was owned exclusively by Soitec for many years, which named it smart-cutÒ, but in late 2012 Soitec's fundamental patent expired and the technology is now widely available. Our estimates suggest that with re-use of substrates, ion-cut would cost less than $60 per transferred layer. 

Monolithic 3D IC


The following flow (Fig. 2) is built on what we call 'gate replacement' [9] and leverages the precision bonder alignment accuracy. Step 1 - a 'donor' wafer will be used to process a transistor layer labeled Stratum 3. The existing front end process could be used. Alternatively for a gate-last flow, the process will hold before the gate replacement phase. Then H+ would be implanted at the desired depth (~100nm) in preparation for the layer transfer step. Step 2 - the donor wafer is bonded (oxide to oxide) to a 'carrier wafer' and ion-cut off. This bonding step does not require precise alignment. Step 3 - the carrier wafer could be now annealed to repair the potential H+ implant damage. Step 4 - the donor wafer is now processed to form Stratum 2. The existing front line process could be used including FinFET or any other available front line process. The choice of the transistor and the architecture for Strata 2 and 3 should consider the need for vertical isolation in-between them. Note that between the transferred layer and the carrier wafer there is an oxide layer which would be an excellent etch stop allowing the transfer onto the target layer without the need for ion-cut. A preferred strategy is to use Stratum 2 for the high performance circuits while Stratum 3 would be used for support of less sensitive circuits. All high temperature should be completed at this point, as in the following step interconnects are added. Step 5 - add contacts and at least one metal layer. Step 6 - bond (oxide to oxide or metal to metal) to the target wafer using the precise bonder alignment with less than 200nm misalignment.  Now grind and etch off the carrier wafer. (Not presented here are options to remove the carrier wafer for reuse.) Step 7 - the dummy gate and the gate oxide of Stratum 3 can be now replaced, and connections could be made between Stratum 2, Stratum 3 and the underneath target wafer. Alignment and via processing are just as if between conventional BEOL metal layers, as the transferred layer is very thin (~100nm).

Smart Alignment


Having a thin transferred layer allows the through layer via to be as small as a conventional BEOL interconnection via (~50 nm). Yet the 200 nm bonding alignment window would appear to require a landing pad of 200 nm by 200nm for each vertical connection. With Smart Alignment the connection is made by two perpendicular 200 nm long strips as seen in Fig 3. The vertical strip is part of the top layer of the target (bottom) wafer. After bonding, the through layer via would be aligned to the target wafer in the X direction and to the transferred layer in the Y direction as seen in Fig 4. The top connection strip could be then processed aligned to the transferred (top) layer. This alignment scheme reduces the vertical connection overhead to minimum and allows for multiple vertical connections per unit area of 200 nm x 200 nm.

Strata 2, 3 - Examples


Fig. 5 illustrates one example for circuit allocation for Stratum 2 and Stratum 3 with an intrinsic vertical isolation. For Stratum 2, most advanced devices could be used such as FinFET transistors and forming high speed logic. The SRAM for the high speed logic circuit could be placed onto the close by Stratum 3. A compelling option for the SRAM would be the use of Zeno technology [10] where a two stable states one transistor SRAM are enabled by a deep implanted back-bias. The vertical isolation is achieved by the back-bias. The FinFET transistor by design is also isolated from the substrate. This use of Stratum 2 and Stratum 3 is compelling as there is no obstruction to the memory blockages and creates a very short path for memory access. Such dual functional layer (Stratum 2 + Stratum 3) could be a product by itself offered as an add-on to many designs and 1-chip systems.         Such flows with a dual functional layer could enable many new innovative devices such as:

* An image sensor on Stratum 3 with pixel electronics on Stratum 2 could provide an unparalleled dynamic range to cameras. 

* A full redundancy layer [11] as Stratum 3 provides redundancy to Stratum 2, allowing almost unlimited logic integration on huge dies, essentially a server farm on a device.

* A configurable logic fabric as an add-on...

Monolithic 3D Cost Estimates


It is well known that high cost is the number one issue which slows down the adoption of 3D ICs based on TSV. The proposed monolithic 3D flow has the potential to overcome these barriers as it avoids use of a thick layer with lengthy etch and deposition processes. In fact, it can provide circuit fabrics for two strata for a cost that is less than one wafer substrate. The donor wafer is reusable and the cost of the first ion-cut is estimated to be less than $60 [12]. The carrier wafer could be reusable or utilize an inexpensive test wafer costing about $30. The estimated per wafer cost of precision bonding is less than $20. Other steps involved in layer transfer, cleaning, etch, etc., are estimated at about $30 total. The costs for transistor formation for Strata 2 and 3 and their associated interconnects are no different than any other circuit fabrication costs. Accordingly we estimate that the cost structure is comparable with the fabrication cost of 2D devices. Yet having the overall design built in a 3 strata fabric provides huge power, performance, and cost benefits.


Heat Removal


A point of concern is always the heat removal aspect for 3D IC. The first question relates to having more transistors in a smaller space. While more complex circuits present an ever increasing power challenge, having it built in monolithic 3D is an important part of the solution as it is well documented [13] that 80% of the power consumption is due to on-chip connectivity. The more interesting question relates to the fact that Strata 2 and 3 transistors are thermally isolated (surrounded by oxide) and without direct access to the silicon bulk for heat removal. Fig. 6 illustrates the solution of using the power delivery network for heat removal. This work was reported in IEDM 2012 [14]. Having Stratum 2 only about 1 micron away from the bulk allows a very effective heat removal path through the power delivery network. Additional supporting techniques such as heat spreaders and thermally conducting but electrically isolated contacts could also be implemented [15].

Summary


Precision Bonders combined with innovative layer transfer and alignment techniques enable a simple path to 3D IC providing the best of all worlds:

•         Vertical connectivity density comparable with the horizontal one
•         Use of existing transistor and interconnect flows
•         Compatible with advanced and older fabs
•         Low cost competitive with 2D IC cost structure 
•         Heterogonous integration - Fab lines, process nodes, device materials, processes
•         Parallel and Sequential process (short TAT)
•         Enables many new classes of device and systems untenable with 2D IC
•          Multiple paths for cost reduction that were untenable with 2D IC
  

        It seems that the new form of 3D IC combines the best of TSV with monolithic 3D IC to offer the most attractive path to keep Moore's Law, while opening an unparalleled path for all fabs to keep enhancing their product range using their existing equipment and flows.

                And yes, this opens a new horizon for the semiconductor industry.

References

[1] Z. Or-Bach, IEEE 3DIC Conference, 2013. 
[2] P. Batude et al., Proceedings of the Electro-Chemical Society (ECS) spring meeting, Vol. 16, pp.47 (2008) 
[3] D. C. Sekar, IEEE 3DIC Conference, 2012. 
[4] B. Rajendran, IEEE 3DIC Conference, 2013. 
[5] Chih-Chao Yang 29.6 IEDM 2013 
[6] Chang-Hong Shen pp. 262 IEDM 2013 
[7] Sang-Yun Lee, US Patent 7,470,142 
[8] Thomas Uhrmann et al., Solid State Technology, pp.14, July 2014 
[9] http://www.monolithic3d.com /hkmg.html 
[10] Yuniarto Widjaja US Patent 8,514,623 
[11] http://www.monolithic3d.com/ultra-large-integration---redundancy-and-repair.html 
[12] http://www.monolithic3d.com/blog/how-much-does-ion-cut-cost1 
[13] L. Chang, IBM Short Course, IEDM 2012 
[14] Hai Wei, et al., IEDM 2012 
[15] D. C. Sekar US Patent 8,686,428.

Presentation:
Precision Bonders - A Game Changer for Monolithic 3D, IEEE S3S 2014, October 2014. 

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the emergence of monolithic 3D technology in the near future.

The coming 2014 IEEE S3S conference (October 6-9) is first one to focus on the emergence of monolithic 3D technology. It is fitting that it would be the forum at which a key decisive breakthrough for monolithic 3D IC ("M3DI") technology will be presented. This game changing breakthrough is the first ever monolithic 3D flow that allows a fab to build a monolithic 3D integrated device while using the fab’s existing transistor process flow, without the need to develop and qualify new transistors and a new transistor formation flow.

Recent blogs such as Established Nodes Getting New Attention and Moore's Lag Shifts Paradigm of Semi Industry have articulated the building up of interest in SOI, Sub-threshold and 3D IC technologies. The IEEE S3S is the conference to learn and get updated on these technologies and M3DI is that newest part integrated into the conference. The 3D part of S3S 2014 will have a full day of tutorial presentations by leading researchers in the space, a full session of invited papers, and will conclude with a session dedicated to discussing the most recent breakthroughs in the field.

The M3DI short course will cover alternative process flows that enable M3DI, discuss the challenges and solutions to removal of the operating heat of monolithic 3D stacks, and describe the range of powerful advantages provided by M3DI. Subsequently, Prof. Sung Kyu Lim of Georgia Tech will cover EDA for M3DI. This will be followed by broad coverage of M3DI for memory applications by two leading experts in the field, Akihiro Nitayama of Toshiba/Tokohu University and Deepak Sekar of Rambus. M3DI provides unparalleled heterogeneous integration options which will be covered by Prof. Eugene Fitzgerald of MIT and SMART Lee Institute of Singapore describing the integration of silicon with other crystals for electro-optic device integration. The short course will conclude with Prof. Philip Wong of Stanford, who leads research efforts to integrate silicon with carbon nanotube and advanced 2D transistors layered with memory such as STT-MRAM and RRAM.

In the special invited 3D Hot Topics session we expect to get a full spectrum of the latest progress in the field. Particularly worth noting is the recent progress on the work done by CEA Leti with involvement of ST Micro, IBM and supported by Qualcomm. This work shows both a practical path to monolithic 3D IC and cost analysis of the monolithic 3D advantages. The following chart illustrates the reasons for the high interest in the technology.

And then there is a great dessert to this 3D feast. On Thursday afternoon, in the 3D New Developments session, a game changing breakthrough technology will be presented. Leveraging the breakthrough progress in wafer bonding technology, presenting for the first time ever a monolithic 3D flow using existing fab transistor process. Any fab could utilize this breakthrough to provide far better products at minimum capital and R&D investment. This game changing flow removes the historical differentiation between sequential and parallel 3D, and should significantly reduce the time for monolithic 3D adoption throughout the semiconductor industry.

For a postprandial enjoyment, CEA Leti will present in the Late News session a fully constructed M3DI SOI device, and IBM will present its Multi Stacked Memory Wafer technology.

More information is available on the conference site: S3S Conference 2014

We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Mr. Or-Bach discusses about the paradigm shift in the semiconductor industry. 

In our blog 28nm – The Last Node of Moore's Law, we had pointed out that the change has happened, and it is no longer a matter of forecast or prediction. In this blog we will start by reviewing some of what has transpired since that blog, and then focus on the ensuing paradigm shift in the semiconductor industry.

The following chart was presented in the IEEE IITC workshop by Globalfoundries. It illustrates the cost impact of the double patterning required for scaling below 28/22 nm. 

Soon after Rick Merritt’s coverage of Semicon West - 13 Things I Heard at Semicon West -- Rick wrote: "Moore's Law has definitely slowed" quoting Gartner semiconductor analyst Bob Johnson."No matter what Intel says, Moore's Law is slowing down" and, Bob added, "Only a few high-volume, high-performance apps can justify 20 nm and beyond."

Soon thereafter Peter Singer, in a blog post about the ConFab 2014 –  Can we take cost out of technology scaling? -- quotes Dr. Gary Patton, VP of semiconductor research and development center at IBM: “The challenge we’re facing now is two fold. Number one, we’re struggling to get that 0.7X linear scaling. It might be about 0.8X. And we’re adding a lot more complexity, especially when you adding double and triple patterning."

And now, in early August we finaly got more information from Intel about their up coming 14nm. In our blog Intel vs. Intel we articulate that Intel’s numbers indicate that Moore’s Law had stopped at 28/22 nm both in terms of the bring-up time it takes and the cost of new technology nodes.

It is hard to accept that a trend that has held strong for 50 years, and which kept going many years after multiple predictions of its imminent demise, has really stopped. And it is even harder as we watch the huge effort of bringing up the 14 nm and 10 nm nodes. Yet it seems that everybody should agree that the semiconductor industry is now going through a paradigm shift and for most designs 28nm is, at least for some time, the last node of Moore's Law.

The following charts are well known and present the reason for that change.

It shows that the design cost increases by more than $100M from 32nm to 16nm. If we assume a die cost of $10 at 32 nm and we assume that the traditional cost reduction per node still holds, then we would need a volume of more than 20 million units just to break even. If one also considers the risk associated which such a design, it would actually require more than 100 million units, or at least $1B of market, for such device to justify the investment. Clearly, very few designs have the market for 100 million units or $1B market.
The following chart by IBS presents the past trend in design starts per node. Clearly, most new designs are still done in 130 nm while the node with the fastest ramp-up is 65 nm.

The forcast for 2016 at Semiconductor Technology Nodes – History, Trends and Forecast is illustrated in the following pie chart:

Yet again it indicates a very slow shift to more advanced nodes, and the expectationis that even in 2016 most new designs will still be done in 130nm.

This is clearly a paradigm shift in the industry, and the industry is responding accordingly.

Just prior to 2014 Semicon West, we have seen the conclusions of the SEMI’s World Fab Forecast -- Technology Node Transitions Slowing Below 32 nm. The Forecast uses a bottom-up methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. The chart below illustrates this new paradigm.

The report states: “The cost per wafer has become an increasing concern below the 32nm node.   The expected cost reduction benefit of production at smaller nodes is diminishing and is not keeping pace with the scaling benefits in many cases.  This has widespread and fundamental implications for an industry long following the cadences of Moore’s Law… These may be contributing factors as to why some volume fabs are exhibiting a lag in beginning production of a new technology node.  Now evident quantitatively for the first time, there is evidence of a clear slowdown in volume production scaling of leading technology node transitions.” (emphasis added)

This was followed by another EE Times article – Silicon Highway Narrows, Twists: “Most foundries have yet to start buying the capital equipment needed for the 14/16 nm node, which for many will be the first to support FinFETs, says Trafas of KLA-Tencor. Gear companies hope the orders start coming in the fall…Indeed, he says, one of the big questions many capital equipment execs will bring to this year's Semicon West event on July 7 is, "When will the 16/14 nm investments begin?"

In the same vein, Ed Sperling continued in Established Nodes Getting New Attention: "Work is under way to improve energy efficiency and boost performance without relying on multi-patterning or finFETs. As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors."

And a week later Samuel Wang, an analyst with Gartner, in Who’s Winning The FinFET Foundry Race? wrote: “Short-term, during the first two years of finFET production, there is no need for more than 50,000 wafers a month capacity from all foundries to satisfy the market demand for finFETs, …In the long run and before 2018, there is no need to have more than 250K wafers a month capacity to support the market demand for finFETs."    The EDA industry also is recognizing this paradigm shift. Dr. Aart de Geus in his keynote to the 2014 Synopsys User Group titled Designing Change Into Semiconductor Techonomics, recognized this shift with a series of slides articulating how EDA tools that were developed to support the new technology nodes could also benefit design efforts of old nodes:  

The IP industry is recognizing this paradigm shift as well, visible in IP Reaches Back To Established Nodes: "As SoC developers shift backward to established nodes, steps can be taken to improve the IP’s functionality. Driven by the IoT and wearable market opportunity, SoC developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality."

There also a clear effort to add value and innovation to older nodes by incorporating technology such as SOI and low Vt, known as sub-threshold designs. Most notable was the recent Samsung announcement of licensing FD-SOI from ST Micro for the established node of 28 nm. Some quotes from the articles above illustrate this trend:

* Krishna Balachandran, product marketing director for low power at Cadence. “Threshold voltage manipulation like forward biasing has been selectively used to speed up critical portions of the IP at the expense of increased leakage that is restricted to those sections of the IP without significant overall impact.”

* ARM Fellow Rob Aitken said energy savings are significant using the same exact processors differently. Moreover, it’s most effective at established process geometries where there are no finFETs. But it isn’t a simple process. (For a deeper understanding of this subject, click here). “We can get 4X to 6X improvements in energy,” said Aitken. “That doesn’t come for free, because we have to make some design changes to allow the design to operate down at this low energy point. But if we do this wrong, the overhead we have to add to get these savings is more than you get in terms of a benefit.”

* Mary Ann White, director of product marketing for the galaxy design platform at Synopsys: "Body biasing is another technique that is being recycled. It entered the picture at 90nm, when design teams found they could reduce leakage by as much as 30%. Even at 45/40nm, savings were in the 20% to 25% range. But at 28nm, the benefit for bulk CMOS dropped to as low as 2%,...When you use biasing, you are using extra tracks and extra resources, which may include one or two extra rails,” said White. “But the benefit was falling off at 28nm using planar CMOS. Interest is picking up again with FD-SOI. What’s interesting about this is we used to insert biasing at the back end, where you require a bulk n-well or p-well pin. But recently we’ve had a request to add that capability into UPF. We rolled that out with skepticism on our part, but we’ve been getting a lot of interest. If you’re adding 5% area for better power, it’s worth it.” (See related discussion.)

This paradigm shift could be a real blessing to the industry. The escalating costs drove out VCs from investing in semiconductor start-ups, drastically narrowed the number of vendors and the number of advanced new designs. It left little room for innovation or anything other than rushing to the next technology node. Now it seems that a whole new industry dynamic is taking place, innovation is being embraced, new markets are being explored, and hopefully we will see the return of VCs with the increase of semiconductor vendors and technologies.

This is also the time to pay increased attention to semiconductor technologies that could offer better intrinsic devices without traditional dimensional scaling. Most notable among those would be, SOI, Monolithic 3D, and Sub-threshold design. The 2014 S3S Conference scheduled for October 6-9, 2014, at the Westin San Francisco Airport would be a great opportunity to learn more about those technologies as it provides the latest research results along with workshops, tutorials and range of invited papers. The conference advance program is now available at < http://s3sconference.org/program/ >. It looks now to be the one conference that active members of the semiconductor industry should not miss.