Recently I read a very uncommon report title: "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless". Quoting directly: “One of the unspoken rules of customer-foundry relations is that you virtually never see the former speak poorly of the latter. Only when things have seriously hit the fan do partners like AMD or NVIDIA admit to manufacturing problems... That’s why we were surprised - and our source testified to being stunned - that Nvidia gave the following presentation at the International Trade Partner Conference (ITPC) forum last November”

The only explanation I can come up with is that NVIDIA is in a panic. And according to Andy Grove’s “Only the Paranoid Survive” I believe NVIDIA will overcome the challenge, and at the later part of this blog we will present our view for an action plan. But first let’s try to understand what the issue is about.

It all starts with the diminishing return of dimensional scaling. This time it is about costs. Dimensional scaling requires continual improvements in lithography capability, and is primarily driven by the rapidly escalating cost of lithography, as illustrated by the following chart:

Now that the cost of lithography dominates the cost of Fabs and accordingly the cost of a finished wafer, the cost reduction associated with getting more dies per wafer (scaling) becomes neutralized by the higher cost of wafers. This was recently articulated in View Point in EE Times by Dr. Handel Jones and illustrated by the following chart.

Furthermore, pure foundry leader TSMC publicly showed the issue as seen in the following chart

And accordingly the following charts from NVIDIA present the same trend in a very clear way:

Moreover, another chart by NVIDIA shows the higher cost of wafers eating away at the benefits of dimensional scaling:

But this is clearly not TSMC’s fault. So why: "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless"? And why would NVIDIA care? If the price will stop going down they should be happy to be able to charge more as long as their competitors need to do the same. And it is hard to believe AMD would see different curves from TSMC??

But careful review of the bullet slide above and the bullet slide below might reveal NVIDIA’s underlying  concerns.

Both slides indicate real concerns and reflect some form of panic.

It seems to me that the key words are “Virtual IDM”, which are the only highlighted words of the second bullet slide but do appear also in the first one.
“When business ($) gets in the way, apply “First principle”, the principle of one company, one virtual IDM company”. I was not aware of this “First principle”. I thought our first principle is open competition, and individual companies are supposed to work as such and not as one company I believe we have some laws - Antitrust - against acting as one company instead of individual company.
Yet, NVIDIA does have one strong IDM competitor - Intel. Could it be that Intel’s costs are different??

I don't know but it does remind me of a previous blog I wrote: Required Change in EDA Vendors’ Role and Reward vs. Scaling Yield. In that blog we tried to understand the implication of dimensional scaling on yield, and more specifically on the systematic yield losses which are design related. The following chart was presented then

In that blog we suggested that an IDM would have a significant advantage over the “partnership” of Fabless-Fab-EDA.

Looking again on the cost related chart one can clearly see NVIDIA pointing to the importance of yield. But I believe they should not blame just TSMC as it would seem to me that the EDA part is just as important.
NVIDIA, TSMC and the other fabless companies and partners (EDA, etc.) should strategically consider the issues associated with dimension scaling, which seem to strongly benefit the IDMs. Such strategic evaluation should include a serious look into the better alternative to dimensional scaling - the monolithic 3D, or as we call it, scaling Up!!!

A recent book review by Peter Clarke on this wonderful new book by Bernd Hoefflinger caught my eye, and also reminded me of an old connection I have with Hoefflinger.

Early in the 90's I had the pleasure to collaborate with Hoefflinger, who at that time was the director of the Institute for Microelectronics Stuttgart (IMS CHIPS). I was the CEO of Chip Express then and we worked together to demonstrate that applying Direct-Write-eBeam to a Chip Express wafer could lead to a very effective Gate-Array prototyping scheme and to low volume production of those Gate-Arrays.

It was great pleasure to reconnect and to read "Chip 2020"
I highly recommend this book as it provides an update view of the Semiconductor Industry by a group of known experts in our field.
The book provides a concise review how we got here and what is ahead for us up to the year 2020.

The book presents a now more common view that the scaling that got us here is gone, and that there are concrete red-bricks for dimensional scaling beyond 2020. Primarily:

1. As gate sizes reach ~10nm we would have nominally 6 atoms of impurity in the channel with a commensurate variation that would constrain effective use of the transistor -see Fig. 1.1

2. As lithography tools are already forced to use double exposure/processing it has became unclear if an effective lithography is going to be available to move forward. See the Table 8.3 below, provided by Burn J. Lin of TSMC

Clearly the future cost of lithography eats away at the cost advantage of dimensional scaling.

Hoefflinger presents some options to tackle these challenges as detailed through the book and with respect to specific segments of the industry. The following Fig. 3.1 presents these future technologies:

At MonolithIC 3D we were pleased to see the important role given to 3D IC in the book as shown in the Fig. 3.1 above.

In short I fully agree with Peter Clarke’s statement: "The book offers some far-reaching and fundamental insights" and I highly recommend the book to semiconductor technologists who are looking forward toward the next decade of progress in the field.