We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about Moore's Law and the impact of it on the industry today.
The assertion that Moore made in April 1965 Electronics
paper was:"Thus there is a minimum cost at any given time in the evolution of the technology. At present, it is reached when 50 components are used per circuit. But the minimum is rising rapidly while the entire cost curve is falling (see graph below)."
"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years."
Clearly Moore's law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays - transistors) to achieve minimum cost will double every year.
The reduction of cost per component for many years was directly related to the reduction in feature size - dimensional scaling. But many other technology improvements made important contributions as well, such as increasing the wafer size from 2" all the way to 12".
But many observers these days suggest that 28nm will be the optimal feature size with respect to cost for many years to come. Below are some charts suggesting so:
And more analytical work by IBS’ Dr. Handel Jones
Graphically presented in the following chart
Or as nicely drawn by Globalfoundries
Yes, we probably can keep on scaling but, clearly, at escalating complexity and with completely new materials below 7nm. As dimensional scaling requires more advanced lithography it is clear that costs will keep moving up, and the additional complexity of transistor structures and all other complexities associated with these extreme efforts will most likely drive the costs even higher.
Looking at the other roadmap chart provided by IMEC
and focusing on the SRAM bit cell in the first row, the situation seems far worse:
Since at 28 nm SRAM bit cell is already 0.081μm2
, this chart indicates that future transistor scaling is barely applicable to the SRAM bit cell, which effectively is not scaling any more.
Unfortunately, most SoC die area is already dominated by SRAM and predicted to be so even more in the future, as illustrated by the following chart:
Source:. Y. Zorian, Embedded memory test and repair: infrastructure IP for SOC yield, in Proceedings the International Test Conference (ITC), 2002, pp. 340–349
Dimensional scaling was not an integral part of Moore's assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore. The following chart captures Samsung’s view of the future of dimensional scaling for NV memory, and it seems relevant to the future of logic scaling just as well.
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi's blog post is about the scaling process that makes monolithic 3D IC practical.
In the 1960s, James Early of Bell Labs proposed three-dimensional structures as a natural evolution for integrated circuits. Since then many attempts have been made to develop such a technology. So far, none have been able to overcome the 400°C process temperature limitation imposed by the use of aluminum and copper in modern IC technologies for the underlying interconnects without great compromises. The “Holy Grail” of 3D IC has been the monolithic 3D, also known as sequential 3D, where a second transistor layer could be constructed directly over the base wafer using ultra-thin silicon – less than 100nm – thus enabling a very rich vertical connectivity.
Accordingly the industry developed a 3D IC technology based on TSV (Thru Silicon Via) where each strata (wafer) could be independently processed, then after thinning at least one wafer, place in a 3D configuration, and then connect the strata with TSV using a low temperature (<400°C) process. This independent (parallel) processing has its own advantages; however, the use of thick layers (>50 µm) greatly limits the vertical connectivity, requires development of all new processing flows, and is still too expensive for broad market adoption. On the other hand, monolithic 3D IC provides a 10,000x better vertical connectivity and would bring many additional benefits as was recently presented
in the IEEE 3D IC conference.
The semiconductor industry is always on the move and new technologies are constantly being introduced making changes the only thing that is constant. For the most part dimensional scaling has been associated with introducing new materials and challenges, thereby making process steps that were once easy far more complex and difficult. But not so in respect to monolithic 3D IC.
The amount of silicon associated with a transistor structure was measured in microns in the early days of the IC industry and has now scaled down to the hundreds and the tens of nano-meters. The new generation of advanced transistors have thicknesses in nanometers as is illustrated in the following ST Micro slide.
Dimensional scaling has also brought down the amount of time used for transistor activation/annealing, to allow sharper transistor junction definition, as illustrated in the following Ultratech slide
Clearly the amount of heat associated with transistor formation has reduced dramatically with scaling as less silicon gets heated for far less time.
And unlike furnace heating or RTP annealing, with laser annealing the heat is coming from the top and directed only on small part of the wafer as illustrated below.
The following illustrates Excico pulsed excimer laser which can cover 2×2 cm2 of the wafer.
Worth noting that this week we learned of good results when utilizing Excico laser annealing for 3D memory enhancement – Laser thermal anneal to boost performance of 3D memory device
These trends help make it practical to protect the first strata interconnect from the high temperature process required for the second strata transistor formation. As the high temperature is on small amount of silicon for a very short time and for a small part of the wafer, the total amount of thermal energy required for activation/annealing is now very small.
One of the three most newsworthy topics and papers included in the 2013 IEDM Tip Sheet for the “Advances in CMOS Technology & Future Scaling Possibilities” track was a monolithic 3D chip fabricated using a laser (reported by Solid State magazine “Monolithic 3D chip fabricated without TSVs
“). Quoting: “To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then used a novel low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated high performance – 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products.”
Furthermore, in last two weeks we presented in the IEEE 3D IC and IEEE S3S conferences an alternative simulation based work. We suggested to use a smart-cut® for the formation of the second strata (and not amorphous silicon crystallization) with innovative shielding layers to protect the first strata interconnect, as illustrated below.
Currently there are at least three different laser annealing systems offered on the market. The shielding layers could be adjusted according to the preferred choice of the laser annealing system. Our simulations show that if an excimer laser such as one offered by Excico is used, then even without these shielding layers the first strata routing layers are not adversely impacted by the laser annealing process.
Summary: In short, dimensional scaling is becoming harder and yet it makes monolithic 3D easier. We should be able to keep scaling one way or the other (or even both), and keep enjoying the benefits.
Note: smart-cut® s a register TM of Soitec
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi details MonolithIC 3D Inc's participation at the upcoming events in 3D IC field and the key role of the company in each event.
This coming October there are two IEEE Conferences discussing 3D IC, both are within an easy drive from Silicon Valley.
The first one is the IEEE International Conference on 3D System Integration (3D IC)
, October 2-4, 2013 in San Francisco, and just following in the second week of October is the S3S Conference on October 7-10 in Monterey. The IEEE S3S Conference
was enhanced this year to include the 3D IC track and accordingly got the new name S3S (SOI-3D-Subthreshold). It does indicate the growing importance and interest in 3D IC technology.
This year is special in that both of these conferences will contain presentations on the two aspects of 3D IC technologies. The first one is 3D IC by the use of Through -Silicon-Via which some call -”parallel” 3D and the second one is the monolithic 3D-IC which some call “sequential.”
This is very important progress for the second type of 3D IC technology. I clearly remember back in early 2010 attending another local IEEE 3D IC Conference: 3D Interconnect: Shaping Future Technology.
An IBM technologist started his presentation titled “Through Silicon Via (TSV) for 3D integration”
with an apology for the redundancy in his presentation title, stating that if it 3D integration it must be TSV!
Yes, we have made quite a lot of progress since then. This year one of the major semiconductor research organization – CEA Leti – has placed monolithic 3D on its near term road-map, and was followed shortly after by a Samsung announcement of mass production of monolithic 3D non volatile memories – 3D NAND.
We are now learning to accept that 3D IC has two sides, which in fact complement each other. In hoping not to over-simplify- I would say that main function of the TSV type of 3D ICs is to overcome the limitation of PCB interconnect as well being manifest by the well known Hybrid Memory Cube consortium
, bridging the gap between DRAM memories being built by the memory vendors and the processors being build by the processor vendors. At the recent VLSI Conference Dr. Jack Sun, CTO of TSMC present the 1000x gap which is been open between on chip interconnect and the off chip interconnect. This clearly explain why TSMC is putting so much effort on TSV technology – see following figure:
Figure 1: System level interconnect gaps
On the other hand, monolithic 3D’s function is to enable the continuation of Moore’s Law and to overcome the escalating on-chip interconnect gap. Quoting Robert Gilmore, Qualcomm VP of Engineering, from his invited paper at the recent VLSI conference: “As performance mismatch between devices and interconnects increases, designs have become interconnect limited. Monolithic 3D (M3D) is an emerging integration technology that is poised to reduce the gap significantly between device and interconnect delays to extend the semiconductor roadmap beyond the 2D scaling trajectory predicted by Moore’s Law…” In IITC11 (IEEE Interconnect Conference 2011) Dr. Kim presented a detailed work on the effect of the TSV size for 3D IC of 4 layers vs. 2D. The result showed that for TSV of 0.1µm – which is the case in monolithic 3D – the 3D device wire length (power and performance) were equivalent of scaling by two process nodes! The work also showed that for TSV of 5.0µm – resulted with no improvement at all (today conventional TSV are striving to reach the 5.0µm size) – see the following chart:
Figure 2: Cross comparison of various 2D and 3D technologies. Dashed lines are wirelengths of 2D ICs. #dies: 4.
So as monolithic 3D is becoming an important part of the 3D IC space, we are most honored to have a role in these coming IEEE conferences. It will start on October 2nd in SF when we will present a Tutorial that is open for all conference attendees. In this Monolithic 3DIC Tutorial we plan to present more than 10 powerful advantages being opened up by the new dimension for integrated circuits. Some of those are well known and some probably were not presented before. These new capabilities that are about to open up would very important in various market and applications.
In the following S3S conference we are scheduled on October 8, to provide the 3D Plenary Talk for the 3D IC track of the S3S conference. The Plenary Talk will present three independent paths for monolithic 3D using the same materials, fab equipment and well established semiconductor processes for monolithic 3D IC. These three paths could be used independently or be mixed providing multiple options for tailoring differently by different entities.
Clearly 3D IC technologies are growing in importance and this coming October brings golden opportunities to get a ‘two for one’ and catch up and learn the latest and greatest in TSV and monolithic 3D technologies — looking forward to see you there.
“Moore’s Law Dead by 2022” announces EE Times headline reporting
Bob Colwell’s keynote at Hot Chips this week. Actual quote: "Moore's Law -- the ability to pack twice as many transistors on the same sliver of silicon every two years -- will come to an end as soon as 2020 at the 7nm node". Collwell told the audience that DARPA “tracks a list of as many as 30 possible alternatives to the CMOS technology that has been the workhorse of Moore's Law …My personal take is there are two or three promising ones and they are not very promising,". Colwell is the Director of DARPA’s Microsystems Technology Office (MTO) and has both visibility and credibility in these matters. In fact, this is not his first time to publicly state the end of Moore's Law -- he did so at ACM SIGDA
and DAC meetings earlier this year. His slide (below) clearly presents the gap between the end of dimensional (Dennard) scaling and the establishment and ramp-up of alternatives to the current silicon based technology.
The discussion at EE Times remind us that we have "been hearing this for 20 years or more", so why is it different now? Well, even in the crying wolf story the wolf eventually did come! This time the signs are very clear. In fact, one could argue that as far as cost reduction, Moore's Law is already dead. The following ASML chart clearly shows it.
Taking into account additional information released during the recent Semicon West, it seems that effective cost for most fabless companies might even go higher with future scaling. Even if we ignore the fact that most foundries chose to keep their metal rules at 20nm when going to 14nm node, with the associated end-device cost implications, advanced nodes come with many additional layout restrictions. Those create circuit design and interconnect overheads that eat away a large part of theoretical scaling benefits. Quoting Andrew Kahng
: "Constant area-factors allowed prior node scaling to be 2x, however since 2009 the real scaling has been 2E(2/3)x or ~1.6x due to an “IC Design Gap"
. Add to it the fact that embedded memory SRAM bit cell is expected to barely scale, as shown in the following slide, and end-product costs might go up even for the same SoC complexity!
The following chart from Samsung clearly illustrates this dynamics for NAND, but from the above discussion it may be even more true for SoC.
The issue of cost has very significant implications. For the semiconductor industry Moore's Law is not just a matter of pride: it became one of its fundamental business drivers. In the food industry vendors keep on selling food as it get consumed, clothing and car industry products get worn out or go out of fashion. But in the semiconductor industry old products mostly get displaced by better new products – the upgrades. Imagine what would happen to the major industry players’ stock if they were to update their projections to expect 20% reduction in revenue!!!
And 20% might be a conservative number once the dynamics of the last 30 years would hit a hard stop.
The following Samsung chart is a good illustration of where we are and the choice that at least Samsung has made:
We can keep on hoping that the wolf will never come, just as it hasn't before. Or we can take action now before 'they comes'.
Samsung, Toshiba and the rest of the NAND industry are already taking action. On the SoC side the challenges are as severe, yet at this point the industry is consumed by the enormous efforts to bring up FinFETs. It may even bring up compound semiconductors (III-V) for the next node (10nm), but then what? At what cost? For what kind of return?
It seems to me that the right moves are:
First, logic design market needs to adopt an alternative to the embedded memory. IBM stated at the recent Common Platform Forum that adopting eDRAM gave it the equivalent benefit of one node scaling. This was seconded by Intel’s recent announcement of integrating eDRAM with their new Haswell processor - Intel eDRAM attacks graphics in pre-3-D IC days. An even better option would be the one transistor two state memory breakthrough solution recently developed by Zeno Semiconductors.
Second, logic design needs to follow the NAND industry by developing monolithic 3D technology for SoC and logic products. In a recent blog we reported that CEA Leti has placed Monolithic 3D is now on the roadmap for 2019
. We are pleased to announce that we will provide a tutorial on monolithic 3D as a part of the upcoming IEEE 3D IC Conference
in early October in San Francisco, and we will follow with a plenary talk the following week at the IEEE S3S Conference
in Monterey. In these conferences we also plan to present a new practical process flow for monolithic 3D, leveraging industry’s shift to laser annealing. This technology supports 3D technologies we had presented in the past, and can be used independently for new monolithic 3D process flows. We are looking forward to meeting you all there.
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses the starts of mass production for the industry's first 3D vertical NAND flash by Samsung.
Samsung announced today
(Aug. 6, 2013) the mass production of the industry's first three-dimensional (3D) Vertical NAND (V-NAND) flash memory, which breaks through the current scaling limit for existing NAND flash technology. Achieving gains in performance and area ratio, the new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid state drives (SSDs).
Samsung's new V-NAND offers a 128 gigabit (Gb) density in a single chip, utilizing the company's proprietary vertical cell structure based on 3D Charge Trap Flash (CTF) technology and vertical interconnect process technology to link the 3D cell array. By applying both of these technologies, Samsung's 3D V-NAND is able to provide over twice the scaling of 20nm-class planar NAND flash.
"For the past 40 years, conventional flash memory has been based on planar structures that make use of floating gates. As manufacturing process technology has proceeded to the 10nm-class and beyond, concern for a scaling limit arose, due to the cell-to-cell interference that causes a trade-off in the reliability of NAND flash products. This also led to added development time and costs.
Samsung's new V-NAND solves such technical challenges by achieving new levels of innovation in circuits, structure and the manufacturing process through which a vertical stacking of planar cell layers for a new 3D structure has been successfully develop...
Also, one of the most important technological achievements of the new Samsung V-NAND is that the company's proprietary vertical interconnect process technology can stack as many as 24 cell layers vertically, using special etching technology that connects the layers electronically by punching holes from the highest layer to the bottom. With the new vertical structure, Samsung can enable higher density NAND flash memory products by increasing the 3D cell layers without having to continue planar scaling, which has become incredibly difficult to achieve”
It’s worth mentioning to the point that while the volume production of TSV based 3D IC is keep being pushed out as discussed in a recent blog: EUV vs TSV: Which one will become production ready first?
, this announcement indicates that monolithic 3D NAND is biting the forecast by few years as being illustrated by the following 2012 ITRS chart:
Clearly monolithic 3D is a promising alternative to dimension scaling, as one can read in this Samsung press release. It also abides very well to the low cost objective for mass production products.
Monolithic 3D technology provides multiple unique and powerful advantages as we present on our site under the tab: 3D-IC Edge
. Under item 5 we present the unique advantage that was first introduced in 2007, when Toshiba unveiled its Bit Cost Scalable (BiCS) technology. The unique advantage of 3D NAND is the ability to pattern and process multiple layers simultaneously.
This advantage comes very natural for regular layout fabrics such as memory, but it is also available for logic circuits. The driver for this advantage is the escalating costs of lithography in state of the art IC. The following charts illustrate the impact of dimensional scaling on lithography costs.
Currently critical lithography steps dominate the end device production costs as been illustrated in the following chart:
Accordingly, if the critical lithography step could be used once for multiple layers rather than multiple times for each single layer, then the end device cost would roughly be reduced in proportion to the number of layers processed simultaneously. Multiple memory architectures that support such drastic cost reduction has been presented in various conferences and other forums. Few of those had been presented in our blog: The Flash Industry's Direction, and MonolithIC 3D Inc.'s Solution...
This dramatic announcement by Samsung comes in less than a week since we posted the blog: Monolithic 3D is now on the roadmap for 2019
. It represents the beginning of a new trend for Moore’s Law – scaling up. As the memory segment of the industry shift its R&D budget and its capital equipment budget for scaling up, the shrinking camp supporting dimension scaling would need to pony up this shortage while facing escalating costs of dimension scaling. It is clear to us that the time to investigate various alternatives for scaling up has come, which also abides to the new industry roadmap recently presented.
"The Evolution of Scaling from the Homogenous Era to the Heterogeneous Era"
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi underlines the milestone for monolithic 3D in the semiconductor road map 2019.
In the recent CEA Leti day
, that took place as part of Semicon West 2013, Laurent Malier, Leti CEO presented his "A look at the coming Decade".
Slide 15 of the presentation provides Leti vision for CMOS roadmaps as presented here:
Monolithic 3D is presented on the road-map as the technology to follow 7nm process node.
Early this year we blogged - IEDM 2012: The pivotal point for monolithic 3D ICs
, it is quite reassuring to see monolithic 3D now as part of the industry road-map. As we discussed than the memory vendors are already gearing up for volume production of the 3D NAND as reported recently Toshiba to Build Fab for 3D NAND Flash
, leveraging monolithic 3D cost reduction advantage. It only makes senses for the CMOS market to follow. Doubters would ask why the industry would introduce new dimension to a road map that has been extremely successful for over 40 years. And the answer is very simple - because it is successful any more. We are all aware that the escalating costs of lithography had diminished transistors cost reduction as illustrated in the following ASML chart
But even if we ignore these issues we should remember that "Atoms don't scale" (as was phrased by Bernie Meyerson of IBM), and we are quickly approaching these limit as is presented by the following Intel chart:
And accordingly Mike Mayberry, director of its component research at Intel, said at the very recent IMEC Technology Forum "...has looked down the highway of conventional silicon development and reckons things become foggy beyond about the 7-nm node".
In fact Mike in his March 2013 presentation titled "Pushing Past the frontiers of Technology
" clearly also present the monolithic 3D on his road map as the following slides illustrates
As was very well stated by Mark Bohr - Senior Fellow of Technology and Manufacturing Group and a Director of Process Architecture and Integration of Intel:
"The Evolution of Scaling from the Homogenous Era to the Heterogeneous Era"
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses about MonolithIC 3D Inc.'s participation at Semicon West 2013.
Thanks to everybody who came by poster exhibition at the Silicon Innovation Forum at SemiconWest 2013 [SemiWest]
! We really enjoyed talking with you about all the exciting possibilities for new products and processes that are enabled by monolithic 3D IC.
Here is Zvi 'guarding' the poster:
Figure 1 - Zvi Or-Bach at Semicon West 2013
Atoms Don't Scale: Dennard type scaling is already reached diminishing returns and looks like going to 'hit the wall' near this decade's end. P. Farrar of IBM said it succinctly: Atoms Don't Scale, and Steve Punta of Intel said "hard to imagine good devices smaller than 10 lattices across - reached in 2020":
As well, Bob Cowell of Intel microprocessor fame, who is currently the head of DARPA's MTO (Microelectronic Technology Office)...the folks who are supposed to be looking way ahead...is publicly saying that Moore's Law is at its end and we will have (at least) a decade long gap (2020-2030) in device improvements:
We all know the trends...much higher lithography costs and litho driven defects, interconnect resistance and capacitance slowing performance, the connectivity is driving power budgets awry, and so on. And the result is that the historical cost trends that we have been enjoying are going to soon no longer be there. Will carbon nano-tubes, graphene, nanowires, InGaAs, spintronics,... save us? Not likely, and certainly not by 2020. What's the Answer?
Monolithic 3D can utilize the existing infrastructure, so the usual 5-10 years of development of evolutionary concepts places this solution as being capable for answering the 2020 call. TSVs (parallel 3D), if
the costs can be contained, can only address a very small part of the solution space.
Take a look at the monolithic 3D techniques and potential for more than Moore ever predicted. http://www.monolithic3d.com/3d-ic-edge1.html
As an industry, how are we going to fill the decade gap?
Give me a call or email if you want to talk more...
2nd edition of: "Dimensional Scaling and the SRAM Bit-Cell"
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi adds information to his previous blog post: Dimension Scaling and the SRAM Bit-Cell.
I just downloaded the ASML presentation from Semicon West2013 site - ASML's NXE Platform Performance and Volume Introduction. Slide #5 - IC manufacture's road maps - says it all.
Embedded SRAM will scale from 0.09ÂµmÂ² at 22-20nm node to 0.06ÂµmÂ² at 11-10nm node. In other words only 30% reduction instead of the 4x reduction expected of historical dimension scaling, to roughly 0.02ÂµmÂ²!!!
In our previous blog (attached below) that followed ISSCC 2013 we saw some early indication of this slowdown. Yet we were still surprised to realize how bad it really is. This might explain why after resisting IBM and other pushes for embedded DRAM, Intel announced few month ago that its Haswell processor will incorporate embedded DRAM after all.
Another point from this ASML slide is the adaption of monolithic 3D by the NAND Flash vendors. We believe this is a start of a trend, and that logic vendors has now one more reason to follow it.
The IEEE International Solid-State Circuit Conference Feb 17-21, 2013 just ended in San Francisco last week, and the issue of dimensional scaling as it relates to EUV and future per transistor device cost was an important topic in the plenary session. One important, and perhaps overlooked, aspect of the industryâs scaling issue relates to the future of the SRAM bit-cell within this framework of dimensional scaling. We would like to shine some light on this impending issue.
As widely reported in the industry and articulated by ASMLâs Executive VP & CTO Martin van den Brink at ISSCC 2013, there is substantial evidence that without EUV the cost of logic transistors is most likely going up with scaling. One slide he used to illustrate this is below:
The above slide arrived after Martin had presented another non-encouraging slide, showing the same view from three companies: a Broadcom chart of increasing cost per gate correlated with dimensional scaling, together with the now famous Nvidia chart of no more crossover of transistor cost below 28nm, and third a GlobalFoundries chart showing some limited value for EUV.
We may attribute Martin statements to ASML interest in promoting EUV, but since ASML has already received significant EUV participation from INTEL, Samsung and TSMC, it might indicate further bumps are on the road to bringing EUV to market. We don't know if EUV will ever become real, but we do know very well that it is been delayed, and delayed again, and delayed again. It was made public recently that EUV has probably already missed the 10nm process node -â10nm will be optical,â
said Ajit Manocha, chief executive of GlobalFoundries.
An even more interesting slide was presented by van den Brink:
This chart brings up an important aspect of dimensional scaling that has not been discussed much before - the scaling of the SRAM bit-cell. According to this chart, the SRAM bit-cell size might not be reduced from the 20nm to 10 nm node, and might even get larger at 7nm as it may need more than 8 transistors. (Sound familiar? Fabs are doing the same with BEOL metallization scalingâ¦little or none)
Modern logic devices demand a significant amount of embedded SRAM. In fact, more than 50% of the typical logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010)
The dominant embedded SRAM bit-cell architecture has been the 6 transistor cell (6T). And for many years this very cell has been hand-crafted using special design rules independently developed by foundries for every new technology node. It makes sense: the SRAM cell is a unique structure that does not obey normal logic design rules as it drives output against output anytime a write cycle is being performed. In many cases it is the SRAM cell that is the most sensitive portion of the logic device to process parameter variations and this sensitivity greatly impacts end device yield.
It well known that scaling the SRAM bit-cell has become harder and harder. Some vendors have already moved away from the 6T bit-cell in preference to the 8T (eight transistors) bit-cell. ISSCC 2013 had a significant number of papers that were presented using 8T SRAM. The few papers who kept the 6T SRAM embedded in their logic devices were forced to add read/write support circuits and additional overhead to enable the 6T bit-cell to function reliably.
Since SRAM bit scaling is now not able to keep up with logic scaling, the overall end device cost scaling could be even more disappointing than the transistor or gate cost illustrations above.
Of course, well aware of this trend, IBM has been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that in their 32nm product line the use of the embedded DRAM has given IBM the equivalent of a process node scaling benefit. Yet, as of now, most other vendors have not adopted eDRAM due to the process complexity and cost it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimensional scaling as the DRAM capacitor will be very hard to scale, the extra power for supporting DRAM will not be available and the cost of advance process development to add in extra complexity will be too high.
Accordingly we can learn from the recent ISSCC that dimensional scaling is facing the cost challenges we were aware of before in addition to new challenges that we might not have been aware of: the cost and the active/passive power handicaps due to the incompatibility of the 6T SRAM bit-cell with scaling.
As we have suggested before, now that monolithic 3D is practical, we could advance and maintain Moore's Law by augmenting dimensional scaling with 3D IC scaling. We could enjoy depreciated equipment charges for more years and much lower R&D engineering outlays that would bring down production and development costs, and also enjoy improvements to power and performance.
Another exciting option is to replace the 6T SRAM bit-cell with the 1T bi-stable
floating body memory cell invented by Zeno Semiconductor
. The Zeno bit-cell provides two stable states, analogous to an SRAM while only consuming ~20% area of a traditional 6T SRAM and requires considerably less power. The area and power savings over a traditional 6T SRAM improve further with scaling. Most excitingly the Zeno bit-cell is compatible with existing logic processes.
"Innovations for Next Generation Scaling"
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses The Common Platform Technology Forum 2013.
The 2013 Forum today (Feb 5, 2013) started with a presentation by Dr. Gary Patton, VP, IBM Semiconductor Research & Development Center. Gary very clearly articulated the two irresolvable challenges the industry now faces:
- On chip interconnect
These two challenges connect very well with our recent blog IEDM 2012 - The Pivotal Point for Monolithic 3D IC
. Gary showed both the exponential increase of RC which results from the dimensional scaling of copper below 100nm width and the high cost associated with double and quad patterning. In addition, he showed how the extreme scaling of the copper metallization creates reliability challenges such as fatal EM modes, and scaling of the insulator k breeds TDDB and strength issues. As a reminder, in the recent IEDM (Dec. 2012) short course, IBM presented the following slide indicating that interconnect now dominates device power!
L. Chang, D.J. Frank - IEDM 2012 Short Course – IBM Watson Research Center
Gary also presented a multi-decade past to future slide that resembles the one presented here below. The decade ending at the year 2000 was the good old days of easy scaling of planar transistor, which he called the gate oxide limit. Then the industry followed with a decade of "Material Innovation" that he called the planar device limit, and starting in 2010 is the beginning of the "3D Era" - 3D transistors and stacked devices.
Finally he shared with us his vision of 3D devices with three planes of devices:
- Logic Plane
- Memory Plane
- Photonic Plane
A vision we mutually share.
Now, here is my failure to understand. As a company who has been in the forefront of 3D and TSV research, IBM is well aware of the severe limitations of TSV as an alternative for vertical interconnect. The following cross-sectional picture by IBM, presented at the recent GSA Summit, clearly illustrates how large a TSV is in comparison to an interconnect via.
IBM Systems and Technology Group – GSA Silicon Summit 2012 (S.s lyer) – 2012 IBM Corporation
With TSVs of 5 micron diameters (and pitches of 15 micron due to keep out zones from stress issues) vs. vias of less than 50 nm, the ratio in vertical connectivity is 1:10,000 as illustrated in the following chart by Perinne Batude of CEA Leti.
Clearly IBM technologists are well aware of the many research papers showing that TSVs, with their relatively huge size compared to all the other on-chip elements, diminish the performance or power benefits in folding designs to 3D. For example, the chart below was presented by Kim at the 2011 IEEE International Interconnect Technology Conference. The chart illustrates the performance benefits of folding a design twice (4 tiers of transistors) as dependent on the via size. At a via size of 5 microns there are actually no benefits, while at a via size of 0.1 micron the benefits are the equivalent of two nodes of dimension scaling!!!
So can someone please explain to me how come IBM is still talking about TSV as if it is the only representative of the "3D Era"???
And particularly now, when monolithic 3D is finally practical, and the NAND Flash memory vendors are adopting it across the board!?
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses The Pivotal Point for Monolithic 3D IC.
From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here’s why:
We start with the EE Times article IEDM goes deep on 3-D circuits
, starting with "Continuing on the theme of 3-D circuit technology addressed in an earlier post
about this year’s International Electron Device Meeting, Rambus, Stanford University and an interesting company called Monolithic 3D will address issues related to cooling 3-D circuits. .." and follow with a quote from the abstract to IEDMs short course "Emerging Technologies for post 14nm CMOS
" organized by Wilfried Haensch, of IBM’s Watson Research Center:
"Scaling the dimension was the key for the unprecedented success of the development of IC circuits for the last several decades. It now becomes apparent that scaling will become increasingly difficult due to fundamental physical limits that we are approaching with respect to power and performance trade-offs. This short course will give an overview of several aspects in this “end-of-scaling” scenario. ..."
"Yet there are a variety of developments in another type of 3-D scaling that are likely to have a similarly large impact on semiconductors in the near future - 3-D devices for NAND flash.... And as in planar CMOS logic, NAND flash technology has been progressively scaled to smaller feature sizes, becoming the process leader in driving the smallest line-widths in manufacturing as evidenced by the current 1x-nm (~19-nm) process node. Yet, despite plans to scale down to the 1y-nm (~15-nm) and possibly 1z-nm (~13-nm) nodes, the traditional planar floating gate NAND flash architecture is approaching the scaling limit, prompting the search for new device architectures. Not to be upstaged by the planar to 3-D (FinFET) transition in logic devices, NAND flash has embarked on its own 3-D scaling program, whereby the stacking of bit cells allows continuous cost-per-bit scaling while relaxing the lateral feature size scaling."
In our recent blog 3D NAND Opens the Door for Monolithic 3D
we discussed in detail the adoption of monolithic 3D for the next generations of NAND Flash. The trend was very popular subject of this year’s IEDM and is nicely illustrated by this older chart:
And accordingly the updated ITRS 2012 present the change from dimension scaling to monolithic 3D scaling as presented in the following slide.
This year’s IEDM brought up two of the driving forces behind the shift from dimensional scaling to monolithic 3D IC scaling, that we will detail below as #1 and #2.The Current 2D-IC is Facing Escalating Challenges:
- On-chip interconnect (#1)
- Dominates device power consumption
- Dominates device performance
- Penalizes device size and cost
- Dominates Fab cost
- Dominates device cost and diminishes scaling benefits
- Dominates device yield
- Dominates IC development costs
The problem with on-chip interconnect didn’t start today. This vintage Synopsys slide below clearly indicates that on-chip interconnect started to dominate overall device performance a decade ago:
In response, the industry has spent an enormous amount of money to convert from aluminum to copper and to low-K inter-metal dielectrics. But now, we have very few additional options left (perhaps air-bridge?) as illustrated by the following chart:
It shows that neither Carbon Nano Tube (CNT) nor Optical interconnect are better than copper, and that monolithic 3D still is the best path.
The practiced ‘band-aid’ fix so far has been throwing more transistors (they are getting cheaper, right? No longer. See father below) at the problem in the form of buffer and repeaters. But as we scale down we need exponentially more of these ban-aids as illustrated by the following:
"The 14 nanometer node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design. On December 11, 2012, Applied Materials, Inc. will host an important forum in San Francisco to explore the path that interconnect technology must take to keep pace with transistor scaling and the transition to new 3D architectures.” (emphasis added)
This had been illustrated before in the following chart
And to make it crystal clear, IBM presented the following chart in its short course:
Power is now dominating IC design and clearly dimensional scaling does not improve the interconnect’s impact – see the following chart built from the ITRS Roadmap. The only effective path forward that addresses interconnect is monolithic 3D.
As for the second challenge – lithography – we start again with an old chart by Synopsys:
The implication is that any new node of dimensional scaling comes with escalating lithography costs; and sure enough, that’s what is happening. When litho costs are plotted over time, it fits a log-linear scale….this is not a sustainable trend.
The following chart illustrate the lithography escalating cost of equipment which directly reflect the wafer cost.
This resulted in the following slide by IBM at the GSA Silicon Summit 2012:
Quoting from the slide: "Net: neither per wafer nor per gate [are] showing historical cost reduction trends"
Another EE Times IEDM12 article covering a keynote given by Luc van den Hove, chief executive of IMEC, IEDM: Moore’s Law seen hitting big bump at 14 nm
, repeats the same conclusion. In fact, some vendors are already changing course accordingly. GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium (11 December, 2012) during IEDM12 week also acknowledged that their 14nm node will have a 20nm node metal pitch, and, just like GlobalFoundries, a similar die size and increase in per-transistor cost. So it would seem that also for lithographic reasons, the industry’s next generation path, and the continuation of Moore's Law, would be achieved by leveraging the third dimension.
Now that monolithic 3D is feasible and practical, the time has come to move in this new direction, as has been nicely illustrated by this concluding chart below