We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses The Pivotal Point for Monolithic 3D IC.
From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here’s why:
We start with the EE Times article IEDM goes deep on 3-D circuits
, starting with "Continuing on the theme of 3-D circuit technology addressed in an earlier post
about this year’s International Electron Device Meeting, Rambus, Stanford University and an interesting company called Monolithic 3D will address issues related to cooling 3-D circuits. .." and follow with a quote from the abstract to IEDMs short course "Emerging Technologies for post 14nm CMOS
" organized by Wilfried Haensch, of IBM’s Watson Research Center:
"Scaling the dimension was the key for the unprecedented success of the development of IC circuits for the last several decades. It now becomes apparent that scaling will become increasingly difficult due to fundamental physical limits that we are approaching with respect to power and performance trade-offs. This short course will give an overview of several aspects in this “end-of-scaling” scenario. ..."
"Yet there are a variety of developments in another type of 3-D scaling that are likely to have a similarly large impact on semiconductors in the near future - 3-D devices for NAND flash.... And as in planar CMOS logic, NAND flash technology has been progressively scaled to smaller feature sizes, becoming the process leader in driving the smallest line-widths in manufacturing as evidenced by the current 1x-nm (~19-nm) process node. Yet, despite plans to scale down to the 1y-nm (~15-nm) and possibly 1z-nm (~13-nm) nodes, the traditional planar floating gate NAND flash architecture is approaching the scaling limit, prompting the search for new device architectures. Not to be upstaged by the planar to 3-D (FinFET) transition in logic devices, NAND flash has embarked on its own 3-D scaling program, whereby the stacking of bit cells allows continuous cost-per-bit scaling while relaxing the lateral feature size scaling."
In our recent blog 3D NAND Opens the Door for Monolithic 3D
we discussed in detail the adoption of monolithic 3D for the next generations of NAND Flash. The trend was very popular subject of this year’s IEDM and is nicely illustrated by this older chart:
And accordingly the updated ITRS 2012 present the change from dimension scaling to monolithic 3D scaling as presented in the following slide.
This year’s IEDM brought up two of the driving forces behind the shift from dimensional scaling to monolithic 3D IC scaling, that we will detail below as #1 and #2.The Current 2D-IC is Facing Escalating Challenges:
- On-chip interconnect (#1)
- Dominates device power consumption
- Dominates device performance
- Penalizes device size and cost
- Dominates Fab cost
- Dominates device cost and diminishes scaling benefits
- Dominates device yield
- Dominates IC development costs
The problem with on-chip interconnect didn’t start today. This vintage Synopsys slide below clearly indicates that on-chip interconnect started to dominate overall device performance a decade ago:
In response, the industry has spent an enormous amount of money to convert from aluminum to copper and to low-K inter-metal dielectrics. But now, we have very few additional options left (perhaps air-bridge?) as illustrated by the following chart:
It shows that neither Carbon Nano Tube (CNT) nor Optical interconnect are better than copper, and that monolithic 3D still is the best path.
The practiced ‘band-aid’ fix so far has been throwing more transistors (they are getting cheaper, right? No longer. See father below) at the problem in the form of buffer and repeaters. But as we scale down we need exponentially more of these ban-aids as illustrated by the following:
"The 14 nanometer node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design. On December 11, 2012, Applied Materials, Inc. will host an important forum in San Francisco to explore the path that interconnect technology must take to keep pace with transistor scaling and the transition to new 3D architectures.” (emphasis added)
This had been illustrated before in the following chart
And to make it crystal clear, IBM presented the following chart in its short course:
Power is now dominating IC design and clearly dimensional scaling does not improve the interconnect’s impact – see the following chart built from the ITRS Roadmap. The only effective path forward that addresses interconnect is monolithic 3D.
As for the second challenge – lithography – we start again with an old chart by Synopsys:
The implication is that any new node of dimensional scaling comes with escalating lithography costs; and sure enough, that’s what is happening. When litho costs are plotted over time, it fits a log-linear scale….this is not a sustainable trend.
The following chart illustrate the lithography escalating cost of equipment which directly reflect the wafer cost.
This resulted in the following slide by IBM at the GSA Silicon Summit 2012:
Quoting from the slide: "Net: neither per wafer nor per gate [are] showing historical cost reduction trends"
Another EE Times IEDM12 article covering a keynote given by Luc van den Hove, chief executive of IMEC, IEDM: Moore’s Law seen hitting big bump at 14 nm
, repeats the same conclusion. In fact, some vendors are already changing course accordingly. GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium (11 December, 2012) during IEDM12 week also acknowledged that their 14nm node will have a 20nm node metal pitch, and, just like GlobalFoundries, a similar die size and increase in per-transistor cost. So it would seem that also for lithographic reasons, the industry’s next generation path, and the continuation of Moore's Law, would be achieved by leveraging the third dimension.
Now that monolithic 3D is feasible and practical, the time has come to move in this new direction, as has been nicely illustrated by this concluding chart below
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses how can heat be removed from 3D-IC Stacks.
Thanks to everybody who came to IEDM
this year, and especially to those I met and who came to paper 14.2, delivered by Hai Wei
University. You can find the meeting paper and slides here
One of the big challenges facing 3D-IC is how to remove the heat dissipated on the upper layers to keep a high performance chip temperature within the system and reliability constraints and prevent hot spots. Most existing proposed techniques rely on arrays of TSVs and thick (xxum) silicon layer to conduct and spread the heat laterally and vertically. We propose that properly designed PDNs* (Power Delivery Networks) can significantly contribute to heat removal in both parallel (think TSV and xx um thick Si layers) and monolithic/sequential (think 100nm Si layer) 3D-ICs.
We investigated both parallel and monolithic in the paper. Here, I will, of course, focus more on the monolithic challenges and solutions, but I will make some important comparisons to parallel at the end.
Since the 130nm node, we have entered an era in our industry where we are not only using new materials, but also new device structures. I have written previously
about the risk associated with this, and (hopefully…) made a case for monolithic 3D technology being the best way for the industry to move forward, still enjoying Moore’s Law type economics (i.e., lower cost) but with a much lower development risk.
Life is getting thin and narrow in our business….so, how best to take advantage of this nanometer and angstrom era and avoid the economic (think EUV at 110+M$ a pop, or double/quad patterning) and atomistic (think 7 nm) brick walls coming? Monolithic 3D stacking technology is the answer: keeping the next evolutionary step of our industry in the wafer fab
, where the batch economics of the silicon wafer can be enjoyed, and avoiding the costly piece-part assembly processes of TSVs.
One of the basic tenets of monolithic 3D is the ability to have thin (preferably monocrystalline) silicon layers that enable very small vertical interconnect manufacturing, and hence a large (>1 million/cm2) layer to layer vertical interconnect density in the stack. This opens up the possibility for powerful new architectures and devices, such as Amdahl’s wafer scale computer (see blog
) and cost effective MLC 3D memories
Two implications arise from the thin (on the order of 100nm or less) silicon layer stacking. First, that fully depleted (FD) devices, and hence silicon islands floating in an insulator such as silicon dioxide, will be the norm. Second, taking full advantage of a manufacturable aspect ratio etching (5:1 to 10:1), we will end up with a large density of very small layer to layer vias (of 1-2 lambda diameter), where vertical interconnect density rivals the horizontal density of interconnect that we have enjoyed thru the many cycles of Dennard
scaling. FD devices are soon to be the norm in 2DICs; for example, the thin UTBBOX
of STMicro/GlobalFoundries and the narrow FinFets
(incidentally, at IEDM12, Intel was criticized for doping the fins…).
Both of these implications, FD devices in islands of Si and very dense vertical interconnect, play a significant role in how we propose to solve a major challenge in 3D stacking.
Since the stacked layers are not in direct contact with the heat sink: How do we get the heat out of the stacked layers???
In short, the answer is to take the heat out of each silicon island with the power delivery network, move it laterally in the metal interconnect of that stack layer (just as if
we had a thick silicon layer underneath), and then vertically move the heat to the heat sink with that large density of interlayer vias (which we can now make due to the thin stacked layer being very thin).
Here’s a picture of what we are doing:
Sounds at least plausible, right?
Well, that’s what we set out to show, with the heavy lifting done by our friends at Stanford. Hai Wei & Tony Wu of Professor Subhasish Mitra's group
, Professor Mitra, and Professor Fabian Pease
, were the drivers in creating the simulation approach and engine to see if this works as we thought it might. It did, and then ended up developing a tool that may be very useful for future 3DIC design work.
Hai and Tony describe in the paper and the presentation the details of the simulation approach, engine, assumptions, and methodologies developed. Quite a nice piece of work! They have built an analysis framework that can be adapted for exploring technology-circuit-application interactions for a wide variety of 3D technologies, cooling options, and PDN designs. Types of 3DIC
technologies modeled are conventional TSVs
, called parallel 3D integration by many in the industry, and monolithic 3D integration, a type of sequential 3D integration. Cooling options range from conventional air cooling of the heat sink (2 W/K·
cm2) to external liquid cooling (10 W/K·
cm2) for high power systems. PDN designs studied ILV densities from 0 to 4 million/cm2.
That said, what are the essential takeaways?
First, the cooling benefits of PDNs are essential to achieve monolithic 3D integration. Without accounting for PDNs in the 3DIC thermal model, it will be next to impossible to achieve the desirable thermal characteristics and result of a 3D IC stack. Further, the density of ILVs is important to achieving the system thermal constraint. In the 100nm thick Si example below, the desired maximum chip temperature is 85°C or less.
Second, a processor can be effectively cooled, with no hot spots, using PDNs in a monolithic 3D configuration. Hai and Tony’s thermal analyses of core-on-core and memory-on-core designs, utilizing the OpenSPARC T1
industrial multi-core design operating running an 8-threaded program that solves the Black-Scholes
application (i.e., hot), showed significant improvement and no hot spots. The top silicon layer is 100nm thick and the hottest parts of the chips were operating at 138 W/cm2. Those hottest parts, the EXU units, were stacked directly on top of each other to show the worst case.
Combining these two seems to indicate that no PDN in the model versus designing and optimizing with thermal-aware PDNs makes the difference between being able to run the design (processor on processor in this example) at only 1/3 of the full power density or at a full power.
That’s the essential take-away for monolithic. Mimic the lateral heat conduction of thick silicon with the PDNs of the thin silicon stack layer, and then get that heat vertically to the heat sink with the dense network of vias provided by the monolithic 3D integration.
For the parallel 3D integration case, the 5um thick silicon greatly helps with the lateral heat conduction to the TSVs. With a properly designed PDN; however, there can be a significant savings in the number of TSVs (ILVs on chart below) used to vertically conduct the heat away, and thus offers a significant area savings by eliminating many of those big TSVs and Keep Out Zones (KOZs). (Note: for both the parallel and monolithic cases, Hai made the KOZ twice the ILV diameter as a conservative choice)
Moreover, by use of a properly designed PDN and an optimized density of TSVs, the maximum power density of the top layer in can be increased considerably …. from 35 to 50 W/cm2 for the parallel 3D case.
It is worth noting an important point from these graphs: At the optimum design point, where the density of ILVs coupled to the PDN satisfies the desired 50W/cm2 max allowed power density, the required number of TSVs to effectively conduct the heat costs about 3% of the chip area. For the monolithic case, the chip area cost is about half that.
A high density of small vias not only makes possible some powerful product architectures such as logic-cone level redundancy, but is also key to producing area efficient vertical heat conduction networks.
*Patent Pending technology
Imec's Luc van den Hove vs. Intel's Mark Bohr
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses EE Time's article about: "Moore’s Law seen hitting big bump at 14 nm".
The EE Times article
covering Imec's Luc van den Hove keynote talk at IEDM 2012 reports: "Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase—and still carry a hefty cost premium—due to the lack of next-generation lithography". Van den Hove provided the following slide photo as an illustration:
Yet, in an article about Intel’s 22nm IEDM presentation, EE Times is quoting
Mark Bohr of Intel: "Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel “is nowhere near that,” he said. “Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.
So who is right between those two giants?
Could it be that both of them are?
In a recent blog titled "Is the Cost Reduction Associated with Scaling Over?"
we presented charts clearly supporting Luc van den Hove, IMEC's CEO, position. The following slide from an IBM presentation includes an NVidia chart (which we also discussed in another blog, Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies?
Accordingly, it would seem that TSMC wafer costs are in line with Luc and so is the case with IBM.
GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium yesterday (Dec. 11) also acknowledged that their 14nm node will have a 20nm node metal pitch and, just like GlobalFoundries, a similar die size and increase in per-transistor cost.
In other words, it seems that the Luc van den Hove keynote is in-line with the cost road map of the non-Intel foundries!
Intel might indeed be different, yet something did cause Intel to take what seems like an extreme measure, when it put $4.1B in ASML just recently
If, however, Mark Bohr has not been misled by the Intel accounting department, and the Intel process is still providing a nice cost reduction at every node of scaling, then clearly Intel has a true competitive edge relative to all other foundries. I have no doubts that Intel has filed enough patents to protect its unique process advantage, but then I wonder why did Mark say
: "However . .. we don’t intend to be in the general-purpose foundry business … [and] I don’t think the [foundry] volumes ever will be huge [for Intel].”
If Mark Bohr is right, with such a competitive edge Intel should aggressively expand its foundry business, which would achieve both a great profit margin and rapid business growth. Now that Intel is looking for a new CEO its Board should consider it as a major criterion for who should lead Intel into the future.
Clearly, dimensional scaling (and its cost reducing benefits) is not what it used to be, and the market appetite for cheaper-faster-better consumer-oriented products grows stronger. Both Intel and non-Intel fabs should start development of monolithic 3D technology. ;-)
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about Qualcomm overtaking Intel in market capitalization.
On Nov 9, 2012 we learned that Qualcomm overtook Intel in market capitalization. Quite shocking news if one considers that Intel’s revenue is almost three times that of Qualcomm and its net margin is more than twice that of Qualcomm. Clearly investors evaluate Qualcomm using a different scale than what they use for Intel, as is evidenced by Qualcomm’s P/E of 20.12 vs. Intel's mere 9.07. EE Times explained it in an article that day stating: "In the eyes of investors who have driven up its market capitalization, the fact that Qualcomm is a fabless company relieves it of the burden of having to invest billions of dollars each year in process development and wafer fabs." However, given that TSMC, a pure foundry, has a P/E of 15.67, it behooves us to look for another explanation. It’s also worth noting that TSMC had a revenue growth of 2% in the last year, far less than Intel's 25.6%, and its net income actually went down vs. a net income growth by Intel of 213%!
My explanation is that it is all about IP strength. I will expand on it in the rest of this blog but as prime evidence I offer SanDisk, who sports a P/E of 20.78 yet has continued to invest heavily, together with its partner Toshiba, in fab capacity upgrades.
Let’s first look at the previous two decades as Intel grew consistently year after year while riding the PC business growth. During those years the team Intel + Microsoft was the exclusive vendor in the PC 'game'. All others had to compete neck to neck in this fast growing commodity market. And as we all know, broad competition erodes margins and allows only the lowest cost producer to achieve some profits. In the case of PC this erosion actually pushed out the market creator - IBM - which eventually exited the market and sold its business to Lenovo. The only real winners back then were Microsoft and Intel, who had pivotal differentiating IP. Yes, Intel had a licensor - AMD - but as a licensor, AMD had to pay heavy royalties that impacted its profits, and helped those of Intel.
Both Intel and Microsoft were able to leverage there unique IP into years of growth and became the largest companies in their field.
But being the largest today does not guarantee the tomorrow. Or, as Andy Grove famously said, "only the paranoid survive".
The technology world is about change. While many of the changes are incremental, at times the paradigm changes too. The change that took away Intel’s and Microsoft’s unchallenged market and IP position was the shift to "smart mobile," or mobile internet, as is illustrated in the following chart.
The technology world is about change. While many of the changes are incremental, at times the paradigm changes as well
And with these changes new technology leaders have been emerging: companies such as Apple, Qualcomm, and Google.
To make matters even worse, a small company - ARM - was able to create a disruptive change in the computing engine with its preferred computing architecture, first for 'smart mobile,' then for tablets, and now it seems to penetrate the PC and the server markets.
In my view, as soon as the investment community realized that Intel’s exclusive market and IP position is not relevant to the new market of Mobile Internet, it started to tune down Intel’s P/E. This trend even got stronger as investors became concerned regarding Intel’s position in the PC and server market.
It should be noted that in this context IP is not counted by the number of patents or the amount of trade secrets but rather by the ability to exclude competitors from major markets or extract royalties from those competitors, which may make you a winner even when you loose business. This is a status that Qualcomm and other companies such as SanDisk enjoy.
Economists estimate that two-thirds of the value of large businesses in the U.S. can be traced to intangible assets.
"IP-intensive industries" are estimated to generate 72 percent more value added
(price minus material cost) per employee than "non-IP-intensive industries".
[dubious – discuss
] , as is illustrated by the following chart
So, is the game over for Intel??? Is the Market irrational, or is the Market perceptive?
Some pundits clearly think so, but given its leadership semiconductor technology, strong leading edge manufacturing infrastructure, and balance sheet, it is way too soon to call game over for Intel. But it would seem that Intel needs to introduce some real change in order to correct its course. Perhaps Intel should look back at what Andy Grove’s said and ask itself: does it really act like a paranoid company, or perhaps it is just the inverse.
We at MonolithIC 3D believe that the whole semiconductor industry is about to go through a major disruptive change. After 50 years of successful growth and progress by dimensional scaling, the time has come for a direction change, and the time is now for starting to embrace scaling-up, going for monolithic 3D. The current leaders in dimensional scaling, the NAND Flash vendors, seem to be leading the way. They are pushing ahead with monolithic 3D-NAND. This disruptive change will bring vast new opportunities, and those who will be early to embrace the change may be able to reap the IP reward.
We have a guest contribution today from Ze'ev Wurman, MonolithIC 3D Inc.'s Chief Software Architect. Ze'ev discusses about where is the semiconductor industry heading to.
The semiconductor industry is in the doldrums. The PC market shrinks, Intel shares sink, Applied Materials cuts staff, and even Apple suddenly experiences its share price drop by $100 in a month. Are things really so bad?
But other news seems different. TSMC shares are close to their historical high; Global Foundries leapfrogs TSMC technology and nips at Intel’s heels with 14nm; Samsung reports record quarterly profit. Things seem to be going swimmingly.
Semiconductor business has had its ups and downs since its inception. As demand followed, more and more capacity was put on line, which caused the next overcapacity and slump, inevitably followed by the next spike in demand as the technology inexorably marched down the scaling curve. So, perhaps, nothing is really new here after all.
Yet, perhaps, we should not be so sanguine anymore. We did cope with 193nm light to define our chips down to 20 nm, but at an ever-increasing cost of expensive phase shift masks, immersion lithography, and double exposure. EUV has been talked about for at least 15 years
(following another 15 years of x-ray lithography development fiasco) and has been “late” since at least 2005. Despite the impressive progress shown by ASML, the industry greats – Intel, Samsung, and TSMC --banding around EUV is possibly more a sign of desperation than a strong vote of confidence. The drastic reduction in foundry players – from 20 or so in 90nm to four or less for 14nm has been noticed by many and cannot be good for the long-term health and vitality of the industry.
ASML is the last remaining game in town and, even if it works, building a foundry at over $10B a pop, and developing a technology node at well north of $1B, does wonders at keeping everyone but the most committed (and with deep pockets) out of the game. And the unanswered question is still in place: at what price point will the industry effectively become the domain of the few mass-produced designs such as Apple’s or Samsung’s phones and nothing else?
Clearly pressures have been building up and the industry can’t pretend everything is as usual for much longer. 3D devices has been talked about for decades, yet implementing this dream was considered infeasible until recently. 3D designs are, in a sense, the holy grail of the industry:
- They allow for shrinkage of the average source to destination distances, shrinking power dissipation and improving performance;
- They can include inexpensive built-in fault detection and repair as described here, allowing for as large as needed yielded dies, which cuts further on power by saving on off-chip I/O power;
- They allow cheap and high performance integration of dies with disparate technologies, so advanced (and expensive) logic can be stacked with reduced-cost technology for memory dies, or specialized analog and RF functions;
- They allow the reuse of older fab lines as much of density improvement is achieved through stacking dies rather than shrinking features;
- They allow efficient heat removal without exotic cooling technologies through use of power delivery networks, to be presented in the upcoming IEDM, paper 14.2 ;
In recent years TSVs started to show up. Yet, while TSVs are good for designs that need limited vertical connectivity between disparate sub-systems such as processors with memory, they do not really open the door to a true monolithic 3D design. What true monolithic devices offer is a much higher vertical connectivity, by a factor of up to 10,000, and enable the stacking of multiple dies.
The impact of the increased monolithic vertical integration at lower cost can be dramatic on every electronic market segment. For mobile devices
, the inexpensive integration of analog, RF, and sensors, can lower their cost and power consumption for an even broader market penetration and longer battery life. In medicine
, the footprint of devices is often critical. The availability of camera-in-a-pill, or of implantable medical devices that control drug release, improve hearing, monitor vital signs, or allow artificial vision, are all strongly dependent on heterogeneous device integration in a small footprint and with reduced power. Monolithic 3D is key to transforming the planar and bulky designs of today’s 2D to grain-of-corn and grain-of-rice shape factors that can be inserted for very long time periods into our bodies. Fostering innovation and reducing barriers to entry
of new products are considered crucial for future economic prosperity. FPGAs have been trying to fill this niche since the demise of ASICs, yet they suffer from many handicaps: they are physically large, they are power hungry, and they are available in a limited number of configurations that are often suboptimal for the application. Monolithic 3D technology allows the inexpensive creation of a nearly infinite number of FPGA configurations that can be tailored to every application, as described here
. And it does so while dramatically reducing both the device footprint and power
. Large-scale computing
is facing enormous challenges to reduce its power consumption. Server farms
of the likes of Google, Amazon, or Facebook consume tens and hundreds of megawatts of energy, while the government struggles mightily to keep its planned Exascale supercomputer
under 20MW. Three-dimensional chips can play a large role in reducing power consumption by reducing the interconnect length (and hence, its capacitance), which is responsible for most of the power dissipation in modern chips. Ultra large scale integration with high yields, enabled through 3D repair structures, will further slash the power that today resides in the off-chip drivers. In memory design
, the transition to 3D technology is already taking place as described in our previous blog
. Monolithic 3D structures using crystalline silicon may further the penetration and efficacy of this technology in both non-volatile memory as well as in DRAM.
The semiconductor world will inevitably move to monolithic three-dimensional technologies. The change drivers are already here: the skyrocketing cost of scaled-down lithography, the need to reduce power dissipation, and the need for heterogeneous integration. The only question is how quickly it will move there, and who will be the winners.
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses low temperature cleaving.
Thanks to everybody who came by our booth at SemiconWest SemiconWest 2012
this second year! We really enjoyed talking with you about all the exciting possibilities for new products and processes that are enabled by monolithic 3D IC.
For those who could not make it, here is what our booth looked like:
Nice tie again Zvi! You can still visit us at www.monolithic3d.com
The most common area that you asked us was about low temperature (less than 400°C) bonding and low temperature cleaving processes. The two topics are quite inter-related: One must make the bond stronger than the energy it takes to cleave at the plane you want, rather than cleave at th at fresh bond. In October last year I wrote a blog about the many low temperature bonding techniques and strategies available and their respective bond strengths. Today, I would like to briefly address some of the low temperature cleaving methods available. Generally they involve either a mechanically induced (blade, gas jet, water jet) method, a lower temp thermal (co-implantation, microwave, etc.) cleaving/layer-transfer method, or a combination of both.
Here are a few papers, with some industrial announcements at the end.
One of the earliest methods published is co-implantation by Q.Y. Tong et al
. of Duke University at the 1997 IEEE SOI Conference
. Tong could greatly affect the kinetics of the hydrogen blister formation by co-implantation of Boron. They were able to transfer a 0.4um silicon layer onto a quartz substrate with a 150°C exposure to the quartz by pre-annealing the co-implanted silicon for 10 minutes at 250°C.
Tong with colleagues at the Max-Planck-Institute followed up with more co-implantation
kinetics data in a 2008 Applied Physics Letter. They again demonstrated a 200°C silicon cleave.
In 1998 App. Phys. Lett., Agarwal et al. showed that He implanted with the H could lead to a significant decrease in the total implant fluence (and hence cost) necessary to achieve Si layer transfer. The total implantation dose can be three times smaller than that which is necessary using H alone.
Nguyen et al. of Soitech/CEA-Leti, at the 2003 IEEE SOI Conference showed that He co-implantation could be used to control the kinetics, so time, dose and temperature trades could be made.
Ma, et al. showed in Semcond Sci. Technol. 2006 that a co-implanted cleave has a smoother
surface than a hydrogen-only implanted cleave.
In 2000 App. Phys. Lett., Henttinen et.al showed mechanical cleaving, blade or N2 gas, on low temperature bonded silicon wafers (ox-ox bond). Depending on the H dose, Henttinen could
cleave the silicon wafers at 200°C or 300°C. Henttinen et.al followed up later in 2002 in J. Nucl. Instr. and Meth. in Phys with fundamental mechanistic studies and also demonstrated that with enough B doping one can enable H-implanted layer exfoliation below 200°C.
Cho et al., in 2003 App. Phys. Lett. reported that full wafer layer transfer could be achieved with a mechanical cleave (edge initiated crack propagation) after a 250°C annealing that enabled the bonding strength at the acceptor/donor interface to exceed the required cleave energy at the hydrogen implant plane.
En, et al., of Silicon Genesis, described a room temperature H implant using PLAD (Plasma Immersion Ion Implantation), plasma assisted oxide to oxide bonding, and a room temperature mechanical cleave process at the 1998 IEEE SOI Conference.
Current, et al. of Silicon Genesis, showed a wafer separation tool in MRS 2001 where they utilized a pressurized N2 jet to cleave silicon bonded pairs at room temperature.
Recently from the industrial side: Soitec
announced at SemiconWest 2012
the availability of a room temperature smart cut:
"Soitec’s low-temperature Smart Cut process uses oxide-oxide molecular bonding and atomic-level cleaving to transfer mono-crystalline silicon films as thin as 0.1 micron onto partially or fully processed wafers. On this new material layer, a second level of devices can be processed and this integration can be repeated in an iterative mode. Transferring an extremely thin layer enables higher interconnect density, higher signal throughput and simpler TSV processing. Benefits include increased computing bandwidth, lower overall manufacturing cost, and power savings due to the reduced wiring distance between connected devices. This final benefit is well suited for producing advanced memory or CMOS logic 3D IC systems.” See: http://www.soitec.com/en/news/press-releases/article-346/
SiGen (Silicon Genesis) has tools (some shown above) available that will bond and cleave at or near room temperature: http://www.sigen.net/semi_debondCleave.htmlReferences:
TONG, Q.-Y., et al., "Low Temperature Si Layer Splitting", Proceedings 1997 IEEE International SOI Conference, Oct. 1997, pp. 126-127
TONG, Q.-Y., et al., "A ‘‘smarter-cut’’ approach to low temperature silicon layer transfer", Applied Physics Letters, Vol. 72, No. 1, 5 January 1998, pp. 49-51
AGARWAL, A., et al., "Efficient production of silicon-on-insulator films by co-implantation of He+ with H+'" Applied Physics Letters, vol. 72, no. 9, March 1998, pp. 1086-1088.
NGUYEN, P., et al., "Systematic study of the splitting kinetic of H/He co-implanted substrate", SOI Conference, 2003, pp. 132-134
MA, X., et al., "A high-quality SOI structure fabricated by low-temperature technology with B+/H+ co-implantation and plasma bonding", Semiconductor Science and Technology, Vol., 21, 2006, pp. 959-963
HENTTINEN, K. et al., "Mechanically Induced Si Layer Transfer in Hydrogen-Implanted Si Wafers," Applied Physics Letters, April 24, 2000, p. 2370-2372, Vol. 76, No. 17.
HENTTINEN, K. et al., "Cold ion-cutting of hydrogen implanted Si," J. Nucl. Instr. and Meth. in Phys. Res. B, 2002, pp. 761-766, Vol. 190.
CHO, Y., et al., “Low Temperature Si Layer Transfer by Direct Bonding and Mechanical Ion Cut,” Applied Physics. Letters., vol. 83, no. 18, November 2003, pp. 3827-3829.
EN, W. G., et al., “The Genesis ProcessTM: A New SOI wafer fabrication method”, Proceedings 1998 IEEE International SOI Conference, pp. 163-164 (Oct. 1998).
CURRENT, M. I., et al., “Atomic-layer Cleaving and Non-contact Thinning and Thickening for Fabrication of Laminated electronic and Photonic Materials”, 2001 Materials Research Society Meeting, April 16-20 2001, Paper I8.3.
We have a guest contribution today from Israel Beinglass, the CTO of MonolithIC 3D Inc. Israel was at Applied Materials for almost two decades, and served as Chief Technology Officer and Chief Marketing Officer for many groups there.
Ion-cut, the process used for manufacturing SOI wafers for the past 15 years, is the most popular method to form c-Si layers for monolithic 3D-ICs. In this blog-post, I'll share cost estimates for ion-cut, and explain why even price-sensitive markets such as solar are adopting it.
For monolithic 3D, it is often required to form single crystal silicon above copper wiring layers at temperatures lower than 400C. Fig. 1 shows the ion-cut process, which is the most popular method of achieving this objective. Hydrogen is first implanted into a "top layer wafer" to create a defect plane. This "top layer wafer" is then flipped and bonded onto a "bottom layer wafer" having transistors and copper wiring.After this, the structure is cleaved at the defect plane using a 400C anneal or a sideways mechanical force. Finally, a CMP is done to get a good surface.
The previous paragraph explained how ion-cut can be used for stacking single crystal silicon layers for 3D-ICs. For forming a SOI wafer using ion-cut, the "bottom layer wafer" in Fig. 1 is a blank silicon wafer instead of a processed one with transistors and wires. As many of you know, ion-cut is the standard process used for high-volume manufacturing of SOI wafers today.
Fig. 2 shows cost calculations for ion-cut using a Sematech Cost-of-Ownership framework. Tool prices and throughputs are obtained from equipment manufacturers who provide tools for these ion-cut process steps. The "top layer wafer" in Fig. 1 is re-used, as is typical in an ion-cut process. The total cost per wafer for a single ion-cut is $58, which is close to estimates that ion-cut practitioners in the industry have provided us. The number seems reasonable... this is what you'd expect of a process that doesn't involve any litho steps. In addition, with passage of time, one would expect throughput of various steps to improve significantly, bringing the price down further.
Companies such as Twin Creeks Technologies and SiGen are using ion-cut for the solar industry today (Fig. 3). As you'd know, the solar industry is a lot more cost-sensitive than the semiconductor industry... this application is possible mainly because these vendors are reaching costs similar to Fig. 2.
Hmmm... If the additional cost per wafer is $58, why are SOI wafers considered "costly" today?
This is because of business issues with SOI wafer manufacturing (see Fig. 4).
How do we deal with the business challenges of ion-cut?
- SOI wafer manufacturing is not a free market now: One player, SOITEC, controls 90% of the SOI market today since it owns the basic patent on ion-cut from Michel Bruel. Markets dominated by a single supplier typically have high prices due to lack of competitive pressures.
- This "sole supplier" makes ~80% of its SOI wafers in Europe: Believe it or not, around 80% of SOI wafers are made in Europe today! Its incredibly expensive to have a fab in Europe - that's why all manufacturing is moving to the Far East. A rule of thumb I've heard is that a fab in Taiwan or Singapore is 30-50% cheaper than one in the US or Europe. This is mainly due to government incentives such as tax breaks, lower building costs and lower labor costs. For example, one company I know got a deal from a Far Eastern nation to have a 10 year tax holiday and the government paid 60% of the company's capital expenditure! I also hear SOITEC built its latest fab in Singapore to tackle some of these issues, but that fab only provides only ~20% of its total output now and is running at 10% of its maximum possible capacity. All of us know an under-utilized semiconductor fab is expensive... (Note that some of the numbers in this paragraph are things I heard from industry sources, they are not official estimates)
- Additional player in the supply chain: A company providing SOI wafers today buys a bulk silicon wafer, does the ion-cut process on it and then sells the finished wafer to foundries and IDMs. You're essentially adding an additional player in the supply chain here, with his own margin requirements. Ion-cut manufacturers such as SOITEC have 30% gross margins, so the customer pays extra for this.
- Not enough economies-of-scale: Due to the business constraints listed above, the SOI wafer price overhead is significantly more than the $58 we calculated above. So, SOI adoption has not proceeded as fast as expected, and one cannot reach high enough economies-of-scale. This, in turn, keeps price high compared to bulk Silicon wafers, which hinders adoption. This chicken-and-egg problem (high prices --> low adoption --> not enough economies of scale --> high prices) is a concern.
What's the bottom line?
- Many people in the ion-cut community believe the business situation for ion-cut will change on September 15, 2012. Why? Because the basic patent from Bruel describing ion-cut expires that day. Check out patent number 5374564 at the US Patent Office Website. It talks about all the technologies described in Fig. 1: the atomic species implant, bonding, cleaving with anneal, surface cleans, etc. See Fig. 5 for more details. Once the ion-cut becomes a public-domain technology, we believe a free market situation will arise, benefiting everyone. Competition will lower prices which will boost adoption significantly.
- For Monolithic 3D applications, we feel the best way forward is for each company (eg. TSMC, Intel, ST, Toshiba, Fujitsu, Samsung, Micron, etc) to do the ion-cut in-house. So, these companies would place equipment for H implant, bond and cleave in their own fabs and run this process themselves. This will keep costs down since the problems described in Fig. 4 can be avoided, and this will be possible after 2012. One could approach the $58 price per ion-cut that I showed in Fig. 2.
The price per ion-cut could be as low as $58, which is miniscule compared to wafer cost of a logic wafer (~$4000), NAND flash memory wafer (~$1500) or DRAM wafer (~$2000). This is encouraging for the monolithic 3D application, since ion-cut is the most popular technique to get stacked single crystal silicon layers. Once these stacked single crystal silicon layers are obtained, one can use MonolithIC 3D Inc.'s innovative device architectures to build high-quality 3D chips.