"Innovations for Next Generation Scaling"
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses The Common Platform Technology Forum 2013.
The 2013 Forum today (Feb 5, 2013) started with a presentation by Dr. Gary Patton, VP, IBM Semiconductor Research & Development Center. Gary very clearly articulated the two irresolvable challenges the industry now faces:
- On chip interconnect
These two challenges connect very well with our recent blog IEDM 2012 - The Pivotal Point for Monolithic 3D IC
. Gary showed both the exponential increase of RC which results from the dimensional scaling of copper below 100nm width and the high cost associated with double and quad patterning. In addition, he showed how the extreme scaling of the copper metallization creates reliability challenges such as fatal EM modes, and scaling of the insulator k breeds TDDB and strength issues. As a reminder, in the recent IEDM (Dec. 2012) short course, IBM presented the following slide indicating that interconnect now dominates device power!
L. Chang, D.J. Frank - IEDM 2012 Short Course – IBM Watson Research Center
Gary also presented a multi-decade past to future slide that resembles the one presented here below. The decade ending at the year 2000 was the good old days of easy scaling of planar transistor, which he called the gate oxide limit. Then the industry followed with a decade of "Material Innovation" that he called the planar device limit, and starting in 2010 is the beginning of the "3D Era" - 3D transistors and stacked devices.
Finally he shared with us his vision of 3D devices with three planes of devices:
- Logic Plane
- Memory Plane
- Photonic Plane
A vision we mutually share.
Now, here is my failure to understand. As a company who has been in the forefront of 3D and TSV research, IBM is well aware of the severe limitations of TSV as an alternative for vertical interconnect. The following cross-sectional picture by IBM, presented at the recent GSA Summit, clearly illustrates how large a TSV is in comparison to an interconnect via.
IBM Systems and Technology Group – GSA Silicon Summit 2012 (S.s lyer) – 2012 IBM Corporation
With TSVs of 5 micron diameters (and pitches of 15 micron due to keep out zones from stress issues) vs. vias of less than 50 nm, the ratio in vertical connectivity is 1:10,000 as illustrated in the following chart by Perinne Batude of CEA Leti.
Clearly IBM technologists are well aware of the many research papers showing that TSVs, with their relatively huge size compared to all the other on-chip elements, diminish the performance or power benefits in folding designs to 3D. For example, the chart below was presented by Kim at the 2011 IEEE International Interconnect Technology Conference. The chart illustrates the performance benefits of folding a design twice (4 tiers of transistors) as dependent on the via size. At a via size of 5 microns there are actually no benefits, while at a via size of 0.1 micron the benefits are the equivalent of two nodes of dimension scaling!!!
So can someone please explain to me how come IBM is still talking about TSV as if it is the only representative of the "3D Era"???
And particularly now, when monolithic 3D is finally practical, and the NAND Flash memory vendors are adopting it across the board!?
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses The Pivotal Point for Monolithic 3D IC.
From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here’s why:
We start with the EE Times article IEDM goes deep on 3-D circuits
, starting with "Continuing on the theme of 3-D circuit technology addressed in an earlier post
about this year’s International Electron Device Meeting, Rambus, Stanford University and an interesting company called Monolithic 3D will address issues related to cooling 3-D circuits. .." and follow with a quote from the abstract to IEDMs short course "Emerging Technologies for post 14nm CMOS
" organized by Wilfried Haensch, of IBM’s Watson Research Center:
"Scaling the dimension was the key for the unprecedented success of the development of IC circuits for the last several decades. It now becomes apparent that scaling will become increasingly difficult due to fundamental physical limits that we are approaching with respect to power and performance trade-offs. This short course will give an overview of several aspects in this “end-of-scaling” scenario. ..."
"Yet there are a variety of developments in another type of 3-D scaling that are likely to have a similarly large impact on semiconductors in the near future - 3-D devices for NAND flash.... And as in planar CMOS logic, NAND flash technology has been progressively scaled to smaller feature sizes, becoming the process leader in driving the smallest line-widths in manufacturing as evidenced by the current 1x-nm (~19-nm) process node. Yet, despite plans to scale down to the 1y-nm (~15-nm) and possibly 1z-nm (~13-nm) nodes, the traditional planar floating gate NAND flash architecture is approaching the scaling limit, prompting the search for new device architectures. Not to be upstaged by the planar to 3-D (FinFET) transition in logic devices, NAND flash has embarked on its own 3-D scaling program, whereby the stacking of bit cells allows continuous cost-per-bit scaling while relaxing the lateral feature size scaling."
In our recent blog 3D NAND Opens the Door for Monolithic 3D
we discussed in detail the adoption of monolithic 3D for the next generations of NAND Flash. The trend was very popular subject of this year’s IEDM and is nicely illustrated by this older chart:
And accordingly the updated ITRS 2012 present the change from dimension scaling to monolithic 3D scaling as presented in the following slide.
This year’s IEDM brought up two of the driving forces behind the shift from dimensional scaling to monolithic 3D IC scaling, that we will detail below as #1 and #2.The Current 2D-IC is Facing Escalating Challenges:
- On-chip interconnect (#1)
- Dominates device power consumption
- Dominates device performance
- Penalizes device size and cost
- Dominates Fab cost
- Dominates device cost and diminishes scaling benefits
- Dominates device yield
- Dominates IC development costs
The problem with on-chip interconnect didn’t start today. This vintage Synopsys slide below clearly indicates that on-chip interconnect started to dominate overall device performance a decade ago:
In response, the industry has spent an enormous amount of money to convert from aluminum to copper and to low-K inter-metal dielectrics. But now, we have very few additional options left (perhaps air-bridge?) as illustrated by the following chart:
It shows that neither Carbon Nano Tube (CNT) nor Optical interconnect are better than copper, and that monolithic 3D still is the best path.
The practiced ‘band-aid’ fix so far has been throwing more transistors (they are getting cheaper, right? No longer. See father below) at the problem in the form of buffer and repeaters. But as we scale down we need exponentially more of these ban-aids as illustrated by the following:
"The 14 nanometer node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design. On December 11, 2012, Applied Materials, Inc. will host an important forum in San Francisco to explore the path that interconnect technology must take to keep pace with transistor scaling and the transition to new 3D architectures.” (emphasis added)
This had been illustrated before in the following chart
And to make it crystal clear, IBM presented the following chart in its short course:
Power is now dominating IC design and clearly dimensional scaling does not improve the interconnect’s impact – see the following chart built from the ITRS Roadmap. The only effective path forward that addresses interconnect is monolithic 3D.
As for the second challenge – lithography – we start again with an old chart by Synopsys:
The implication is that any new node of dimensional scaling comes with escalating lithography costs; and sure enough, that’s what is happening. When litho costs are plotted over time, it fits a log-linear scale….this is not a sustainable trend.
The following chart illustrate the lithography escalating cost of equipment which directly reflect the wafer cost.
This resulted in the following slide by IBM at the GSA Silicon Summit 2012:
Quoting from the slide: "Net: neither per wafer nor per gate [are] showing historical cost reduction trends"
Another EE Times IEDM12 article covering a keynote given by Luc van den Hove, chief executive of IMEC, IEDM: Moore’s Law seen hitting big bump at 14 nm
, repeats the same conclusion. In fact, some vendors are already changing course accordingly. GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium (11 December, 2012) during IEDM12 week also acknowledged that their 14nm node will have a 20nm node metal pitch, and, just like GlobalFoundries, a similar die size and increase in per-transistor cost. So it would seem that also for lithographic reasons, the industry’s next generation path, and the continuation of Moore's Law, would be achieved by leveraging the third dimension.
Now that monolithic 3D is feasible and practical, the time has come to move in this new direction, as has been nicely illustrated by this concluding chart below
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology & IP. Brian discusses how can heat be removed from 3D-IC Stacks.
Thanks to everybody who came to IEDM
this year, and especially to those I met and who came to paper 14.2, delivered by Hai Wei
University. You can find the meeting paper and slides here
One of the big challenges facing 3D-IC is how to remove the heat dissipated on the upper layers to keep a high performance chip temperature within the system and reliability constraints and prevent hot spots. Most existing proposed techniques rely on arrays of TSVs and thick (xxum) silicon layer to conduct and spread the heat laterally and vertically. We propose that properly designed PDNs* (Power Delivery Networks) can significantly contribute to heat removal in both parallel (think TSV and xx um thick Si layers) and monolithic/sequential (think 100nm Si layer) 3D-ICs.
We investigated both parallel and monolithic in the paper. Here, I will, of course, focus more on the monolithic challenges and solutions, but I will make some important comparisons to parallel at the end.
Since the 130nm node, we have entered an era in our industry where we are not only using new materials, but also new device structures. I have written previously
about the risk associated with this, and (hopefully…) made a case for monolithic 3D technology being the best way for the industry to move forward, still enjoying Moore’s Law type economics (i.e., lower cost) but with a much lower development risk.
Life is getting thin and narrow in our business….so, how best to take advantage of this nanometer and angstrom era and avoid the economic (think EUV at 110+M$ a pop, or double/quad patterning) and atomistic (think 7 nm) brick walls coming? Monolithic 3D stacking technology is the answer: keeping the next evolutionary step of our industry in the wafer fab
, where the batch economics of the silicon wafer can be enjoyed, and avoiding the costly piece-part assembly processes of TSVs.
One of the basic tenets of monolithic 3D is the ability to have thin (preferably monocrystalline) silicon layers that enable very small vertical interconnect manufacturing, and hence a large (>1 million/cm2) layer to layer vertical interconnect density in the stack. This opens up the possibility for powerful new architectures and devices, such as Amdahl’s wafer scale computer (see blog
) and cost effective MLC 3D memories
Two implications arise from the thin (on the order of 100nm or less) silicon layer stacking. First, that fully depleted (FD) devices, and hence silicon islands floating in an insulator such as silicon dioxide, will be the norm. Second, taking full advantage of a manufacturable aspect ratio etching (5:1 to 10:1), we will end up with a large density of very small layer to layer vias (of 1-2 lambda diameter), where vertical interconnect density rivals the horizontal density of interconnect that we have enjoyed thru the many cycles of Dennard
scaling. FD devices are soon to be the norm in 2DICs; for example, the thin UTBBOX
of STMicro/GlobalFoundries and the narrow FinFets
(incidentally, at IEDM12, Intel was criticized for doping the fins…).
Both of these implications, FD devices in islands of Si and very dense vertical interconnect, play a significant role in how we propose to solve a major challenge in 3D stacking.
Since the stacked layers are not in direct contact with the heat sink: How do we get the heat out of the stacked layers???
In short, the answer is to take the heat out of each silicon island with the power delivery network, move it laterally in the metal interconnect of that stack layer (just as if
we had a thick silicon layer underneath), and then vertically move the heat to the heat sink with that large density of interlayer vias (which we can now make due to the thin stacked layer being very thin).
Here’s a picture of what we are doing:
Sounds at least plausible, right?
Well, that’s what we set out to show, with the heavy lifting done by our friends at Stanford. Hai Wei & Tony Wu of Professor Subhasish Mitra's group
, Professor Mitra, and Professor Fabian Pease
, were the drivers in creating the simulation approach and engine to see if this works as we thought it might. It did, and then ended up developing a tool that may be very useful for future 3DIC design work.
Hai and Tony describe in the paper and the presentation the details of the simulation approach, engine, assumptions, and methodologies developed. Quite a nice piece of work! They have built an analysis framework that can be adapted for exploring technology-circuit-application interactions for a wide variety of 3D technologies, cooling options, and PDN designs. Types of 3DIC
technologies modeled are conventional TSVs
, called parallel 3D integration by many in the industry, and monolithic 3D integration, a type of sequential 3D integration. Cooling options range from conventional air cooling of the heat sink (2 W/K·
cm2) to external liquid cooling (10 W/K·
cm2) for high power systems. PDN designs studied ILV densities from 0 to 4 million/cm2.
That said, what are the essential takeaways?
First, the cooling benefits of PDNs are essential to achieve monolithic 3D integration. Without accounting for PDNs in the 3DIC thermal model, it will be next to impossible to achieve the desirable thermal characteristics and result of a 3D IC stack. Further, the density of ILVs is important to achieving the system thermal constraint. In the 100nm thick Si example below, the desired maximum chip temperature is 85°C or less.
Second, a processor can be effectively cooled, with no hot spots, using PDNs in a monolithic 3D configuration. Hai and Tony’s thermal analyses of core-on-core and memory-on-core designs, utilizing the OpenSPARC T1
industrial multi-core design operating running an 8-threaded program that solves the Black-Scholes
application (i.e., hot), showed significant improvement and no hot spots. The top silicon layer is 100nm thick and the hottest parts of the chips were operating at 138 W/cm2. Those hottest parts, the EXU units, were stacked directly on top of each other to show the worst case.
Combining these two seems to indicate that no PDN in the model versus designing and optimizing with thermal-aware PDNs makes the difference between being able to run the design (processor on processor in this example) at only 1/3 of the full power density or at a full power.
That’s the essential take-away for monolithic. Mimic the lateral heat conduction of thick silicon with the PDNs of the thin silicon stack layer, and then get that heat vertically to the heat sink with the dense network of vias provided by the monolithic 3D integration.
For the parallel 3D integration case, the 5um thick silicon greatly helps with the lateral heat conduction to the TSVs. With a properly designed PDN; however, there can be a significant savings in the number of TSVs (ILVs on chart below) used to vertically conduct the heat away, and thus offers a significant area savings by eliminating many of those big TSVs and Keep Out Zones (KOZs). (Note: for both the parallel and monolithic cases, Hai made the KOZ twice the ILV diameter as a conservative choice)
Moreover, by use of a properly designed PDN and an optimized density of TSVs, the maximum power density of the top layer in can be increased considerably …. from 35 to 50 W/cm2 for the parallel 3D case.
It is worth noting an important point from these graphs: At the optimum design point, where the density of ILVs coupled to the PDN satisfies the desired 50W/cm2 max allowed power density, the required number of TSVs to effectively conduct the heat costs about 3% of the chip area. For the monolithic case, the chip area cost is about half that.
A high density of small vias not only makes possible some powerful product architectures such as logic-cone level redundancy, but is also key to producing area efficient vertical heat conduction networks.
*Patent Pending technology
We have a guest contribution from Zvi Or-Bach, the President and CEO of MonolithIC 3D Inc. Zvi discusses about Qualcomm overtaking Intel in market capitalization.
On Nov 9, 2012 we learned that Qualcomm overtook Intel in market capitalization. Quite shocking news if one considers that Intel’s revenue is almost three times that of Qualcomm and its net margin is more than twice that of Qualcomm. Clearly investors evaluate Qualcomm using a different scale than what they use for Intel, as is evidenced by Qualcomm’s P/E of 20.12 vs. Intel's mere 9.07. EE Times explained it in an article that day stating: "In the eyes of investors who have driven up its market capitalization, the fact that Qualcomm is a fabless company relieves it of the burden of having to invest billions of dollars each year in process development and wafer fabs." However, given that TSMC, a pure foundry, has a P/E of 15.67, it behooves us to look for another explanation. It’s also worth noting that TSMC had a revenue growth of 2% in the last year, far less than Intel's 25.6%, and its net income actually went down vs. a net income growth by Intel of 213%!
My explanation is that it is all about IP strength. I will expand on it in the rest of this blog but as prime evidence I offer SanDisk, who sports a P/E of 20.78 yet has continued to invest heavily, together with its partner Toshiba, in fab capacity upgrades.
Let’s first look at the previous two decades as Intel grew consistently year after year while riding the PC business growth. During those years the team Intel + Microsoft was the exclusive vendor in the PC 'game'. All others had to compete neck to neck in this fast growing commodity market. And as we all know, broad competition erodes margins and allows only the lowest cost producer to achieve some profits. In the case of PC this erosion actually pushed out the market creator - IBM - which eventually exited the market and sold its business to Lenovo. The only real winners back then were Microsoft and Intel, who had pivotal differentiating IP. Yes, Intel had a licensor - AMD - but as a licensor, AMD had to pay heavy royalties that impacted its profits, and helped those of Intel.
Both Intel and Microsoft were able to leverage there unique IP into years of growth and became the largest companies in their field.
But being the largest today does not guarantee the tomorrow. Or, as Andy Grove famously said, "only the paranoid survive".
The technology world is about change. While many of the changes are incremental, at times the paradigm changes too. The change that took away Intel’s and Microsoft’s unchallenged market and IP position was the shift to "smart mobile," or mobile internet, as is illustrated in the following chart.
The technology world is about change. While many of the changes are incremental, at times the paradigm changes as well
And with these changes new technology leaders have been emerging: companies such as Apple, Qualcomm, and Google.
To make matters even worse, a small company - ARM - was able to create a disruptive change in the computing engine with its preferred computing architecture, first for 'smart mobile,' then for tablets, and now it seems to penetrate the PC and the server markets.
In my view, as soon as the investment community realized that Intel’s exclusive market and IP position is not relevant to the new market of Mobile Internet, it started to tune down Intel’s P/E. This trend even got stronger as investors became concerned regarding Intel’s position in the PC and server market.
It should be noted that in this context IP is not counted by the number of patents or the amount of trade secrets but rather by the ability to exclude competitors from major markets or extract royalties from those competitors, which may make you a winner even when you loose business. This is a status that Qualcomm and other companies such as SanDisk enjoy.
Economists estimate that two-thirds of the value of large businesses in the U.S. can be traced to intangible assets.
"IP-intensive industries" are estimated to generate 72 percent more value added
(price minus material cost) per employee than "non-IP-intensive industries".
[dubious – discuss
] , as is illustrated by the following chart
So, is the game over for Intel??? Is the Market irrational, or is the Market perceptive?
Some pundits clearly think so, but given its leadership semiconductor technology, strong leading edge manufacturing infrastructure, and balance sheet, it is way too soon to call game over for Intel. But it would seem that Intel needs to introduce some real change in order to correct its course. Perhaps Intel should look back at what Andy Grove’s said and ask itself: does it really act like a paranoid company, or perhaps it is just the inverse.
We at MonolithIC 3D believe that the whole semiconductor industry is about to go through a major disruptive change. After 50 years of successful growth and progress by dimensional scaling, the time has come for a direction change, and the time is now for starting to embrace scaling-up, going for monolithic 3D. The current leaders in dimensional scaling, the NAND Flash vendors, seem to be leading the way. They are pushing ahead with monolithic 3D-NAND. This disruptive change will bring vast new opportunities, and those who will be early to embrace the change may be able to reap the IP reward.
Samsung contributes just 7% to the world’s foundry revenue today. But here’s why it could be TSMC’s biggest challenge yet...
Most people will agree that Andy Grove has been the semiconductor industry's most successful CEO. After co-founding Intel and serving as COO for many years, he took over the CEO role and oversaw a 2400% increase in the company’s stock price. Among the present set of semiconductor CEOs, does anyone possess Grove’s high levels of performance, dynamism and vision? There can be only one answer: Morris Chang, the founder and CEO of TSMC.
I’m sure many of you have read Andy Grove’s classic book, “Only the Paranoid Survive”. Let’s now apply the principles in Grove’s book to the foundry industry. If you were Morris Chang and had 50% market share in the foundry industry, which competitor of yours would you be “paranoid” about?
Figure 1: Foundry Revenue in 2011 (Source: SemiMD).
Fig. 1 shows the foundry landscape at the end of 2011. Many competitors show up: there’s Globalfoundries with its plentiful oil money, UMC with its excellent customer service and high yields and SMIC with its Chinese government backing. But, to me, Samsung is undoubtedly the biggest threat to TSMC, even though its foundry market share today is just 7%. Let me explain why... Economies of Scale due to Memory Business
Semiconductor manufacturing costs are heavily dependent on economies of scale. Fig. 2 
, which is an estimate of DRAM costs and selling prices in 2003, illustrates this point. The highest volume producer, Samsung, has the lowest raw material costs in Fig. 2. The same goes for semiconductor equipment purchases. A higher volume producer gets a lower price per tool. You’ll notice the highest volume producer (Samsung) has the lowest depreciation cost in Fig. 2.
Figure 2: DRAM industry landscape in 2003. Costs are a function of production volumes. (Source: 
What does this mean for the foundry industry? Well, TSMC, since it has 50% market share, should benefit from economies of scale and build a lead over its rivals, right? That certainly gives TSMC an advantage over UMC and Globalfoundries, but doesn’t work with Samsung. Why? Because Samsung owns a huge chunk of the world’s memory business (~40%). It buys tools and raw materials in huge volumes for those markets, and you use pretty similar tools and raw materials for logic foundry manufacturing. Fig. 3 illustrates that Samsung’s capital expenditure for tools in 2012 is actually double that of TSMC. Samsung might therefore have lower raw material costs and depreciation costs than TSMC.
Figure 3: Samsung buys more semiconductor equipment than TSMC (numbers shown for 2012). Scale of equipment buying provides low prices. (Source: SemiMD)
Yield improvement methodologies
Samsung has a great set of yield improvement methodologies developed over its years in the competitive memory industry. Fig. 5 
illustrates yields of different DRAM manufacturers in 2003. You’ll notice Samsung has, by far, the best yields. Based on this data and Samsung’s reputation for high-yield memory products, you would expect Samsung to get good yields in the logic foundry business. They seem to be delivering on that front. I hear from industry contacts that Samsung is the only manufacturer getting reasonable yields for gate-first high k metal gate products at 28nm.
Figure 4: Samsung’s yield enhancement methodologies gave it an advantage over competitors in the memory industry. (Source: 
Low cost fabs
In cost sensitive markets such as memory and foundries, the location of a fab makes a difference. Fig. 5 
shows a chart from the US National Academy of Engineering which reveals that fab costs in the US are ~25% higher than fab costs in the Far East. Some of TSMC’s competitors have fabs in Europe and the US, but Samsung is building a good portion of its capacity in Korea (they do have one facility in Texas though). The fab cost advantage TSMC has over its other competitors doesn’t necessarily exist with Samsung.
Figure 5: Cost of US fabs higher than those in Korea, Taiwan or Singapore. (Source: 
Sensible partnership strategy
One of the barriers to entry for the foundry business is availability of Intellectual property (IP) blocks and CAD tool support. Intel, which is looking to enter the foundry business, has difficulties with this, since IP blocks haven’t been developed for its technologies yet. SoC makers today show a marked preference for foundries offering competitive IP blocks at low prices.
When Samsung entered the foundry industry, it addressed this issue by joining the IBM alliance, and so its customers could use IP blocks developed for the IBM alliance. Samsung did not have much experience developing logic technologies either, and the alliance helped Samsung learn from existing players in the logic business such as IBM and Globalfoundries. In spite of having a similar technology offering to Globalfoundries and IBM, Samsung retains an advantage over these competitors since it is better at ramping up yields and because it has low cost fabs.
R&D costs for next-generation logic technologies are $1-2 billion today. Sharing the cost with IBM and Globalfoundries gives Samsung a R&D cost advantage over companies such as TSMC and UMC which develop new technologies alone. Ability to fund large capital expenditures
TSMC, UMC, Globalfoundries and SMIC derive almost all their sales from the foundry industry. This limits the amount of capacity they can add every year, since their balance sheets place restrictions on maximum cap-ex to revenue ratio (Globalfoundries is an exception here due to its oil money). Samsung, on the other hand, is a diversified company that sells everything from TVs to DRAM to NAND flash to cell phones. It routinely takes profits from other divisions and invests it in the logic foundry industry. Fig. 6 
illustrates this trend. Samsung’s capex to revenue ratio for its foundry business is way higher than anyone else. This added capacity is helping Samsung’s foundry business grow rapidly – notice how Samsung’s froundry revenues increased almost 7x between 2010 and 2012. Samsung used this “capacity-add-like-there-is-no-tomorrow” strategy to become our industry’s biggest DRAM producer, so the foundry folks had better watch out!
Figure 6: Samsung has the highest cap-ex to revenue ratio among all foundries. (Source: SemiMD)
Proven Research Expertise
If you talk with engineering folks in our industry and ask them which companies do the best research, you will find Samsung near the top of the list. Let me illustrate Samsung’s research capabilities using Monolithic 3D as an example. They started working on the technology almost 10 years back, and have developed monolithic 3D technologies for NAND flash, SRAM and resistive memories. In addition, their roadmap calls for commercialization of Monolithic 3D NAND flash memories within 2 years. Check out Fig. 7. This is some of the best work I’ve seen on monolithic 3D so far. This phenomenal research capability will help Samsung make strides in the logic space.
Figure 7: Samsung has a long history of developing monolithic 3D technologies.
While the above capabilities of Samsung threaten TSMC in the long term, there are stormy clouds looming for Samsung in the short term. Apple, which accounts for more than 75% of Samsung’s foundry revenues 
today, is flirting with TSMC due to its increasingly litigious competition with Samsung in the mobile space. If TSMC executes well and takes this business away from Samsung, it could be a big blow to Samsung’s ambitions. To summarize
I explained why I believe Morris Chang will consider Samsung his biggest competitor in the long-term. The economies of scale Samsung has due to its memory business could help its logic operations. Samsung’s superb yield ramp capabilities and low cost Korean fabs are another key asset. Probably the biggest weapon Samsung has is its conglomerate (chaebol
) structure, which allows it to make huge capital investments and grow rapidly.
At the start of this write-up, I talked about how Morris Chang has grown TSMC the way Andy Grove grew Intel. One of Andy Grove’s strengths was that he recognized Intel’s biggest challenges, and channelized his “paranoia” and limitless energy into finding counter-measures. What can Morris Chang do to deal with “the Samsung challenge”? In a future blog post, I will describe strategies for this... stay tuned! - Post by Deepak Sekar
Today, we'll discuss why TSV pitches smaller than 500nm are useful and how one can achieve that. Evolutionary advances with today's TSV technology as well as radically new monolithic 3D approaches are options.
The Silicon Valley IEEE Components, Packaging and Manufacturing Technology (CPMT) Society invited me to give a talk on "Fine-Grain 3D Integration" last week. In case you're not familiar with this IEEE chapter, they host speakers from around the Valley periodically. Check out their website
if you get a chance - they have some nice talks lined up for the future. Now, let me describe the stuff I presented there. IntroductionAs many of you know, 3D technologies in the marketplace today have huge TSVs. For example, TSMC's 28nm technology has 6um diameter TSVs with 5um keep-out zone. Other manufacturers are offering similar TSV sizes too. When you start comparing these with on-chip feature sizes (28nm), you'll understand why I use the term "huge" to describe these TSVs. In contrast, fine-grain 3D technologies are defined as those having TSV pitches smaller than 500nm
. Why Fine-Grain 3D Integration?There are many applications that benefit from small TSV sizes. Fig. 1 describes the basic motivation - wires consume a lot more energy than transistor-based computation today, and 3D can reduce lengths of these wires. Micron-scale TSVs
can reduce chip-to-chip wire lengths, but smaller TSVs are needed to reduce on-chip wire lengths.
Figure 1: Situation in nVIDIA's 28nm chips.
Below are some uses for fine-grain 3D. Note that small TSV sizes (around minimum feature size) are required for some of these applications:
Limitations of today's TSV technologyLike many engineers, I believe understanding a problem is important for figuring out a solution. So, let's analyze why today's TSVs are so fat. Fig. 2 shows a typical process for high-density 3D-ICs.
- Short on-chip wires in logic cores and SoCs: Components within a single logic chip can be stacked atop each other to shorten on-chip wires. This leads to smaller gates, since these gates need to drive less wire capacitance. The result is reduced power and die size. Analyses show that a 2x reduction in power, a 2x reduction in silicon area and a 4x reduction in chip footprint may be possible by doubling the number of 3D stacked layers (link).
- Logic-SRAM stacking: The requirements of logic devices and SRAM on a chip are very different today. SRAM circuits typically require just 4 metal levels compared to 12 for logic circuits. SRAM transistors have different channel length, oxide thickness and threshold voltage compared to logic transistors too. In this scenario, it makes sense to stack SRAM and logic in 3D. The SRAM layer can be optimized for 4 metal levels and SRAM-type transistors, thereby saving cost.
- nMOS and pMOS stacking: Today's nMOS and pMOS transistors have different gate stacks, strain layers, implants and wells. Separate lithography steps are required for all of these. To save cost, one could stack the nMOS and pMOS atop each other. This reduces standard cell area too. Analysis from IBM shows that 30-40% reduction in standard cell area is possible for inverters, NAND and NOR cells by stacking nMOS and pMOS layers atop one another. Smaller standard cells result in shorter wires, improving power and performance.
Figure 2: Process flow for a bumpless bonded 3D TSV technology.
The limiting steps for TSV size in these face-to-back bonded technologies are: Step 5: Wafer thinning
- Aspect ratio limitations of TSV manufacturing processes nowadays are around 10:1. To get 1um diameter TSVs, one needs to have a 10um thick silicon layer. For this scenario, during the thinning step, a 775um thick wafer needs to be thinned down to 10um +/- 1um (10% tolerance). This 1um tolerance is very hard to achieve at high throughput. Many manufacturers take the easy way out and thin the silicon wafer from 775um to 50um +/- 5um (10% tolerance). For an aspect ratio of 10:1, a 50um silicon thickness will lead to 5um diameter TSVs. Step 7: Wafer alignment
- In this step, the top and bottom layers are aligned with each other and bonded. Misalignment occurs due to several reasons
- 3D align and bond tools on the market often do not have the stable alignment stages and image capture/storage required for sub-500nm pitch TSVs.
- Co-efficient of thermal expansion (CTE) mismatch between the top and bottom layers, wafer bow, thermal and stress induced flow of temporary bonding adhesives, localized bonding imperfections and other issues can cause um-scale misalignment.
Evolutionary Improvement of Today's TSV Technologies
In this section, I will summarize evolutionary ways to improve today's TSV technologies. IBM and MIT Lincoln Labs are the pioneers in this area, as are image sensor makers such as Sony and Omnivision.
Wafer thinning techniques - Fig. 3 shows approaches to reduce wafer thickness from 775um to less than 1um. The method in Fig. 3(a) works for SOI wafers. Buried oxide layers of SOI wafers are used as etch stops to get low silicon thickness with sufficient precision. An alternative approach for bulk silicon wafers is shown in Fig. 3(b). Silicon etch solutions such as EDP have orders of magnitude lower etch rates for p++ silicon compared to p silicon. One could therefore use a p++ layer in a silicon wafer as an etch stop. Both these techniques are starting to be used in manufacture of back-side illuminated image sensors.
Figure 3: Next generation wafer thinning technologies that use etch stop layers.
Techniques to improve alignment accuracy
- For high density TSVs, companies prefer to use glass carrier wafers at present. The transparency of glass, combined with low silicon thickness of transferred films, allows one to look through the top wafer and align. Limitations of 3D alignment tools can be overcome with this technique. In addition, if glass carrier wafers are used, adhesives for attaching silicon to a carrier wafer can be optically debondable. Optically debondable adhesives are more stable at the high temperatures needed for bumpless bonding.
Besides using glass carriers, one could do a few more things:
- Use CTE matched carrier wafers - Even if you use borosilicate glass with an excellent CTE match with Si, a small CTE mismatch is introduced at bond temperatures. For example, at 300C, silicon wafer diameter can increase by 314um while borosilicate glass diameter can increase by 264um. This difference in diameter can introduce alignment error. If you want to get sub-500nm pitch, costlier glasses that have CTE-match with silicon at various temperatures are required (Fig. 4(a)).
- Use oxide-to-oxide bonding - For fine-grain 3D, oxide-to-oxide bonding is the technique of choice due to the low temperatures involved vs. Cu-Cu bonding. Lower temperatures reduce CTE mismatch errors. In an oxide-to-oxide bonding process, a weak bond is formed at room temperature. Following this, a post-bond anneal (~300C) is done to get a stronger bond. The alignment got at room temperature is largely maintained. Less than 400nm misalignment is introduced by the post-bond anneal (Fig. 4(b)).
- Use wafer bow compensation - Wafers can frequently have bow of 50-100um, making sub-micron alignment accuracy difficult while bonding. IBM and MIT have developed wafer bow compensation schemes to reduce this. For example, one could deposit thin films on back sides of wafers to compensate partially for the wafer bow. See Fig. 4(c).
Click to enlarge.
Figure 4(a)-(c) from left to right: (a) CTE match of various glasses with silicon. (b) Change of alignment after post-bond anneal. (c) Wafer bow compensation schemes.
IBM built prototypes utilizing many of these techniques. SOI wafers and buried oxide etch stop layers enabled transfer of thin silicon. CTE-matched borofloat glass carriers, oxide-to-oxide bonding and wafer bow compensation schemes were used. IBM's best prototypes had a TSV pitch of 6.7um, and they said 2um pitch would be possible when bonders with sub-0.5um alignment accuracy are available (which is the case today). Essentially, we can reduce TSV pitches from the 20um we get in the marketplace today to around 2um. I believe it may be possible to lower TSV pitches to less than 500nm by improving processes further. Please see slides of my talk for details.The Monolithic 3D PathWith monolithic 3D
technology, additional transistor layers are constructed monolithically atop Cu/low k layers. This could lead to TSV size close to minimum feature size, which is needed for many of the fine-grain 3D applications described above.
Fig. 5 indicates the main barrier to creating high-quality transistors at Cu/low k compatible temperatures (sub-400C) is dopant activation.
Figure 5: Steps required for constructing a silicon transistor.
Fig. 6 describes one approach to overcome this problem, which utilizes recessed channel transistors. These have been used in DRAM manufacturing since the 90nm node, and are known to be competitive with standard planar transistors
. As can be seen in Fig. 6, high temperature dopant activation steps are conducted before transferring bilayer n+/p silicon layers atop Cu/low k using ion-cut
. For ion-cut, hydrogen is implanted into a wafer at a certain depth creating a defect plane. Following this, the wafer is bonded to the bottom device layer using oxide-to-oxide bonding. The bonded structure can now be cleaved at the hydrogen plane using a 400C anneal or a sideways mechanical force. CMP is done to planarize the transferred surface. Transferred layers are unpatterned, therefore no misalignment issues occur while bonding. Following bonding, sub-400C etch and deposition steps are used to define the recessed channel transistor. This is enabled by the unique structure of the device. These transistor definition steps can use alignment marks of the bottom Cu/low k stack since transferred silicon films are thin (usually sub-100nm) and transparent. Minimum feature size through-silicon connections can be produced due to the excellent alignment.
Figure 6: (a) A recessed channel transistor (b) Process flow for monolithic 3D logic. Bottom device layer with Cu/low k does not see more than 400C. Through-silicon connections can be close to minimum feature size due to the thin-film process.
A few points about Fig. 6: (i) All materials, process steps and device structures are well-known and are used in high-volume manufacturing (ii) The original donor wafer with n+ and p layers can be reused after layer transfer. This is an advantage over today's TSV processes, where one spends time and cost etching away a 300mm wafer that costs $120. (iii) Though-silicon via connections are minimum feature size, enabling large improvements (As described previously, benefits can be 2x lower power, 2x lower silicon area by doubling the number of device layers. nMOS and pMOS stacking is possible.) The main risk is the use of DRAM-type recessed channel transistors in logic technologies. My somewhat biased view is that recessed channel transistors have been used in DRAM manufacturing since the 80nm node, so they may not be difficult for logic manufacturers to bring up and make competitive (especially for low-power applications).
Anyway, it is time to sign off now. If you are at the IEEE 3D System Integration Conference in Japan next week, don't forget to attend MonolithIC 3D Inc.'s presentation. I will be giving an invited talk titled "Monolithic 3D-ICs with Single Crystal Silicon Layers".
Disclosure: I work at MonolithIC 3D Inc., a company developing monolithic 3D technologies. I have tried to be as unbiased as possible while describing 3D-TSV and monolithic 3D technologies. However, if you disagree with something written in this blog post, please let me know in the comments section. I would welcome the discussion. Thank you.- Post by Deepak Sekar
In today's blog post, we'll look at TSV sizes for TSMC, IBM and others, and discuss technical reasons for the fat TSVs we are seeing... I'll present solutions to this issue at the IEEE CPMT Society on Wednesday.
We at MonolithIC 3D Inc. would like to wish you and your families a Merry Christmas and a Happy New Year. Thank you for all the support and patronage you have given us in 2011. We really appreciate it.
PS: Due to the holidays, we will take a break from blogging until 5th January 2012.
Want to know what the next big technology is? Gartner periodically releases a chart called a "Hype Cycle" that tells you. In today's blog post, I'll talk about the 2011 Hype Cycle for Semiconductors...
We have a guest contribution today from Brian Cronquist, MonolithIC 3D Inc.'s VP of Technology. Brian shares his perspective on Low Temperature Wafer Direct Bonding, where an important concern is the strength of the wafer to wafer oxide to oxide bond.